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Showing below up to 250 results in range #101 to #350.
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- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Big Data Analytics Benchmarks for Ara
- Biomedical Systems on Chip
- BirdGuard
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Bluetooth Low Energy network with optimized data throughput
- Bluetooth Low Energy receiver in 65nm CMOS
- Bridging QuantLab with LPDNN
- Bringing XNOR-nets (ConvNets) to Silicon
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- Brunn test
- Build the Fastest 2G Modem Ever
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
- CLIC for the CVA6
- CMOS power amplifier for field measurements in MRI systems
- CPS Software-Configurable State-Machine
- Cell-Free mmWave Massive MIMO Communication
- Cell Measurements for the 5G Internet of Things
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Change-based Evaluation of Convolutional Neural Networks
- Channel Decoding for TD-HSPA
- Channel Estimation and Equalization for LTE Advanced
- Channel Estimation for 3GPP TD-SCDMA
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Channel Estimation for TD-HSPA
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Characterization techniques for silicon photonics-Lumiphase
- Charge and heat transport through graphene nanoribbon based devices
- Charging System for Implantable Electronics
- Circuits and Systems for Nanoelectrode Array Biosensors
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Compiler Profiling and Optimizing
- Compressed Sensing Reconstruction on FPGA
- Compressed Sensing for Wireless Biosignal Monitoring
- Compression of Ultrasound data on FPGA
- Compression of iEEG Data
- Computation of Phonon Bandstructure in III-V Nanostructures
- Configurable Ultra Low Power LDO
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating a HDMI Video Interface for PULP
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Cycle-Accurate Event-Based Simulation of Snitch Core
- DC-DC Buck converter in 65nm CMOS
- DaCe on Snitch
- Data Augmentation Techniques in Biosignal Classification
- Data Mapping for Unreliable Memories
- Deconvolution Accelerator for On-Chip Semi-Supervised Learning
- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Deep Unfolding of Iterative Optimization Algorithms
- Deep neural networks for seizure detection
- Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design and Implementation of a multi-mode multi-master I2C peripheral
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of ultra low power vision system
- Design and implementation of the front-end for a portable ionizing radiation detector
- Design of Charge-Pump PLL in 22nm for 5G communication applications
- Design of MEMs Sensor Interface
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- Design of State Retentive Flip-Flops
- Design of Streaming Data Platform for High-Speed ADC Data
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
- Design of a Fused Multiply Add Floating Point Unit
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)
- Design of a VLIW processor architecture based on RISC-V
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of an LTE Module for the Internet of Things
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design of combined Ultrasound and Electromyography systems
- Design of combined Ultrasound and PPG systems
- Design of low-offset dynamic comparators
- Design of low mismatch DAC used for VAD
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Design study of tunneling transistors based on a core/shell nanowire structures
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Designing a Power Management Unit for PULP SoCs
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Developing High Efficiency Batteries for Electric Cars
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Developing a small portable neutron detector for detecting smuggled nuclear material
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Development of a Rockfall Sensor Node
- Development of a fingertip blood pressure sensor
- Development of a syringe label reader for the neurocritical care unit
- Development of an efficient algorithm for quantum transport codes
- Development of an implantable Force sensor for orthopedic applications
- Development of statistics and contention monitoring unit for PULP
- DigitalUltrasoundHead
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Control of a DC/DC Buck Converter
- Digital Transmitter for Cellular IoT
- Digitally-Controlled Analog Subtractive Sound Synthesis
- EEG-based drowsiness detection
- EEG artifact detection for epilepsy monitoring
- EEG artifact detection with machine learning
- EEG earbud
- Edge Computing for Long-Term Wearable Biomedical Systems
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Implementation of an Active-Set QP Solver for FPGAs
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Efficient Search Design for Hyperdimensional Computing
- Efficient Synchronization of Manycore Systems (M/1S)
- Efficient TNN Inference on PULP Systems
- Efficient TNN compression
- Efficient collective communications in FlooNoC (1M)
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Elliptic Curve Accelerator for zkSNARKs
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Enabling Efficient Systolic Execution on MemPool (M)
- Enabling Standalone Operation
- Enabling Standalone Operation for a Mobile Health Platform
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Efficient SoCs
- Engineering For Kids
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Evaluating An Ultra low Power Vision Node
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Event-based navigation on autonomous nano-drones
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring NAS spaces with C-BRED
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- FFT-based Convolutional Network Accelerator
- FFT HDL Code Generator for Multi-Antenna mmWave Communication
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
- FPGA mapping of RPC DRAM
- Fast Accelerator Context Switch for PULP
- Fast Simulation of Manycore Systems (1S)
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fault-Tolerant Floating-Point Units (M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Finite Element Simulations of Transistors for Quantum Computing
- Finite element modeling of electrochemical random access memory
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Flexible Front-End Circuit for Biomedical Data Acquisition
- Floating-Point Divide & Square Root Unit for Transprecision
- Forward error-correction ASIC using GRAND
- Freedom from Interference in Heterogeneous COTS SoCs
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- GPT on the edge
- GRAND Hardware Implementation
- GSM Voice Capacity Evolution - VAMOS
- GUI-developement for an action-cam-based eye tracking device
- Glitches Reduce Listening Time of Your iPod
- Gomeza old project1
- Gomeza old project2
- Gomeza old project3
- Gomeza old project4
- Gomeza old project5
- Graph neural networks for epileptic seizure detection
- HERO: TLB Invalidation
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Hardware Accelerated Derivative Pricing
- Hardware Accelerator Integration into Embedded Linux
- Hardware Accelerator for Model Predictive Controller
- Hardware Constrained Neural Architechture Search
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Hardware Support for IDE in Multicore Environment
- Herschmi
- High-Resolution, Calibrated Folding ADCs
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- High-speed Scene Labeling on FPGA
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- High Performance Cellular Receivers in Very Advanced CMOS
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hypervisor Extension for Ariane (M)
