Pages with the most revisions
From iis-projects
Showing below up to 50 results in range #301 to #350.
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- Wireless EEG Acquisition and Processing (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format (8 revisions)
- Fault-Tolerant Floating-Point Units (M) (8 revisions)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (8 revisions)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- BCI-controlled Drone (8 revisions)
- OTDOA Positioning for LTE Cat-M (8 revisions)
- ASIC Implementation of Jammer Mitigation (8 revisions)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 revisions)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- Hardware/software co-programming on the Parallella platform (8 revisions)
- Ultra Low-Power Oscillator (8 revisions)
- Streaming Layer Normalization in ITA (M/1-2S) (8 revisions)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Putting Together What Fits Together - GrÆStl (7 revisions)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (7 revisions)
- Ibex: FPGA Optimizations (7 revisions)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (7 revisions)
- Spiking Neural Network for Autonomous Navigation (7 revisions)
- RazorEDGE: An Evolved EDGE DBB ASIC (7 revisions)
- Predictable Execution (7 revisions)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (7 revisions)
- EEG earbud (7 revisions)
- IoT Turbo Decoder (7 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (1M) (7 revisions)
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (7 revisions)
- LTE IoT Network Synchronization (7 revisions)
- Compressed Sensing for Wireless Biosignal Monitoring (7 revisions)
- Internet of Things Network Synchronizer (7 revisions)
- Fault Tolerance (7 revisions)
- Digital Audio Interface for Smart Intensive Computing Triggering (7 revisions)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (7 revisions)
- Outdoor Precision Object Tracking for Rockfall Experiments (7 revisions)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (7 revisions)
- Gomeza old project5 (7 revisions)
- Transforming MemPool into a CGRA (M) (7 revisions)
- Development of an implantable Force sensor for orthopedic applications (7 revisions)
- Indoor Positioning with Bluetooth (7 revisions)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities (7 revisions)
- Extending the HERO SDK to support asynchronous offloading (M/1-3S) (7 revisions)
- Ultra-low power processor design (7 revisions)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S) (7 revisions)
- Efficient NB-IoT Uplink Design (7 revisions)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (7 revisions)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (7 revisions)
- Satellite Internet of Things (7 revisions)
