List of redirects
From iis-projects
Showing below up to 100 results in range #51 to #150.
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- Energy Efficient AXI Inteface to Analog Circuit → Energy Efficient AXI Inteface to serial link physical layer
- Energy Efficient AXI Inteface to Serial Link Physical Layer → Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient AXI Inteface to serial link physical layer → Energy Efficient AXI Inteface to Serial Link Physical Layer
- Energy Efficient Heterogeneous MCU Platforms → Gomeza old project1
- Energy Efficient Heterogeneous Sensor Nodes → Gomeza old project3
- Energy Effiecient Serial Link → Energy Efficient Serial Link
- Energy Netural Multi Sensors Wearable Device → Energy Neutral Multi Sensors Wearable Device
- Energy effiecient serial link → Energy Effiecient Serial Link
- Erg → FPGA mapping of RPC DRAM
- EvaLTE → EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- EvalEDGE → EvalEDGE: A 2G Cellular Transceiver FMC
- Event Driven Spike sorting engine → Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Fast Data Interface → Data Interface: SPI to PC Bridge for ASICs
- Fast Wakeup → Fast Wakeup From Deep Sleep State
- Fault Tolerant OpenPULP System for Critical Spacial Applications → PULP in space - Fault Tolerant PULP System for Critical Space Applications
- First ASIC Realization For A New HSPA/HSPA+ Detector → Design and VLSI Implementation of a Constrained-Viterbi Algorithm for 3GPP TD-HSPA
- Flexible Electronic Systems and Epidermal Devices → Flexible Electronic Systems and Embedded Epidermal Devices
- GPU-Accelerated Nanoelectronic Device Simulations → Investigation of Redox Processes inCBRAM
- HERO: TLB Coherency → HERO: TLB Invalidation
- Heterogeneous Acceleration Systems → Heterogeneous SoCs
- Heterogeneous Microcontroller for Batteryless Applications → Energy Efficient Heterogeneous Sensor Nodes
- High-Definition 3D Ultrasound Imaging ASIC → Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
- High-Throughput Next Generation Turbo Decoders → ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- High performance continous-time Delta-Sigma ADC for magnetic resonance imaging → High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High performance continous-time Delta-Sigma ADC for mobile communications → High performance continous-time Delta-Sigma ADC for magnetic resonance imaging
- Implementation of a Heterogeneous System for Image Processing on an FPGA (M) → Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Improved Reacquisition for the Cellular IoT → Improved Reacquisition for the 5G Cellular IoT
- Integrating Hardware Accelerators into Snitch 1S → Integrating Hardware Accelerators into Snitch (1S)
- Integration and Implementation of Alibaba’s T-Head CLIC Interrupt Controller in PULP SoC → Integration and implementation of PULP’s CLIC in PULPissimo
- Integration and implementation of PULP’s CLIC in PULPissimo → PULP’s CLIC extensions for fast interrupt handling
- Interference Detection and Cancellation for EC-GSM-IoT → Interference Cancellation for EC-GSM-IoT
- Investigation of Quantization Strategies for Retentive Networks → Investigation of Quantization Strategies for Retentive Networks (1S)
- Investigation of Redox Processes inCBRAM → Investigation of Redox Processes in CBRAM
- LED on Timer: On-chip Oscillator Tuned by Light to Compensate Temperature Variation → Precise Ultra-low-power Timer
- LTE Testbed Design for the Internet-of-Things → Synchronisation and Cyclic Prefix Handling For LTE Testbed
- LightProbe - WIFI extension → LightProbe - WIFI extension (PCB)
- Linear Solvers for Image and Video Processing Applications → DMA Streaming Co-processor
- Long Range Communication For IoT Applications → Gomeza old project5
- MAD → Real-Time Stereo to Multiview Conversion
- Mesh generation for the simulation of Li-ion batteries on supercomputers using GPUs → Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
- Mmaxim → User:Mmaxim
- Modular Spiking Neural Network Accelerator → Event-Driven Convolutional Neural Network Modular Accelerator
- Multi issue OoO Ariane Backend → Multi issue OoO Ariane Backend (M)
- My page → High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
- NextGenerationChannelDecoder → Next Generation Channel Decoder
- Next Gen Digital Ultrasound Imaging Systems (Industry Collaboration) → Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
- Non-blocking Algorithms in real-time Operating Systems → Non-blocking Algorithms in Real-Time Operating Systems
- Open Source Basestation for Evolved EDGE → Open Source Baseband Firmware for 2G Cellular Networks
- Open Source GSM Phone Call → Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Optical Weights for Photonic Neural Networks → Finite Element Simulations of Transistors for Quantum Computing
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture → Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optimization of a Binary Feature Extraction Core using Approximation → Accelerator for Boosted Binary Features
- OsmoPHY: An Open-Source Physical Layer Development Framework → MatPHY: An Open-Source Physical Layer Development Framework
- Outdated pitches → Category:Outdated pitches
- Parallel bandstructure calculation of nanostructures → Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Peak-to-average power reduction → Peak-to-average power Reduction
- Physical Implementation of MemPool, PULP's Manycore System → Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Quest for the smallest Turing-complete core (2-3G) → Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- RF SoCs → RF SoCs for the Internet of Things
- RF SoCs for the Internet of Things → Wireless Communication Systems for the IoT
- RISC-V based Implementation of Secure Ranging → RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Radiation Testing Board → Radiation Testing of a PULP ASIC
- RazorEDGE → RazorEDGE: An Evolved EDGE DBB ASIC
- RazorEDGE: An Evolved EDGE PHY ASIC → RazorEDGE: An Evolved EDGE DBB ASIC
- Runtime partitioning of L1 memory in Mempool → Runtime partitioning of L1 memory in Mempool (1-2S/B)
- Runtime partitioning of L1 memory in Mempool (1-2S/B) → Runtime partitioning of L1 memory in Mempool (M)
- SSR combined with FREP in LLVM/Clang (M/1-3S) → LLVM and DaCe for Snitch (1-2S)
- Self Powered Radioactivity Sensor Nodes → Gomeza old project2
- Simulation of novel solar cell architectures for higher energy efficiency → Development of an efficient algorithm for quantum transport codes
- Simulation of the optical properties of nanostructured solar cells → Ab-initio modeling of ballistic thermal transport
- Snitch meets iCE40 (1-2S/B) → A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Source contact engineering in 2D materials MOSFET to achieve sub-60 mV/decade transistors → Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Stable nonvolatile resistance switching (NVRS) in single-layer 2D Materials → Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- StoneEDGE → StoneEDGE: An Evolved EDGE PHY ASIC
- StoneEDGE: An Evolved EDGE PHY ASIC → StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Streaming Integer Extensions for Snitch (M) → Streaming Integer Extensions for Snitch (M/1-2S)
- System Analysis and VLSI Design of LTE Cat-M Baseband Processing → System Analysis and VLSI Design of LTE NB-IoT Baseband Processing
- System Analysis and VLSI Design of LTE NB-IoT Baseband Processing → System Analysis and VLSI Design of NB-IoT Baseband Processing
- System on Chips for IoTs → RF SoCs for the Internet of Things
- Towards Self Sustainable UAV → Towards Self Sustainable UAVs
- Tracer Debugger for custom RISC-V Core → Trace Debugger for custom RISC-V Core
- Training and Deploying Next-Generation Neural Networks on Microcontrollers → Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Training and Deploying Tiny Mixed-Precision Networks → Training and Deploying Next-Generation Neural Networks on Microcontrollers
- Transmitter and Testbed Development for TD-SCDMA → Digital Transmitter Mobile Communications
- Universal Stream Semantic Registers for Snitch (1S) → Streaming Integer Extensions for Snitch (M)
- Using piezoelectricity in monolayer 2D materials to build future nanoscale devices → Characterization techniques for silicon photonics
- VLSI Implementation of a Channel Shortener → VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- Voice Codec High Level Synthesis → Digital Audio High Level Synthesis
- WCDMA/HSPA+ Modem System Design, Implementation, and Testing → WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- Zksnark → Elliptic Curve Accelerator for zkSNARKS
- User:Aguacil → Taimir Aguacil
- User:Akurth → Andreas Kurth
- User:Badawi → Karim Badawi
- User:Balasr → Robert Balas
- User:Belfanti → Sandro Belfanti
- User:Chrikell → Christoph Keller
- User:Cleitne → Christoph Leitner
- User:Cosandre → Andrea Cossettini
- User:Felber → Norbert Felber
- User:Fschuiki → Fabian Schuiki
