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- [[File:Ultra-low power processor design.jpg|thumb]] ...use a state of the art 28nm SOI process to evaluate the performance of the processor.10 KB (1,669 words) - 19:01, 30 January 2014
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2 KB (302 words) - 12:09, 26 March 2015
- ...le:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]] ...icient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability.2 KB (344 words) - 10:30, 5 November 2019
- ...is usually attached as a fixed-function-unit to a heterogeneous multicore processor. The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod1 KB (210 words) - 08:34, 20 January 2021
- ...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this ...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.2 KB (265 words) - 08:34, 20 January 2021
- ...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r : Interest in processor design3 KB (443 words) - 13:10, 2 November 2015
- ...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp1 KB (229 words) - 18:01, 29 March 2017
- The goal of this project is to design a processor using existing components and port it to an FPGA-based prototyping platform2 KB (347 words) - 17:58, 14 April 2016
- ...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]3 KB (377 words) - 10:25, 5 November 2019
- ...d system architecture will be developed around an Ultra low power parallel processor developed at IIS to show to be ideally suited to interface4 KB (518 words) - 11:40, 2 February 2018
- ...ery effectively, providing better energy efficiency than a general purpose processor for applications that fit its execution model. ...ner, Luca Benini. Ara: A 1GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22nm FD-SOI. [https://doi.or4 KB (627 words) - 14:42, 29 October 2020
- ...classes motor-imagery and often they are not implemented in a neuromorphic processor, and none of them are presenting a whole system from the data acquisition t6 KB (815 words) - 20:02, 10 March 2024
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0 bytes (0 words) - 19:24, 2 November 2020
- ...nally, it can support he ‘M’ and ‘F’ extension through a custom co-processor interface. However, currently, there is no support for domain-specific inst ...the OpenHW Group [<nowiki/>[[#ref-CV32E40P|7]]]. It is a 32-bit in-order processor with 4 pipeline stages. In contrast to Snitch, it features custom DSP instr9 KB (1,311 words) - 00:08, 13 March 2021
- <!-- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) --> The aim of this project is to design a reconfigurable vector processor cluster for area-optimized, yet compute and energy-efficient, radar signal5 KB (651 words) - 20:42, 22 November 2022
Page text matches
- [[File:Ultra-low power processor design.jpg|thumb]] ...use a state of the art 28nm SOI process to evaluate the performance of the processor.10 KB (1,669 words) - 19:01, 30 January 2014
- At the IIS we are working on an ultra low-power multi-processor (PULP) multi-processor shared-memory cluster.3 KB (409 words) - 10:52, 27 March 2014
- [[Category:Processor]]4 KB (397 words) - 15:44, 14 February 2023
- [[Category:Processor]]6 KB (741 words) - 18:14, 21 July 2023
- At the IIS we are working on an ultra low-power multi-processor processing applications that can be included in the multi-processor3 KB (407 words) - 10:57, 5 November 2019
- #REDIRECT [[Digital Audio Processor for Cellular Applications]]63 bytes (7 words) - 16:36, 3 August 2015
- ...ry simple tasks at a very low power budget, without having to power up the processor. Together with a low power timer, the state-machine forms what we call the3 KB (418 words) - 11:24, 10 November 2017
- ...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi ...referred algorithm in hardware such that it can be integrated in the multi-processor platform.3 KB (377 words) - 10:58, 21 February 2018
- GrÆStl cryptographic co-processor. Bottom: Photo of the manufactured Chameleon chip, host- ...r to accelerate the computations of the cryptographic primitives. Both the processor and GrÆStl were ported onto a low-cost FPGA and finally a comparison betwe3 KB (434 words) - 12:01, 26 March 2015
- [[Category:Processor]]5 KB (597 words) - 12:56, 4 December 2021
- ...e physical baseband receiver that is typically implemented on the baseband processor, assisted by accelerator blocks in dedicated hardware including TPU, digita3 KB (360 words) - 14:14, 27 May 2015
- ...cessor. The decoding of the RLC blocks takes place on a PHY Digital Signal Processor (DSP) and an accelerator attached to it.3 KB (397 words) - 14:12, 27 May 2015
- ...n in terms of usage of hardware accelerators, heterogeneous or homogeneous processor cores and of communication or network-on-chip that has to be implemented fo4 KB (568 words) - 12:48, 9 February 2015
- ...le:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]] ...icient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability.2 KB (344 words) - 10:30, 5 November 2019
- ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp6 KB (941 words) - 11:29, 5 February 2016
- An application-specific instruction-set processor (ASIP) tailored to In addition to the "pseudo-processor-controlled approach", the2 KB (326 words) - 12:26, 26 March 2015
- :[1] [http://arxiv.org/abs/1404.3162 A Signal Processor for Gaussian Message Passing]2 KB (236 words) - 09:46, 12 October 2017
- * [http://asic.ethz.ch/2021/Marsellus.html Marsellus] IoT processor based on PULPopen * [http://asic.ethz.ch/2021/Kraken.html Kraken] IoT Processor with 3 accelerators based on PULPopen. Total of 9x 32bit RI5CY cores.10 KB (1,563 words) - 10:09, 19 August 2022
- [[Category:Processor]]3 KB (449 words) - 12:12, 4 November 2019
- ...mplementation of the OpenRisc was completed as part of a [[Ultra-low power processor design | previous semester thesis]]. We are already using this core in our ...e, during this wake up it will store the incoming message and allowing the processor to access the incoming data and react to it.4 KB (667 words) - 15:23, 23 December 2016
- ...is usually attached as a fixed-function-unit to a heterogeneous multicore processor. The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod1 KB (210 words) - 08:34, 20 January 2021
- ...sed measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recor ...he field of wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless t3 KB (369 words) - 18:11, 1 March 2023
- ...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this ...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.2 KB (265 words) - 08:34, 20 January 2021
- Dynamic Reliability Management (DRM) techniques aims at trading-off processor performance with lifetime at run-time by modulating the working temperature4 KB (573 words) - 17:24, 9 February 2015
- [[Category:Processor]]3 KB (335 words) - 14:20, 4 November 2019
- ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp9 KB (1,289 words) - 19:45, 24 March 2015
- operating voltage, the clock rate of such a processor will be between3 KB (466 words) - 19:37, 3 March 2016
- [[Category:Processor]]3 KB (374 words) - 16:24, 30 October 2020
- ...power platform similar to the Raspberry Pi. It features a dual-core ARM A9 processor running Linux, a powerful FPGA and a 16-core accelerator chip called "Epiph3 KB (501 words) - 14:26, 2 September 2015
- # Characterization of the time/memory overhead incurred by the inter-processor communication.3 KB (431 words) - 18:04, 28 January 2017
- ...e the backbone of big data and scientific computing. While general purpose processor architectures such as Intel's x86 provide good performance across a wide va2 KB (275 words) - 17:05, 24 November 2023
- #REDIRECT [[DMA Streaming Co-processor]]40 bytes (4 words) - 18:10, 14 April 2016
- ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance. ...n allows the programmer to share virtual address pointers between the host processor and the accelerator in a completely transparent manner, it still requires t5 KB (716 words) - 13:43, 29 November 2019
- ...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r : Interest in processor design3 KB (443 words) - 13:10, 2 November 2015
- ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp8 KB (1,145 words) - 11:30, 5 February 2016
- ...the types of layer in the ConvNet, interaction between a flow controlling processor (e.g. an ARM core on a Xilinx Zynq) and the programmable logic is foreseen. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp8 KB (1,197 words) - 18:18, 29 August 2016
- ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.4 KB (585 words) - 17:57, 7 November 2017
- ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.4 KB (554 words) - 17:57, 7 November 2017
- ...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp1 KB (229 words) - 18:01, 29 March 2017
- [[Category:Processor]]4 KB (471 words) - 11:13, 3 May 2018
- The goal of this project is to design a processor using existing components and port it to an FPGA-based prototyping platform2 KB (347 words) - 17:58, 14 April 2016
- #REDIRECT [[Baseband Processor Development for 4G IoT]]55 bytes (7 words) - 14:46, 28 May 2015
- ...X1 board to get best performance transferring data from the sensor to the processor. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp8 KB (1,176 words) - 16:26, 30 October 2020
- [[File:lteTestbed.jpg|thumb|Figure 2: LTE testbed with digital baseband and processor on an FPGA and RF-IC on the [[evaLTE]] FMC module.]]2 KB (245 words) - 10:39, 6 November 2017
- ...ailable before the power outage, i.e., the supply voltage is dropping, the processor state can be saved only when a power outage is imminent and thus superfluou Both scenarios require a mechanism to save a snapshot of the processor state in a non-volatile memory. This mechanism is commonly known as '''hibe3 KB (390 words) - 11:59, 20 June 2016
- ...ation to be retained between two calls, it is not acceptable for an entire processor core idling, for example while waiting for a DMA transfer to be completed.2 KB (364 words) - 09:34, 25 July 2017
- ...ocks of any processing system, in fact most of the performance of a modern processor is determined by its ability to efficiently store and retrieve data. For IC5 KB (769 words) - 15:54, 23 May 2018
- ...PMU should schedule the system tasks in an optimal way and wakeup the main processor if required. Naturally, the iPMU should consume as little power as possible2 KB (292 words) - 11:40, 2 June 2021
- ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp5 KB (747 words) - 18:04, 29 August 2016
- ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp9 KB (1,263 words) - 18:52, 12 December 2016
- ...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]3 KB (377 words) - 10:25, 5 November 2019
- ...n are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is enough. A very simple 2-3stag ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]3 KB (384 words) - 17:24, 21 August 2019
- [[Category:Processor]]3 KB (450 words) - 11:43, 13 November 2018
- ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.5 KB (711 words) - 10:27, 5 November 2019
- [[Category:Processor]]3 KB (402 words) - 15:31, 13 April 2016
- [[Category:Processor]]3 KB (418 words) - 14:01, 13 November 2020
- ...ftware co-design in which part of the algorithm will be mapped onto a PULP processor while computational complex tasks are realized in dedicated hardware accele [[Category:Processor]]4 KB (555 words) - 16:36, 23 May 2018
- ...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi ...multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.2 KB (346 words) - 10:26, 5 November 2019
- ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.5 KB (712 words) - 17:57, 7 November 2017
- ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.6 KB (866 words) - 13:43, 29 November 2019
- ...sensors and one or two algorithms will be implemented directly in the PULP processor. One of main challenging goal of the project is bring these algorithm in an * programming the PULP processor for the specific application, otimize the code and carry out in-field testi4 KB (631 words) - 11:39, 21 July 2017
- ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp10 KB (1,357 words) - 16:25, 30 October 2020
- *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]3 KB (351 words) - 16:19, 27 February 2018
- ...m the ADC HW-FIFO to SW-FIFO at kernel-space and the real-time embedded co-processor ([http://beagleboard.org/pru PRU]) for post-processing of the data-stream. *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet]3 KB (394 words) - 16:19, 27 February 2018
- *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]3 KB (440 words) - 16:15, 1 September 2017
- ...mic power controller algorithm is then needed to always configure the PULP processor in the most energy efficient point.3 KB (348 words) - 15:31, 13 September 2016
- ...ps (SoCs) often consist of various independent subsystems (e.g., different processor cores, hardware accelerators, analog IPs, etc), each with its own clocking3 KB (389 words) - 11:20, 14 September 2016
- while the DBB processing can be done in a CPU, a Digital Signal Processor (DSP), an Appli- Open-RISC processor. The processor can be used to control the baseband blocks as well as to6 KB (900 words) - 16:58, 7 May 2018
- ...ystems Laboratory (IIS) we have been working on a Parallel Ultra-Low Power Processor (PULP) System for the past two years. PULP is intended to be used for near-9 KB (1,427 words) - 18:36, 5 September 2019
- [[Category:Processor]]3 KB (392 words) - 14:17, 5 April 2022
- ...ger part of the affected digital baseband processing is mapped to a RISC-V processor, most of the work throughout the project requires embedded C coding, with s [[Category:Processor]]3 KB (462 words) - 13:54, 13 November 2020
- [[Category:Processor]]4 KB (467 words) - 13:38, 10 November 2020
- ...-power devices such as the PULP chips we develop at IIS. However, a vector processor shares many similarities with custom-designed HW accelerators that we have [[Category:Processor]]6 KB (916 words) - 15:50, 7 December 2018
- [[Category:Processor]]4 KB (546 words) - 11:33, 17 April 2020
- [[Category:Processor]]3 KB (372 words) - 20:22, 1 April 2019
- ...project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient controller based on principles of HD computing, an [[Category:Processor]]3 KB (401 words) - 19:08, 29 January 2021
- ...it should not have any impact on the maximum achievable clock speed of the processor. Another challenge in designing a trace debugger is the fact that on-chip R * Basic knowledge of computer architecture/processor design as thought in the Energy-Efficient Parallel Computing Systems for Da5 KB (729 words) - 11:27, 11 December 2018
- [[Category:Processor]]3 KB (366 words) - 15:39, 10 November 2020
- architectures, where a powerful host processor is coupled to massively pushing for an architectural model where the host processor and the6 KB (865 words) - 12:16, 17 November 2017
- [[Category:Processor]]3 KB (409 words) - 13:58, 9 November 2017
- ...ea footprint. One way to reduce the area is the sharing of memory with the processor cluster. The final design can either be mapped to an FPGA, or an ASIC.3 KB (427 words) - 09:37, 14 September 2018
- [[Category:Processor]]4 KB (460 words) - 21:42, 30 January 2018
- ...ront ends, RF-transceiver, digital baseband processing, and an application processor. Such a RF System-on-Chip (RF-SoC) is mandatory to achieve minimal manufact3 KB (344 words) - 01:45, 10 February 2021
- [[Category:Processor]]3 KB (393 words) - 13:53, 13 November 2020
- ...n a general purpose microcontroller platform and on our own PULP multicore processor platforms. But as applications and research is changing fast, these impleme3 KB (317 words) - 14:40, 14 April 2021
- HERO combines an ARM Cortex-A host processor with a scalable, configurable, and extensible FPGA implementation of a prog3 KB (421 words) - 18:41, 28 October 2020
- ...e-core microcontrollers (i.e. Arm-Cortex-M family) or MultiCore (i.e. PULP Processor designed in IIS)5 KB (625 words) - 16:59, 10 November 2020
- ...sy reconfigurability of the oscillator with an external microcontroller or processor, while having outputs based on the I2S protocol that directly connect with [[Category:Processor]]5 KB (621 words) - 18:09, 9 October 2022
- [[Category:Processor]]5 KB (549 words) - 12:35, 28 November 2022
- ==Extremely Resilient HD Processor== ...project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient controller based on principles of HD computing, an10 KB (1,341 words) - 10:46, 25 April 2018
- [[Category:Processor]]3 KB (354 words) - 16:06, 6 May 2019
- [[Category:Processor]]5 KB (599 words) - 09:03, 21 December 2017
- [[Category:Processor]]3 KB (329 words) - 11:43, 20 August 2021
- ...d system architecture will be developed around an Ultra low power parallel processor developed at IIS to show to be ideally suited to interface4 KB (518 words) - 11:40, 2 February 2018
- ...e exploring deep integration of analog precision circuits with the digital processor of the PULP family, both workforce and expertise converge on the VivoSoC pr2 KB (327 words) - 19:55, 22 February 2018
- [[Category:Processor]]4 KB (597 words) - 19:15, 9 March 2020
- [[Category:Processor]]4 KB (661 words) - 08:38, 20 January 2021
- [[Category:Processor]]3 KB (381 words) - 14:17, 28 January 2023
- ...sed measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recor2 KB (311 words) - 12:02, 5 December 2018
- [[Category:Processor]]4 KB (566 words) - 15:50, 9 February 2021