Search results

Create the page "FPGA & Digital ASIC Design" on this wiki! See also the search results found.

• An FPGA-Based Testbed for 3G Mobile Communications Receivers
  In this project you will develop and FPGA-based testbed for the 3G standard TD-SCDMA, with the option to extend it with an ASIC in the
  1 KB (169 words) - 16:42, 9 December 2015
• Vector Processor for In-Memory Computing
  : Interest in processor design : 40% Architecture Design & Exploration
  3 KB (443 words) - 13:10, 2 November 2015
• FFT-based Convolutional Network Accelerator
  ...The focus of this work is on speeding up this step by creating an ASIC or FPGA accelerator to perform this step faster and more power-efficiently in the f [[Category:Digital]] [[Category:FPGA]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:2015]]
  8 KB (1,145 words) - 11:30, 5 February 2016
• High-speed Scene Labeling on FPGA
  ...and a display or an ethernet adapter. As opposed to an ASIC project, such FPGA and hardware-software codesign work is much more applicable in industry and [[Category:Digital]] [[Category:FPGA]] [[Category:Completed]] [[Category:2016]] [[Category:Semester Thesis]]
  8 KB (1,197 words) - 18:18, 29 August 2016
• Michael Muehlberghuber
  * Digital design, design flows, ASIC design * ASIC and FPGA design of cryptographic hardware
  1 KB (139 words) - 12:39, 7 November 2017
• Time Synchronization for 3G Mobile Communications
  ...er working with FPGAs, you can alternatively implement the algorithm on an FPGA and test it in real-time and with real data on our 3G testbed. [[Category:Digital]]
  3 KB (420 words) - 11:22, 14 April 2016
• Spatio-Temporal Video Filtering
  * '''[[Design Review]]''' ...esis]] [[Category:Hot]] [[Category:Completed]][[Category:ASIC]] [[Category:FPGA]] [[Category:2016]]
  3 KB (373 words) - 19:40, 14 April 2016
• Switched Capacitor Based Bandgap-Reference
  ...re important building blocks in analog and mixed-signal integrated circuit design. The classical Band Gap-Reference combines the negative VBE temperature coe ...is offers the possibility to study main aspects of analog and mixed-signal design, such as noise, linearity, matching, small signal-concepts and power consum
  4 KB (471 words) - 11:13, 3 May 2018
• Compressed Sensing vs JPEG
  ...le step and close to the sensor. CS can be implemented very efficiently in digital logic, and the encoding (or compression) step can be performed with very li ...al ASIC (Application Specific Integrated Circuit) or the implementation in FPGA (Field-Programmable Gate Array).
  2 KB (343 words) - 10:24, 14 September 2016
• Compressed Sensing for Wireless Biosignal Monitoring
  ...le step and close to the sensor. CS can be implemented very efficiently in digital logic, and the encoding (or compression) step can be performed with very li ...V4.0_Homer.html] including analog front-end, analog-to-digital conversion, digital signal processing and a compressed sensing encoder stage.
  2 KB (353 words) - 08:35, 20 January 2021
• Improving our Smart Camera System
  [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]] * for the student(s) to get to know the FPGA design flow from specification through architecture exploration to implementation,
  8 KB (1,176 words) - 16:26, 30 October 2020
• FPGA System Design for Computer Vision with Convolutional Neural Networks
  [[File:origami-fpga-system.png|400px|thumb]] ...e Origami accelerator to run efficiently on the FPGA, hardware/software-co-design configuring memory and DMA controllers, building small IP cores to finish t
  3 KB (397 words) - 18:17, 29 August 2016
• Internet of Things Network Synchronizer
  ...he [[stoneEDGE]] project and the [[evalEDGE]] RF board. Synthesis and ASIC design are also an option. [[Category:Digital]]
  4 KB (582 words) - 20:00, 26 September 2017
• Rethinking our Convolutional Network Accelerator Architecture
  [[Category:Digital]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Not available]] [[Category:Semester Thesis]] [[Category:Master ...hitecture exploration to implementation, functional verification, back-end design and silicon testing.
  9 KB (1,263 words) - 18:52, 12 December 2016
• Non-binary LDPC Decoder for Deep-Space Optical Communications
  ...master project the complete decoder could be implemented and tested on an FPGA. : 30% RTL Design
  2 KB (290 words) - 16:05, 21 July 2016
• Turbo Equalization for Cellular IoT
  ...hm to an HDL implementation and synthesize it either towards an FPGA or an ASIC implementation in order to analyze the hardware complexity of the developed * '''[[Design Review]]'''
  3 KB (450 words) - 11:43, 13 November 2018
• PULPonFPGA: Hardware L2 Cache
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [4] capable of implementing PULP [5] with 4 to 8 clusters and a total of 32 ...mplementation on the Xilinx Virtex-7 FPGA but if desired, an ASIC back-end design can also be implemented.
  5 KB (711 words) - 10:27, 5 November 2019
• NextGenChannelDec
  ...developed RTL code. The work concludes with a comparison of the generated ASIC with literature and especially with implementations of other channel decode : 30% Architectural Design
  3 KB (402 words) - 15:31, 13 April 2016
• Next Generation Channel Decoder
  ...developed RTL code. The work concludes with a comparison of the generated ASIC with literature and especially with implementations of other channel decode : 30% Architectural Design
  3 KB (418 words) - 14:01, 13 November 2020
• Bringing XNOR-nets (ConvNets) to Silicon
  [[Category:Digital]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category:2016]] ...hitecture exploration to implementation, functional verification, back-end design and silicon testing.
  10 KB (1,357 words) - 16:25, 30 October 2020
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  1. design a low-power interface in standard cell technology that could be used to lin ...the cochleaLP sensor. In this target, the interface resides on a low-power FPGA (e.g. an a MicroSemi IGLOO).
  9 KB (1,427 words) - 18:36, 5 September 2019
• LightProbe
  ...hardware (phone, tablet, workstation) for post-processing over a standard digital link as simple as a standard peripheral, like a camera. * Implementation of processing subunits: Hardware design FPGA/ASIC (VHDL/HLS)
  2 KB (254 words) - 14:14, 31 October 2020
• Single-Bit-Synapse Spiking Neural System-on-Chip
  ...IBM TrueNorth architecture [Merolla14], a homogeneous fabric of 1 million digital spiking neurons that can be used for visual classification at a very low po ...omize and use this neuron to create a scalable spiking neuron for FPGA and ASIC targets. Whereas that work marked a starting point for the development of a
  7 KB (1,000 words) - 12:22, 13 January 2017
• Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  [[Category:Software]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category:2016] Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the rel
  6 KB (823 words) - 08:36, 20 January 2021
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
  : 40% Architecture Design * '''[[Design Review]]'''
  4 KB (467 words) - 13:38, 10 November 2020
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  [[Category:Digital]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category:2016]] ...ccess which can be exploited by an application-specific integrated circuit ASIC, in contrast to CPUs or even GPUs.
  6 KB (842 words) - 08:37, 20 January 2021
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
  ...ly quantized CNNs (''YodaNN'' [Andri2017]), in the Ergo project we want to design a PULP-based entire computation cluster around a set of deep, fast and low- ...er the QNE should be an extension to the currently existing XNE or a novel design based on the same building blocks.
  6 KB (949 words) - 13:41, 10 November 2020
• Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  * AER-SPI interface, implemented on an ULP FPGA development board (see [http://iis-projects.ee.ethz.ch/index.php/Interfacin AER-SPI interface is a custom IP hosted on an ULP FPGA development board. It efficiently collects and stores the data produced asy
  7 KB (1,025 words) - 19:52, 30 May 2017
• A computational memory unit using phase-change memory devices
  ...t. The ideal candidate should be well versed in digital and analog circuit design with hands on experimental experience. A strong mathematical background and : Basics of Digital and Analog Design (VLSI1/AIC)
  4 KB (546 words) - 11:33, 17 April 2020
• Deep Learning for Brain-Computer Interface
  [[Category:Digital]] [[Category:FPGA]]
  3 KB (372 words) - 20:22, 1 April 2019
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
  In this project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient cont : 40% Architecture Design
  3 KB (401 words) - 19:08, 29 January 2021
• Trace Debugger for custom RISC-V Core
  # Specification, RTL design and host software development of a trace debugger for one of our custom RIS # FPGA evaluation of your implementation.
  5 KB (729 words) - 11:27, 11 December 2018
• Efficient Search Design for Hyperdimensional Computing
  ...arch operations in HD computing. You would develop RTL implementation with FPGA prototyping. : Architecture Design
  3 KB (366 words) - 15:39, 10 November 2020
• Creating a HDMI Video Interface for PULP
  ...ted native differential signalling this is easier to implement in a purely digital fashion. ...ip (or external) frame-buffer. At first your implementation will target an FPGA (Xilinz Zynq) implementation as a first prototype but upon successful compl
  4 KB (603 words) - 09:37, 10 July 2018
• BigPULP: Multicluster Synchronization Extensions
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 : 50% Implementation (VHDL, FPGA/ASIC Design, C)
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 : 50% Implementation (C, VHDL, FPGA/ASIC Design)
  6 KB (801 words) - 15:05, 23 August 2018
• Hyper Meccano: Acceleration of Hyperdimensional Computing
  * '''[[Design Review]]''' [[Category:Digital]]
  3 KB (409 words) - 13:58, 9 November 2017
• IoT Turbo Decoder
  [[File:High Throughput Turbo Decoder Design.png|400px|thumb|A previous, high throughput, Turbo Decoder developed at IIS ...processor cluster. The final design can either be mapped to an FPGA, or an ASIC.
  3 KB (427 words) - 09:37, 14 September 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  ...phys.ethz.ch/ Physics Department of ETH Zurich]. If you are experienced in FPGA programming (VHDL) and want to spice up your knowledge with a real world, t ...puts that connect to the AC701’s FMC connector and get familiar with the design of the unit and it’s purpose.
  4 KB (460 words) - 21:42, 30 January 2018
• Wireless Communication Systems for the IoT
  ...ns, which incorporate analog sensor / actuator front ends, RF-transceiver, digital baseband processing, and an application processor. Such a RF System-on-Chip ...an RF SoC design is the hardware- and energy-efficient realization of the digital baseband algorithms in which we constantly offer various semester and maste
  3 KB (344 words) - 01:45, 10 February 2021
• HERO: TLB Invalidation
  ...evaluation platform combines a modern ARMv8 multicluster CPU with a Xilinx FPGA capable of implementing PULP with up to 8 clusters and a total of 64 cores. : 50% Design and Implementation (SystemVerilog, C, FPGA/ASIC Design)
  6 KB (796 words) - 17:19, 18 November 2019
• Beat Cadence
  ...g a highly integrated SoC for the IoT in including RF front-end, dedicated digital baseband hardware, and a CPU system. But, expected area and therefore cost ...s project is a perfect opportunity to get to know state-of-the-art HLS and digital architecture approaches and to show that a human is still better than a mac
  1 KB (217 words) - 11:01, 18 March 2019
• Aliasing-Free Wavetable Music Synthesizer
  [[File:Iip_syneth.png|300px|thumb|SYNƎTH wavetable synthesizer ASIC project. ]] ...integrated circuits (ASICs). Furthermore, it is practically challenging to design wavetable oscillators that do not produce aliasing artifacts, especially if
  5 KB (621 words) - 18:09, 9 October 2022
• Modular Frequency-Modulation (FM) Music Synthesizer
  ...a large number of freely programmable operators resulting in endless sound-design possibilities compared to existing FM synthesizers. ...he architecture in a modern CMOS process and send the modular FM synthesis ASIC to fabrication.
  5 KB (549 words) - 12:35, 28 November 2022
• Hyperdimensional Computing
  * '''Algorithmic''' design and optimizations (Matlab/ Python) * '''Hardware and digital architecture''' design
  10 KB (1,341 words) - 10:46, 25 April 2018
• CMOS power amplifier for field measurements in MRI systems
  .... The thesis offers the possibility to study main aspects of analog and RF design, such as noise, linearity, matching, small signal-concepts and power consum : 50% Design
  3 KB (354 words) - 16:06, 6 May 2019
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...ecord and display the signal processing results. The interface between the FPGA and ADC board, DDR3 and PC is already implemented. ...with signal processing in the context of quantum computing experiments and FPGA hardware implementations
  5 KB (599 words) - 09:03, 21 December 2017
• Inductive Charging Circuit for Implantable Devices
  : 30% Design * '''[[Design Review]]'''
  3 KB (329 words) - 11:43, 20 August 2021
• Extend the RI5CY core with priviledge extensions
  ...plus custom instructions that have been designed to efficiently deal with digital-signal-processing applications typical for near-sensor systems. ...lace. The student will focus especially on the memory exeptions and in the design of an MMU. The student is required to extend the testbench to emulated the
  4 KB (661 words) - 08:38, 20 January 2021
• Wearables for Sports and Life Enhancement
  : 40% ASIC Design * '''[[Design Review]]'''
  3 KB (381 words) - 14:17, 28 January 2023

View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)