Difference between revisions of "Digital"
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** '''[[Digital Medical Ultrasound Imaging]]''' | ** '''[[Digital Medical Ultrasound Imaging]]''' | ||
** '''[[Flexible Electronic Systems and Embedded Epidermal Devices]]''' | ** '''[[Flexible Electronic Systems and Embedded Epidermal Devices]]''' | ||
| − | ** '''[[Human Intranet]]''' | + | ** '''[[Human Intranet | Human Intranet: wearables and algorithms for health and human-machine interfaces]]''' |
** '''[[Wearables for Sports and Fitness Tracking]]''' | ** '''[[Wearables for Sports and Fitness Tracking]]''' | ||
* '''[[Deep Learning Projects|Efficient Deep Learning]]''' | * '''[[Deep Learning Projects|Efficient Deep Learning]]''' | ||
| Line 31: | Line 31: | ||
==External Collaborations== | ==External Collaborations== | ||
<imagemap> | <imagemap> | ||
| − | Image: | + | Image:digital_external.png|780px |
| − | rect | + | rect 0 0 1309 912 [[IBM Research]] |
| − | rect | + | rect 1309 0 2618 912 [[Huawei_Research|Huawei Research]] |
| − | + | rect 2618 0 3927 912 [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]] | |
| − | rect | ||
</imagemap> | </imagemap> | ||
===Topic List=== | ===Topic List=== | ||
| − | |||
| − | |||
* '''[[IBM Research]]''' | * '''[[IBM Research]]''' | ||
* '''[[Huawei_Research|Huawei Research - Future Computing Laboratory (Computer Architecture and Machine Learning Acceleration)]]''' | * '''[[Huawei_Research|Huawei Research - Future Computing Laboratory (Computer Architecture and Machine Learning Acceleration)]]''' | ||
Latest revision as of 15:21, 23 February 2024
Topic List
- High Performance SoCs
- HW/SW Safety and Security
- Biomedical Circuits, Systems, and Applications
- Efficient Deep Learning
- Embedded Systems and Autonomous UAVs
- ASIC Design Projects
External Collaborations
Topic List
- IBM Research
- Huawei Research - Future Computing Laboratory (Computer Architecture and Machine Learning Acceleration)
- Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets
- Physics is looking for PULP
Projects
All projects are annotated with one or more possible project types (M/S/B/G) and a number of students (1 to 3).
- M: Master's thesis: 26 weeks full-time (6 months) for one student only
- S: Semester project: 14 weeks half-time (1 semester lecture period) or 7 weeks full-time for 1-3 students
- B: Bachelor's thesis: 14 weeks half-time (1 semester lecture period) for one student only
- G: Group project: 14 weeks part-time (1 semester lecture period) for 2-3 students
Usually, these are merely suggestions from our side; proposals can often be reformulated to fit students' needs.
Available Projects
These are the projects that were recently made available. Please have a look at the individual topic list pages to find more available projects or talk to one of the supervisors directly if you are interested in his topics. Whether a thesis is available as a master or semester thesis is most of the time negotiable with the supervisor. Don't hesitate to show interest in a master thesis topic even though you are e.g. looking for a semester thesis.
- GPT on the edge
- Audio Visual Speech Separation and Recognition (1S/1M)
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Federated Continual Learning on Nano-Drone Swarms
- FPGA mapping of RPC DRAM
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extreme-Edge Experience Replay for Keyword Spotting
- Learning at the Edge with Hardware-Aware Algorithms
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- NeuroSoC RISC-V Component (M/1-2S)
Active Projects
These are the projects that are currently active:
- ASR-Waveformer
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Fault-Tolerant Floating-Point Units (M)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Implementation of a Cache Reliability Mechanism (1S/M)
- Efficient collective communications in FlooNoC (1M)
- On-Board Software for PULP on a Satellite
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Zephyr RTOS on PULP
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Physical Implementation of ITA (2S)
- 3D Matrix Multiplication Unit for ITA (1S)
- Virtual Memory Ara
- New RVV 1.0 Vector Instructions for Ara
- Big Data Analytics Benchmarks for Ara
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Runtime partitioning of L1 memory in Mempool (M)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Radiation Testing of a PULP ASIC
- Ultrasound Doppler system development
- On - Device Continual Learning for Seizure Detection on GAP9
- Ultrasound-EMG combined hand gesture recognition
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Ternary Neural Networks for Face Recognition
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Efficient TNN compression
- Event-Driven Vision on an embedded platform
- ASIC Development of 5G-NR LDPC Decoder
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
Completed Projects
These are projects that were completed in the last few years:
2023
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Enabling Efficient Systolic Execution on MemPool (M)
- Network-off-Chip (M)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Transformer Deployment on Heterogeneous Many-Core Systems
- Smart Meters
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
2022
- Bandwidth Efficient NEureka
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Resource Partitioning of Caches
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Enabling Efficient Systolic Execution on MemPool (M)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Evaluating SoA Post-Training Quantization Algorithms
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Wireless EEG Acquisition and Processing
- Development of statistics and contention monitoring unit for PULP
- Implementing Configurable Dual-Core Redundancy
- Running Rust on PULP
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Implementing DSP Instructions in Banshee (1S)
- Design of combined Ultrasound and Electromyography systems
- Designing a Power Management Unit for PULP SoCs
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Triple-Core PULPissimo
- Watchdog Timer for PULP
- Ultrasound signal processing acceleration with CUDA
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
2021
- Novel Metastability Mitigation Technique
- Analog Compute-in-Memory Accelerator Interface and Integration
- Wearables in Fashion
- Outdoor Precision Object Tracking for Rockfall Experiments
- Autonomous Sensing For Trains In The IoT Era
- CLIC for the CVA6
- Online Learning of User Features (1S)
- Feature Extraction for Speech Recognition (1S)
- SCMI Support for Power Controller Subsystem
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Implementing DSP Instructions in Banshee (1S)
- Streaming Integer Extensions for Snitch (M/1-2S)
- Efficient Synchronization of Manycore Systems (M/1S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- PULP’s CLIC extensions for fast interrupt handling
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Next Generation Synchronization Signals
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Ultra low power wearable ultrasound probe
- Machine Learning for extracting Muscle features using Ultrasound 2
- Hardware Constrained Neural Architechture Search
- Implementation of an AES Hardware Processing Engine (B/S)
- Transforming MemPool into a CGRA (M)
- Ultrasound Low power WiFi with IMX7
- Ultrasound signal processing acceleration with CUDA
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Machine Learning for extracting Muscle features using Ultrasound
- Compression of Ultrasound data on FPGA
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- LLVM and DaCe for Snitch (1-2S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Manycore System on FPGA (M/S/G)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- Time Gain Compensation for Ultrasound Imaging
2020
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Hypervisor Extension for Ariane (M)
- Advanced 5G Repetition Combining
- Multi issue OoO Ariane Backend (M)
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Low Latency Brain-Machine Interfaces
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- Deep Convolutional Autoencoder for iEEG Signals
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Timing Channel Mitigations for RISC-V Cores
2019
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Floating-Point Divide & Square Root Unit for Transprecision
- TCNs vs. LSTMs for Embedded Platforms
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Exploring Algorithms for Early Seizure Detection
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Indoor Positioning with Bluetooth
- Improving Resiliency of Hyperdimensional Computing
- Toward Superposition of Brain-Computer Interface Models
- LightProbe - WIFI extension (PCB)
2018
- Digital Audio Interface for Smart Intensive Computing Triggering
- Shared Correlation Accelerator for an RF SoC
- IoT Turbo Decoder
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Creating a HDMI Video Interface for PULP
- Interference Cancellation for EC-GSM-IoT
2017
- A computational memory unit using phase-change memory devices
- Deep Learning for Brain-Computer Interface
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Turbo Equalization for Cellular IoT
- Sensor Fusion for Rockfall Sensor Node
- Development of a Rockfall Sensor Node
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- A Wireless Sensor Network for a Smart Building Monitor and Control
- BigPULP: Multicluster Synchronization Extensions
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
2016
- A Recurrent Neural Network Speech Recognition Chip
- Efficient NB-IoT Uplink Design
- Internet of Things Network Synchronizer
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- High-speed Scene Labeling on FPGA
- Learning Image Decompression with Convolutional Networks
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- Implementing Hibernation on the ARM Cortex M0
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Spatio-Temporal Video Filtering
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
2015
- Hardware Accelerated Derivative Pricing
- Glitches Reduce Listening Time of Your iPod
- FFT-based Convolutional Network Accelerator
- Real-Time Optical Flow Using Neural Networks
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Vector Processor for In-Memory Computing
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Hardware/software co-programming on the Parallella platform
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Real-Time Stereo to Multiview Conversion
2014
- EvalEDGE: A 2G Cellular Transceiver FMC
- Real-Time Stereo to Multiview Conversion
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
2012
- A Multiview Synthesis Core in 65 nm CMOS
- Real-time View Synthesis using Image Domain Warping
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
2011
- Compressed Sensing Reconstruction on FPGA
- A Multiview Synthesis Core in 65 nm CMOS
- Real-time View Synthesis using Image Domain Warping
- Putting Together What Fits Together - GrÆStl
ASICs
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Single-Bit-Synapse Spiking Neural System-on-Chip
Categories:
- Computer Architecture
- Acceleration and Transprecision
- Heterogeneous Acceleration Systems
- Event-Driven Computing
- Predictable Execution
- Low Power Embedded Systems
- Embedded Artificial Intelligence:Systems And Applications
- Transient Computing
- System on Chips for IoTs
- Energy Efficient Autonomous UAVs
- Biomedical System on Chips
- Digital Medical Ultrasound Imaging
- Cryptography
- Deep Learning Acceleration
- Human Intranet
