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Showing below up to 500 results in range #251 to #750.
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- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (9 revisions)
- Automatic unplugging detection for Ultrasound probes (9 revisions)
- A Multiview Synthesis Core in 65 nm CMOS (9 revisions)
- DC-DC Buck converter in 65nm CMOS (9 revisions)
- Energy Efficient SoCs (9 revisions)
- Configurable Ultra Low Power LDO (9 revisions)
- Gomeza old project2 (9 revisions)
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology (9 revisions)
- Improved State Estimation on PULP-based Nano-UAVs (9 revisions)
- Freedom from Interference in Heterogeneous COTS SoCs (9 revisions)
- Practical Reconfigurable Intelligent Surfaces (RIS) (9 revisions)
- Real-time View Synthesis using Image Domain Warping (9 revisions)
- Michael Rogenmoser (9 revisions)
- Hardware Accelerated Derivative Pricing (9 revisions)
- OpenRISC SoC for Sensor Applications (9 revisions)
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging (9 revisions)
- Physical Implementation of ITA (2S) (8 revisions)
- Weekly Reports (8 revisions)
- Streaming Layer Normalization in ITA (M/1-2S) (8 revisions)
- OTDOA Positioning for LTE Cat-M (8 revisions)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 revisions)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 revisions)
- Resource Partitioning of RPC DRAM (8 revisions)
- A Unified Compute Kernel Library for Snitch (1-2S) (8 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- Object Detection and Tracking on the Edge (8 revisions)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (8 revisions)
- NVDLA meets PULP (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Evaluating SoA Post-Training Quantization Algorithms (8 revisions)
- (M/1-2S): A Snitch-based Compute Accelerator for HERO (8 revisions - redirect page)
- Sandro Belfanti (8 revisions)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 revisions)
- Learning at the Edge with Hardware-Aware Algorithms (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- Wireless EEG Acquisition and Processing (8 revisions)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- An FPGA-Based Evaluation Platform for Mobile Communications (8 revisions)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (8 revisions)
- Flexible Electronic Systems and Epidermal Devices (8 revisions - redirect page)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (8 revisions)
- Pirmin Vogel (8 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (8 revisions)
- Implementing Hibernation on the ARM Cortex M0 (8 revisions)
- Evaluating the RiscV Architecture (8 revisions)
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC (8 revisions)
- BCI-controlled Drone (8 revisions)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs (8 revisions)
- Manycore System on FPGA (M/S/G) (8 revisions)
- Fast Wakeup From Deep Sleep State (8 revisions)
- Multi issue OoO Ariane Backend (M) (8 revisions)
- PREM Runtime Scheduling Policies (8 revisions)
- Hypervisor Extension for Ariane (M) (8 revisions)
- Deep Convolutional Autoencoder for iEEG Signals (8 revisions)
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications (8 revisions)
- ASIC Implementation of Jammer Mitigation (8 revisions)
- Development of a fingertip blood pressure sensor (8 revisions)
- Hardware/software co-programming on the Parallella platform (8 revisions)
- Ultra Low-Power Oscillator (8 revisions)
- Modular Distributed Data Collection Platform (8 revisions)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (8 revisions)
- SCMI Support for Power Controller Subsystem (8 revisions)
- Linux Driver for fine-grain and low overhead access to on-chip performance counters (8 revisions)
- Fault-Tolerant Floating-Point Units (M) (8 revisions)
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format (8 revisions)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) (8 revisions)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (8 revisions)
- A Trustworthy Three-Factor Authentication System (8 revisions)
- A computational memory unit using phase-change memory devices (8 revisions)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (7 revisions)
- Development of an implantable Force sensor for orthopedic applications (7 revisions)
- IoT Turbo Decoder (7 revisions)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (7 revisions)
- Autonomous Sensing For Trains In The IoT Era (7 revisions)
- EEG earbud (7 revisions)
- Internet of Things Network Synchronizer (7 revisions)
- Development of statistics and contention monitoring unit for PULP (7 revisions)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (7 revisions)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S) (7 revisions)
- Gomeza old project5 (7 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (7 revisions)
- Charging System for Implantable Electronics (7 revisions)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (7 revisions)
- SW/HW Predictability and Security (7 revisions)
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients (7 revisions)
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT (7 revisions)
- FFT HDL Code Generator for Multi-Antenna mmWave Communication (7 revisions)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (7 revisions)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (7 revisions)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver (7 revisions)
- RVfplib (7 revisions)
- Bateryless Heart Rate Monitoring (7 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (1M) (7 revisions)
- Putting Together What Fits Together - GrÆStl (7 revisions)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (7 revisions)
- Compressed Sensing for Wireless Biosignal Monitoring (7 revisions)
- Predictable Execution (7 revisions)
- Satellite Internet of Things (7 revisions)
- Mauro Salomon (7 revisions)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities (7 revisions)
- Ultra-low power processor design (7 revisions)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (7 revisions)
- Battery indifferent wearable Ultrasound (7 revisions)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (7 revisions)
- Outdoor Precision Object Tracking for Rockfall Experiments (7 revisions)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (7 revisions)
- Make Cellular Internet of Things Receivers Smart (7 revisions)
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (7 revisions)
- Ibex: FPGA Optimizations (7 revisions)
- Digital Audio Interface for Smart Intensive Computing Triggering (7 revisions)
- Ultrasound Low power WiFi with IMX7 (7 revisions)
- Indoor Positioning with Bluetooth (7 revisions)
- Efficient NB-IoT Uplink Design (7 revisions)
- Development of a Rockfall Sensor Node (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (7 revisions)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (7 revisions)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (7 revisions)
- Efficient Search Design for Hyperdimensional Computing (7 revisions)
- RazorEDGE: An Evolved EDGE DBB ASIC (7 revisions)
- Transforming MemPool into a CGRA (M) (7 revisions)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (7 revisions)
- Spiking Neural Network for Autonomous Navigation (7 revisions)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (7 revisions)
- Zephyr RTOS on PULP (7 revisions)
- EEG artifact detection for epilepsy monitoring (7 revisions)
- Fault Tolerance (7 revisions)
- Streaming Integer Extensions for Snitch (M/1-2S) (7 revisions)
- LTE IoT Network Synchronization (7 revisions)
- Characterization techniques for silicon photonics-Lumiphase (7 revisions)
- IBM Research–Zurich (6 revisions)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) (6 revisions)
- Change-based Evaluation of Convolutional Neural Networks (6 revisions)
- Android Software Design (6 revisions)
- FPGA mapping of RPC DRAM (6 revisions)
- Next Generation Channel Decoder (6 revisions)
- Design of a Low Power Smart Sensing Multi-modal Vision Platform (6 revisions)
- Self Aware Epilepsy Monitoring (6 revisions)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S) (6 revisions)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (6 revisions)
- Graph neural networks for epileptic seizure detection (6 revisions)
- Ultra-Efficient Visual Classification on Movidius Myriad2 (6 revisions)
- Enabling Efficient Systolic Execution on MemPool (M) (6 revisions)
- Learning Image Decompression with Convolutional Networks (6 revisions)
- Switched Capacitor Based Bandgap-Reference (6 revisions)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) (6 revisions)
- Moritz Schneider (6 revisions)
- Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening (6 revisions)
- Channel Estimation for 3GPP TD-SCDMA (6 revisions)
- Implementing Configurable Dual-Core Redundancy (6 revisions)
- Autonomous Smart Watches: Hardware and Software Desing (6 revisions)
- Creating a HDMI Video Interface for PULP (6 revisions)
- LightProbe - Ultracompact Power Supply PCB (6 revisions)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (6 revisions)
- Implementing DSP Instructions in Banshee (1S) (6 revisions)
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA (6 revisions)
- CMOS power amplifier for field measurements in MRI systems (6 revisions)
- VLSI Design of an Asynchronous LDPC Decoder (6 revisions)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (6 revisions)
- Bluetooth Low Energy receiver in 65nm CMOS (6 revisions)
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing (6 revisions)
- A Recurrent Neural Network Speech Recognition Chip (6 revisions)
- MemPool on HERO (1S) (6 revisions)
- Improved Collision Avoidance for Nano-drones (6 revisions)
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things (6 revisions)
- Floating-Point Divide & Square Root Unit for Transprecision (6 revisions)
- New RVV 1.0 Vector Instructions for Ara (6 revisions)
- Towards Self Sustainable UAVs (6 revisions)
- Writing a Hero runtime for EPAC (1-3S/B) (6 revisions)
- Beat Cadence (6 revisions)
- Exploring Algorithms for Early Seizure Detection (6 revisions)
- Compression of iEEG Data (6 revisions)
- VLSI Implementation of a 5G Ciphering Accelerator (6 revisions)
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets (6 revisions)
- Low-power Temperature-insensitive Timer (6 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache (6 revisions)
- FPGA Optimizations of Dense Binary Hyperdimensional Computing (6 revisions)
- Exploring NAS spaces with C-BRED (6 revisions)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (6 revisions)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M) (6 revisions)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (6 revisions)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (6 revisions)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich) (6 revisions)
- Ultrasound image data recycler (6 revisions)
- Efficient Synchronization of Manycore Systems (M/1S) (6 revisions)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA (6 revisions)
- Novel Metastability Mitigation Technique (6 revisions)
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors (6 revisions)
- System Emulation for AR and VR devices (6 revisions)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) (6 revisions)
- Novel Methods for Jammer Mitigation (6 revisions)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (6 revisions)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (6 revisions)
- Andreas Kurth (5 revisions)
- Resource Partitioning of Caches (5 revisions)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography (5 revisions)
- Ultrasound signal processing acceleration with CUDA (5 revisions)
- Low-Complexity MIMO Detection (5 revisions)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing (5 revisions)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (5 revisions)
- Towards Autonomous Navigation for Nano-Blimps (5 revisions)
- Open Power-On Chip Controller Study and Integration (5 revisions)
- LightProbe - Frontend Firmware and Control Side Channel (5 revisions)
- Simulation of 2D artificial cilia metasurface in COMSOL (5 revisions)
- Machine Learning for extracting Muscle features from Ultrasound raw data (5 revisions)
- TCNs vs. LSTMs for Embedded Platforms (5 revisions)
- Embedded Systems and autonomous UAVs (5 revisions)
- Learning Image Compression with Convolutional Networks (5 revisions)
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path (5 revisions)
- Ultrafast Medical Ultrasound imaging on a GPU (5 revisions)
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB (5 revisions)
- Internet of Things SoC Characterization (5 revisions)
- Data Augmentation Techniques in Biosignal Classification (5 revisions)
- IP-Based SoC Generation and Configuration (1-3S/B) (5 revisions)
- Universal Stream Semantic Registers for Snitch (1S) (5 revisions - redirect page)
- Precise Ultra-low-power Timer (5 revisions)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (5 revisions)
- Software-Defined Paging in the Snitch Cluster (2-3S) (5 revisions)
- Hardware Accelerator for Model Predictive Controller (5 revisions)
- LightProbe - Thermal-Power aware on-head Beamforming (5 revisions)
- State-Saving @ NXP (5 revisions)
- ASIC Design Projects (5 revisions)
- A Wearable System To Control Phone And Electronic Device Without Hands (5 revisions)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf (5 revisions)
- Predict eye movement through brain activity (5 revisions)
- Engineering For Kids (5 revisions)
- Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S) (5 revisions)
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device (5 revisions)
- Noise Figure Measurement for Cryogenic System (5 revisions)
- Federico Villani (5 revisions)
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor (5 revisions)
- Design and Implementation of ultra low power vision system (5 revisions)
- Fast Simulation of Manycore Systems (1S) (5 revisions)
- Multi-Modal Environmental Sensing With GAP9 (1-2S) (5 revisions)
- Predictable Execution on GPU Caches (5 revisions)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich) (5 revisions)
- Compression of Ultrasound data on FPGA (5 revisions)
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET (5 revisions)
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring (5 revisions)
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap (5 revisions)
- Low-power Clock Generation Solutions for 65nm Technology (5 revisions)
- Final Presentation (5 revisions)
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA) (5 revisions)
- Ultra-low power transceiver for implantable devices (5 revisions)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea (5 revisions)
- Adding Linux Support to our DMA Engine (1-2S/B) (5 revisions)
- Artificial Reverberation for Embedded Systems (5 revisions)
- Ternary Neural Networks for Face Recognition (5 revisions)
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers (5 revisions)
- A Wireless Sensor Network for a Smart Building Monitor and Control (5 revisions)
- Channel Shortening Prefilter (5 revisions - redirect page)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S) (5 revisions)
- Implementation of a NB-IoT Positioning System (5 revisions)
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces (5 revisions)
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) (5 revisions)
- Phase-change memory devices for emerging computing paradigms (5 revisions)
- Indoor Smart Tracking of Hospital instrumentation (5 revisions)
- Beat DigRF (5 revisions)
- LLVM and DaCe for Snitch (1-2S) (5 revisions)
- Subject specific embeddings for transfer learning in brain-computer interfaces (5 revisions)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) (5 revisions)
- IBM A2O Core (5 revisions)
- Designing a Power Management Unit for PULP SoCs (5 revisions)
- Inductive Charging Circuit for Implantable Devices (5 revisions)
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control (5 revisions)
- Image Sensor Interface and Pre-processing (5 revisions)
- An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications (5 revisions)
- Embedded Artificial Intelligence:Systems And Applications (5 revisions)
- Snitch meets iCE40 (1-2S/B) (5 revisions - redirect page)
- Hardware/software codesign neural decoding algorithm for “neural dust” (5 revisions)
- Toward Superposition of Brain-Computer Interface Models (5 revisions)
- Ultra Low Power Conversion Circuit For Batteryless Applications (5 revisions)
- FPGA Testbed Implementation for Bluetooth Indoor Positioning (5 revisions)
- 5G Cellular RF Front-end Design in 22nm CMOS Technology (5 revisions)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) (5 revisions)
- Design of a Fused Multiply Add Floating Point Unit (5 revisions)
- Development of an efficient algorithm for quantum transport codes (5 revisions)
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams (5 revisions)
- Low Latency Brain-Machine Interfaces (5 revisions)
- Eye tracking (5 revisions)
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC (5 revisions)
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration (5 revisions)
- Ultra Low Power Wake Up Radio for Wireless Sensor Network (5 revisions)
- EEG artifact detection with machine learning (4 revisions)
- Variability Tolerant Ultra Low Power Cluster (4 revisions)
- Efficient TNN compression (4 revisions)
- NAND Flash Open Research Platform (4 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core (4 revisions)
- Super Resolution Radar/Imaging at mm-Wave frequencies (4 revisions)
- Improving Resiliency of Hyperdimensional Computing (4 revisions)
- Every individual on the planet should have a real chance to obtain personalized medical therapy (4 revisions)
- AMZ Driverless Competition Embedded Systems Projects (4 revisions)
- IP-Based SoC Generation and Configuration (1-3S) (4 revisions)
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM. (4 revisions)
- Jammer-Resilient Synchronization for Wireless Communications (4 revisions)
- Energy Neutral Multi Sensors Wearable Device (4 revisions)
- SSR combined with FREP in LLVM/Clang (M/1-3S) (4 revisions - redirect page)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) (4 revisions)
- Theory, Algorithms, and Hardware for Beyond 5G (4 revisions)
- ASR-Waveformer (4 revisions)
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems (4 revisions)
- Evaluating An Ultra low Power Vision Node (4 revisions)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (4 revisions)
- Pascal Hager (4 revisions)
- Edge Computing for Long-Term Wearable Biomedical Systems (4 revisions)
- Wireless Biomedical Signal Acquisition Device (4 revisions)
- Android reliability governor (4 revisions)
- Fabian Schuiki (4 revisions)
- GPT on the edge (4 revisions)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments (4 revisions)
- AnalogInt (4 revisions)
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications (4 revisions)
- Design of State Retentive Flip-Flops (4 revisions)
- DigitalUltrasoundHead (4 revisions)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (4 revisions)
- Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets (4 revisions)
- Guillaume Mocquard (4 revisions)
- Digital Transmitter for Cellular IoT (4 revisions)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (4 revisions)
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node (4 revisions)
- Low Power Neural Network For Multi Sensors Wearable Devices (4 revisions)
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator (4 revisions)
- Design of low-offset dynamic comparators (4 revisions)
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks (4 revisions)
- Routing 1000s of wires in Network-on-Chips (1-2S/M) (4 revisions)
- Stefan Lippuner (4 revisions)
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor (4 revisions)
- Low-Power Time Synchronization for IoT Applications (4 revisions)
- Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication (4 revisions)
- Improving our Smart Camera System (4 revisions)
- Stefan Mach (4 revisions)
- Telecommunications (4 revisions)
- ASIC Design of a Sigma Point Processor (4 revisions)
- Non-binary LDPC Decoder for Deep-Space Optical Communications (4 revisions)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (4 revisions)
- Ibex: Bit-Manipulation Extension (4 revisions)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers (4 revisions)
- Enhancing our DMA Engine with Fault Tolerance (4 revisions)
- Near-Memory Training of Neural Networks (4 revisions)
- Ultra-low power sampling front-end for acquisition of physiological signals (4 revisions)
- Accelerating Applications Relying on Matrix-Vector-Product-Like Operations (4 revisions)
- Intelligent Power Management Unit (iPMU) (4 revisions)
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications (4 revisions)
- Hardware Exploration of Shared-Exponent MiniFloats (M) (4 revisions)
- Ultrasound High Speed Microbubble Tracking (4 revisions)
- Positioning for the cellular Internet of Things (4 revisions)
- In-ear EEG signal acquisition (4 revisions)
- CPS Software-Configurable State-Machine (4 revisions)
- Virtual Memory Ara (4 revisions)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (4 revisions)
- Sub-Noise Floor Channel Tracking (4 revisions)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (4 revisions)
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning (4 revisions)
- Final Report (4 revisions)
- High performance continous-time Delta-Sigma ADC for biomedical applications (4 revisions)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (4 revisions)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (4 revisions - redirect page)
- Forward error-correction ASIC using GRAND (4 revisions)
- Adding Linux Support to our DMA engine (1-2S/B) (4 revisions - redirect page)
- Power Optimization in Multipliers (4 revisions)
- Low-power chip-to-chip communication network (4 revisions)
- Smart e-glasses for concealed recording of EEG signals (4 revisions)
- Eye movements (4 revisions)
- Implementation of an AES Hardware Processing Engine (B/S) (4 revisions)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (4 revisions)
- Advanced Data Movers for Modern Neural Networks (4 revisions)
- VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM (4 revisions)
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM (4 revisions)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3 (4 revisions)
- Finite element modeling of electrochemical random access memory (4 revisions)
- Palm size chip NMR (4 revisions)
- LightProbe - Design of a High-Speed Optical Link (3 revisions)
- Signal to Noise Ratio Estimation for 3G standards (3 revisions)
- Machine Learning Assisted Direct Synthesis of Passive Networks (3 revisions)
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation (3 revisions)
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs) (3 revisions)
- Design of MEMs Sensor Interface (3 revisions)
- Audio DAC Conversion Jitter Measurement System (3 revisions)
- High-throughput Embedded System For Neurotechnology in collaboration with INI (3 revisions)
- Turbo Decoder Design for High Code Rates (3 revisions)
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications (3 revisions)
- Embedded Gesture Recognition Using Novel Mini Radar Sensors (3 revisions)
- Low Power Embedded Systems (3 revisions)
- Softmax for Transformers (M/1-2S) (3 revisions)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) (3 revisions)
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors (3 revisions)
- Build the Fastest 2G Modem Ever (3 revisions)
- DaCe on Snitch (M/1-3S) (3 revisions - redirect page)
- Unconventional phase change memory device concepts for in-memory and neuromorphic computin (3 revisions)
- Ambient RF Energy harvesting for Wireless Sensor Network (3 revisions)
- Channel Decoding for TD-HSPA (3 revisions)
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection (3 revisions)
- Low Power Embedded Systems and Wireless Sensors Networks (3 revisions)
- Software (3 revisions)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (3 revisions)
- (M): A Flexible Peripheral System for High-Performance Systems on Chip (3 revisions)
- Standard Cell Compatible Memory Array Design (3 revisions)
- Infrared Wake Up Radio (3 revisions)
- Jammer Mitigation Meets Machine Learning (3 revisions)
- Extended Verification for Ara (3 revisions)
- Matthias Korb (3 revisions)
- Thermal Control of Mobile Devices (3 revisions)
- Implementing A Low-Power Sensor Node Network (3 revisions)
- Watchdog Timer for PULP (3 revisions)
- Receiver design for the DigRF 4G high speed serial link (3 revisions)
- Towards Formal Verification of the iDMA Engine (1-3S/B) (3 revisions)
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations (3 revisions)
- Simulation of Negative Capacitance Ferroelectric Transistor (3 revisions)
- Taping a Safer Silicon Implementation of Snitch (M/2-3S) (3 revisions)
- Developing a small portable neutron detector for detecting smuggled nuclear material (3 revisions)
- Integrated Devices, Electronics, And Systems (3 revisions)
- Mattia (3 revisions)
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip (3 revisions)
- Sound-Based Vehicle Classification and Counting (1-2S) (3 revisions)
- 3D Matrix Multiplication Unit for ITA (1S) (3 revisions)
- Neural Recording Interface and Spike Sorting Algorithm (3 revisions)
- Improving datarate and efficiency of ultra low power wearable ultrasound (3 revisions)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M) (3 revisions)
- Radiation Testing Board (3 revisions - redirect page)
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels (3 revisions)
- Enabling Standalone Operation for a Mobile Health Platform (3 revisions)
- Bluetooth Low Energy network with optimized data throughput (3 revisions)
- NeuroSoC RISC-V Component (M/1-2S) (3 revisions)
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras (3 revisions)
- Running Rust on PULP (3 revisions)
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (3 revisions)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers (3 revisions)
- Channel Estimation for TD-HSPA (3 revisions)
- MemPool on HERO (3 revisions)
- Study and Development of Intelligent Capability for Small-Size UAVs (3 revisions)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) (3 revisions)
- Digitally-Controlled Analog Subtractive Sound Synthesis (3 revisions)
- RedCap-5G for IOT application on prototype taped-out silicon (3 revisions)
- Serverless Benchmarks on RISC-V (M) (3 revisions)
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX (3 revisions)
- Air Quality Prediction in Office Rooms (1-2S/M) (3 revisions)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development (3 revisions)
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications (3 revisions)
- Multi issue OoO Ariane Backend (3 revisions - redirect page)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S) (3 revisions)
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) (3 revisions)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) (3 revisions)
- Glitches Reduce Listening Time of Your iPod (3 revisions)
- An Industrial-grade Bluetooth LE Mesh Network Solution (3 revisions)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning (3 revisions)
- EECIS (3 revisions)
- Bringing XNOR-nets (ConvNets) to Silicon (3 revisions)
- 3D Ultrasound Bubble Tracking (3 revisions)
- Design and implementation of the front-end for a portable ionizing radiation detector (3 revisions)
- Towards The Integration of E-skin into Prosthetic Devices (3 revisions)
- Aliasing-Free Wavetable Music Synthesizer (3 revisions)
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration (3 revisions)
- Design of a D-Band Variable Gain Amplifier for 6G Communication (3 revisions)
- Integrating Hardware Accelerators into Snitch (1S) (3 revisions)
- EEG-based drowsiness detection (3 revisions)
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC (3 revisions)
- NextGenChannelDec (3 revisions)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (3 revisions)
- Development of a syringe label reader for the neurocritical care unit (3 revisions)
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors (3 revisions)
- Low-power time synchronization for IoT applications (3 revisions)
- Michael Muehlberghuber (3 revisions)
- Successive Approximation Register (SAR) ADC (3 revisions)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems (3 revisions)
- Interference Cancellation for the cellular Internet of Things (3 revisions)
- Bandwidth Efficient NEureka (3 revisions)
- Efficient TNN Inference on PULP Systems (3 revisions)
- Investigation of the source starvation effect in III-V MOSFET (3 revisions)
- Digital Control of a DC/DC Buck Converter (3 revisions)
- Improving Cold-Start in Batteryless And Energy Harvesting Systems (2 revisions)
- RISC-V base ISA for ultra-low-area cores (2-3G) (2 revisions)
- DaCe on Snitch (2 revisions)
- System on Chips for IoTs (2 revisions - redirect page)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy (2 revisions)
- Prasadar (2 revisions)
- SSR combined with FREP in LLVM/Clang (2 revisions)
- Smart Agriculture System (1-2S) (2 revisions)
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices (2 revisions)
- PULP Freertos with LLVM (2 revisions)
- Project Meetings (2 revisions)
- Neural Networks Framwork for Embedded Plattforms (2 revisions)
- A Post-Simulation Trace-Based RISC-V GDB Debugging Server (2 revisions)
- High resolution, low power Sigma Delta ADC (2 revisions)
- Accelerators for object detection and tracking (2 revisions)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing (2 revisions)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (2 revisions)
- NORX - an AEAD algorithm for the CAESAR competition (2 revisions)
- High Performance Cellular Receivers in Very Advanced CMOS (2 revisions)
- Implementation of a 2-D model for Li-ion batteries (2 revisions)
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- Realtime Gaze Tracking on Siracusa (2 revisions)
- Neural Processing (2 revisions)
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- Accurate deep learning inference using computational memory (2 revisions)
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- An Efficient Compiler Backend for Snitch (1S/B) (2 revisions)
