Orphaned pages

The following pages are not linked from or transcluded into other pages in iis-projects.

Showing below up to 50 results in range #31 to #80.

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31. A Wearable System To Control Phone And Electronic Device Without Hands
32. A Wearable System for long term monitoring of human physiological parameters with E skin sensors
33. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
34. A Wireless Sensor Network for HPC monitoring
35. A Wireless Sensor Network for a Smart Building Monitor and Control
36. A computational memory unit using phase-change memory devices
37. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
38. A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
39. Ab-initio Simulation of Strained Thermoelectric Materials
40. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
41. Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
42. Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
43. Accelerators for object detection and tracking
44. Accurate deep learning inference using computational memory
45. Active-Set QP Solver on FPGA
46. Advanced 5G Repetition Combining
47. Advanced Data Movers for Modern Neural Networks
48. Advanced EEG glasses
49. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
50. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
51. Air Quality Prediction in Office Rooms (1-2S/M)
52. Alias-Free Oscillator Synchronization for Arbitrary Waveforms
53. Aliasing-Free Wavetable Music Synthesizer
54. All the flavours of FFT on MemPool (1-2S/B)
55. Ambient RF Energy harvesting for Wireless Sensor Network
56. An Efficient Compiler Backend for Snitch (1S/B)
57. An Energy Efficient Brain-Computer Interface using Mr.Wolf
58. An FPGA-Based Evaluation Platform for Mobile Communications
59. An FPGA-Based Testbed for 3G Mobile Communications Receivers
60. An Industrial-grade Bluetooth LE Mesh Network Solution
61. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
62. An Ultra-Low-Power Neuromorphic Spiking Neuron Design
63. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
64. AnalogInt
65. Analog Compute-in-Memory Accelerator Interface and Integration
66. Analog Layout Engine
67. Analog building blocks for mmWave manipulation
68. Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
69. Android Software Design
70. Android reliability governor
71. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
72. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
73. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
74. Artificial Reverberation for Embedded Systems
75. Assessment of novel photovoltaic architectures by circuit simulation
76. Audio DAC Conversion Jitter Measurement System
77. Audio Video Preprocessing In Parallel Ultra Low Power Platform
78. Audio Visual Speech Recognition (1S/1M)
79. Audio Visual Speech Separation (1S/1M)
80. Audio Visual Speech Separation and Recognition (1S/1M)

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