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Showing below up to 50 results in range #151 to #200.
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- CPS Software-Configurable State-Machine
- Cell-Free mmWave Massive MIMO Communication
- Cell Measurements for the 5G Internet of Things
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Change-based Evaluation of Convolutional Neural Networks
- Channel Decoding for TD-HSPA
- Channel Estimation and Equalization for LTE Advanced
- Channel Estimation for 3GPP TD-SCDMA
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Channel Estimation for TD-HSPA
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Characterization techniques for silicon photonics-Lumiphase
- Charge and heat transport through graphene nanoribbon based devices
- Charging System for Implantable Electronics
- Christoph Keller
- Christoph Leitner
- Circuits and Systems for Nanoelectrode Array Biosensors
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
- Coding Guidelines
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Compiler Profiling and Optimizing
- Completed
- Compressed Sensing Reconstruction on FPGA
- Compressed Sensing for Wireless Biosignal Monitoring
- Compressed Sensing vs JPEG
- Compression of Ultrasound data on FPGA
- Compression of iEEG Data
- Computation of Phonon Bandstructure in III-V Nanostructures
- Configurable Ultra Low Power LDO
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating a HDMI Video Interface for PULP
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Cryptography
- Cycle-Accurate Event-Based Simulation of Snitch Core
- DC-DC Buck converter in 65nm CMOS
- DMA Streaming Co-processor
- DaCe on Snitch
