Difference between revisions of "Category:Master Thesis"

Latest revision as of 19:56, 17 February 2015

The projects listed here are Master thesis projects. In principle a master project at IIS can take no longer than 6 months, and the student is expected to work full time on the thesis project. In some cases it is possible to make a simplified version of the project as a semester thesis, talk to the supervisor of the project to discuss this possibility.

Available Projects

• Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
• On-Device Learnable Embeddings for Acoustic Environments
• On-Device Federated Continual Learning on Nano-Drone Swarms
• Extending our FPU with Internal High-Precision Accumulation (M)
• Extreme-Edge Experience Replay for Keyword Spotting
• Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
• Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
• GPT on the edge
• Modeling FlooNoC in GVSoC (S/M)
• Hardware Exploration of Shared-Exponent MiniFloats (M)
• Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
• EEG-based drowsiness detection
• In-ear EEG signal acquisition
• EEG earbud
• NeuroSoC RISC-V Component (M/1-2S)
• Routing 1000s of wires in Network-on-Chips (1-2S/M)
• Network-on-Chip for coherent and non-coherent traffic (M)
• Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
• An Ultra-Low-Power Neuromorphic Spiking Neuron Design
• Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
• Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
• System Emulation for AR and VR devices
• Learning at the Edge with Hardware-Aware Algorithms
• Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
• Advanced EEG glasses
• Softmax for Transformers (M/1-2S)
• Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
• Testbed Design for Self-sustainable IoT Sensors
• Towards Flexible and Printable Wearables
• Modular Distributed Data Collection Platform
• Cycle-Accurate Event-Based Simulation of Snitch Core
• Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
• Wireless In Action Data Streaming in Ski Jumping (1 B/S)
• A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
• Object Detection and Tracking on the Edge
• Design of a Low Power Smart Sensing Multi-modal Vision Platform
• Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
• Efficient Banded Matrix Multiplication for Quantum Transport Simulations
• Charge and heat transport through graphene nanoribbon based devices
• Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening
• High resolution, low power Sigma Delta ADC
• Noise Figure Measurement for Cryogenic System
• An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
• Configurable Ultra Low Power LDO
• Energy Efficient Serial Link
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
• Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
• BirdGuard
• ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
• Multisensory system for performance analysis in ski jumping (M/1-2S/B)
• High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
• High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
• Design of low mismatch DAC used for VAD
• Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
• Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
• Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
• Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
• Ultrasound image data recycler
• Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
• Design of combined Ultrasound and PPG systems
• Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
• An Efficient Compiler Backend for Snitch (1S/B)
• Integration Of A Smart Vision System
• Event-based navigation on autonomous nano-drones
• Development of an implantable Force sensor for orthopedic applications
• Improving datarate and efficiency of ultra low power wearable ultrasound
• Quantum Transport Modeling of Interband Cascade Lasers (ICL)
• A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
• Battery indifferent wearable Ultrasound
• Wearable Ultrasound for Artery monitoring
• Machine Learning for extracting Muscle features from Ultrasound raw data
• Improved Collision Avoidance for Nano-drones
• Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
• Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
• Deep Learning-based Global Local Planner for Autonomous Nano-drones
• Ultra-wideband Concurrent Ranging
• Fast Accelerator Context Switch for PULP
• Serverless Benchmarks on RISC-V (M)
• Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
• Non-blocking Algorithms in Real-Time Operating Systems
• Every individual on the planet should have a real chance to obtain personalized medical therapy
• Analog building blocks for mmWave manipulation
• A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
• Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
• Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
• Spiking Neural Network for Motor Function Decoding Based on Neural Dust
• Integrated silicon photonic structures-Lumiphase
• Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
• Characterization techniques for silicon photonics-Lumiphase
• Hardware/software codesign neural decoding algorithm for “neural dust”
• Automatic unplugging detection for Ultrasound probes
• Huawei Research
• Short Range Radars For Biomedical Application
• Smart Patch For Heath Care And Rehabilitation
• Autonomus Drones With Novel Sensors And Ultra Wide Band
• Evaluating memory access pattern specializations in OoO, server-grade cores (M)
• Machine Learning on Ultrasound Images
• IBM Research
• RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
• BCI-controlled Drone
• Accurate deep learning inference using computational memory
• Spiking Neural Network for Autonomous Navigation
• Event-Driven Convolutional Neural Network Modular Accelerator
• Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
• Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
• Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
• Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
• Electrothermal characterization of van der Waals Heterostructures with a partial overlap
• Phase-change memory devices for emerging computing paradigms
• Finite element modeling of electrochemical random access memory
• Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
• Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
• Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
• Quantum transport in 2D heterostructures
• Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
• High-throughput Embedded System For Neurotechnology in collaboration with INI
• Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
• Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
• Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
• Visualizing Functional Microbubbles using Ultrasound Imaging
• Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
• Extending the RISCV backend of LLVM to support PULP Extensions
• Compiler Profiling and Optimizing
• PREM Intervals and Loop Tiling
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
• Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
• Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
• Design and implementation of the front-end for a portable ionizing radiation detector
• Level Crossing ADC For a Many Channels Neural Recording Interface
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
• Improving Cold-Start in Batteryless And Energy Harvesting Systems
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
• Application Specific Frequency Synthesizers (Analog/Digital PLLs)
• Edge Computing for Long-Term Wearable Biomedical Systems
• AMZ Driverless Competition Embedded Systems Projects
• Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
• Wireless Sensing With Long Range Comminication (LoRa)
• Indoor Smart Tracking of Hospital instrumentation
• A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
• Physics is looking for PULP
• Embedded Gesture Recognition Using Novel Mini Radar Sensors
• Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
• An Industrial-grade Bluetooth LE Mesh Network Solution
• BLISS - Battery-Less Identification System for Security
• Monocular Vision-based Object Following on Nano-size Robotic Blimp
• A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
• Zero Power Touch Sensor and Reciever For Body Communication
• Wake Up Radio For Energy Efficient Communication System and IC Design
• A Wireless Sensor Network for HPC monitoring
• High Speed FPGA Trigger Logic for Particle Physics Experiments
• Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
• Low Power Geolocalization And Indoor Localization
• Neural Networks Framwork for Embedded Plattforms
• Hyper Meccano: Acceleration of Hyperdimensional Computing
• Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
• Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
• Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
• 5G Cellular RF Front-end Design in 22nm CMOS Technology
• Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
• Single-Bit-Synapse Spiking Neural System-on-Chip
• Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
• Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
• Open Power-On Chip Controller Study and Integration
• Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
• A Wearable System To Control Phone And Electronic Device Without Hands
• Towards The Integration of E-skin into Prosthetic Devices
• Ultra Low Power Conversion Circuit For Batteryless Applications
• Towards Self Sustainable UAVs
• Using Motion Sensors to Support Indoor Localization
• Low Power Neural Network For Multi Sensors Wearable Devices
• Bateryless Heart Rate Monitoring
• Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
• Ultra-Efficient Visual Classification on Movidius Myriad2
• Kinetic Energy Harvesting For Autonomous Smart Watches
• A Wearable System for long term monitoring of human physiological parameters with E skin sensors
• Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
• Autonomous Smart Watches: Hardware and Software Desing
• A Wireless Sensor Network for a Smart LED Lighting control
• Compressed Sensing vs JPEG
• Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
• Real-Time Pedestrian Detection For Privacy Enhancement
• Thermal Control of Mobile Devices
• Android reliability governor
• Infrared Wake Up Radio
• Ambient RF Energy harvesting for Wireless Sensor Network
• Development of an efficient algorithm for quantum transport codes
• Investigation of Metal Diffusion in Oxides for CBRAM Applications
• Investigation of Redox Processes in CBRAM
• Ultra Low Power Wake Up Radio for Wireless Sensor Network
• Developing High Efficiency Batteries for Electric Cars
• Processing of 3D Micro-tomography data for Lithium Ion Batteries

Active Projects

• ASR-Waveformer
• A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
• Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
• Fault-Tolerant Floating-Point Units (M)
• Implementation of a Cache Reliability Mechanism (1S/M)
• Efficient collective communications in FlooNoC (1M)
• Streaming Layer Normalization in ITA (M/1-2S)
• Virtual Memory Ara
• Runtime partitioning of L1 memory in Mempool (M)
• Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
• On - Device Continual Learning for Seizure Detection on GAP9
• Ternary Neural Networks for Face Recognition
• Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
• Event-Driven Vision on an embedded platform
• ASIC Development of 5G-NR LDPC Decoder
• Channel Estimation for 5G Cellular IoT and Fast Fading Channels
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications

Completed Projects

• Ultrasound Doppler system development
• Ultrasound-EMG combined hand gesture recognition
• Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
• A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
• Exploring NAS spaces with C-BRED
• Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
• Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
• Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
• Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
• Enabling Efficient Systolic Execution on MemPool (M)
• Network-off-Chip (M)
• Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
• MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
• Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
• Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
• Smart e-glasses for concealed recording of EEG signals
• Transformer Deployment on Heterogeneous Many-Core Systems
• Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
• Development of statistics and contention monitoring unit for PULP
• Implementing Configurable Dual-Core Redundancy
• Ultrasound based hand gesture recognition
• Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
• Bridging QuantLab with LPDNN
• Design of MEMs Sensor Interface
• Precise Ultra-low-power Timer
• Novel Metastability Mitigation Technique
• Analog Compute-in-Memory Accelerator Interface and Integration
• Outdoor Precision Object Tracking for Rockfall Experiments
• Autonomous Sensing For Trains In The IoT Era
• CLIC for the CVA6
• Flexfloat DL Training Framework
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
• Streaming Integer Extensions for Snitch (M/1-2S)
• Efficient Synchronization of Manycore Systems (M/1S)
• Design of combined Ultrasound and Electromyography systems
• Designing a Power Management Unit for PULP SoCs
• A Unified Compute Kernel Library for Snitch (1-2S)
• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
• Hypervisor Extension for Ariane (M)
• Advanced 5G Repetition Combining
• Next Generation Synchronization Signals
• Low-power Temperature-insensitive Timer
• Ultra low power wearable ultrasound probe
• Machine Learning for extracting Muscle features using Ultrasound 2
• Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
• Transforming MemPool into a CGRA (M)
• Multi issue OoO Ariane Backend (M)
• Memory Augmented Neural Networks in Brain-Computer Interfaces
• Hyper-Dimensional Computing Based Predictive Maintenance
• Low Latency Brain-Machine Interfaces
• Minimum Variance Beamforming for Wearable Ultrasound Probes
• Machine Learning for extracting Muscle features using Ultrasound
• Compression of Ultrasound data on FPGA
• Design of a 25 Gbps SerDes for optical chip-to-chip communication
• Inductive Charging Circuit for Implantable Devices
• Ultra-low power transceiver for implantable devices
• High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
• Manycore System on FPGA (M/S/G)
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
• Time Gain Compensation for Ultrasound Imaging
• Neural Networks Framwork for Embedded Plattforms
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
• ISA extensions in the Snitch Processor for Signal Processing (M)
• NVDLA meets PULP
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
• Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
• Floating-Point Divide & Square Root Unit for Transprecision
• TCNs vs. LSTMs for Embedded Platforms
• Timing Channel Mitigations for RISC-V Cores
• A computational memory unit using phase-change memory devices
• Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
• Real-Time ECG Contractions Classification
• Exploring Algorithms for Early Seizure Detection
• Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
• Predictable Execution on GPU Caches
• CMOS power amplifier for field measurements in MRI systems
• Ultra-low power sampling front-end for acquisition of physiological signals
• Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
• Deep Learning for Brain-Computer Interface
• Digital Audio Interface for Smart Intensive Computing Triggering
• Trace Debugger for custom RISC-V Core
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
• Turbo Equalization for Cellular IoT
• IoT Turbo Decoder
• BigPULP: Shared Virtual Memory Multicluster Extensions
• Sensor Fusion for Rockfall Sensor Node
• Intelligent Power Management Unit (iPMU)
• A Wireless Sensor Network for a Smart Building Monitor and Control
• Creating a HDMI Video Interface for PULP
• Standard Cell Compatible Memory Array Design
• A Wireless Sensor Network for HPC monitoring
• Study and Development of Intelligent Capability for Small-Size UAVs
• BigPULP: Multicluster Synchronization Extensions
• LTE-Advanced RF Front-end Design in 28nm CMOS Technology
• Switched Capacitor Based Bandgap-Reference
• Smart Virtual Memory Sharing
• Hardware Accelerated Derivative Pricing
• Glitches Reduce Listening Time of Your iPod
• Internet of Things Network Synchronizer
• Accelerator for Boosted Binary Features
• Accelerator for Spatio-Temporal Video Filtering
• High performance continous-time Delta-Sigma ADC for biomedical applications
• GUI-developement for an action-cam-based eye tracking device
• WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
• System Analysis and VLSI Design of NB-IoT Baseband Processing
• Learning Image Decompression with Convolutional Networks
• FPGA System Design for Computer Vision with Convolutional Neural Networks
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
• 3D Turbo Decoder ASIC Realization
• ASIC Implementation of High-Throughput Next Generation Turbo Decoders
• FPGA-Based Digital Frontend for 3G Receivers
• Spatio-Temporal Video Filtering
• An FPGA-Based Testbed for 3G Mobile Communications Receivers
• Baseband Meets CPU
• Active-Set QP Solver on FPGA
• Vector Processor for In-Memory Computing
• Hardware/software co-programming on the Parallella platform
• Design and Implementation of ultra low power vision system
• Multiuser Equalization and Detection for 3GPP TD-SCDMA
• Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
• Compressed Sensing Reconstruction on FPGA
• A Multiview Synthesis Core in 65 nm CMOS
• High-Throughput Authenticated Encryption Architectures based on Block Ciphers
• Putting Together What Fits Together - GrÆStl