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  • Accelerators for object detection and tracking
    In this project, you will design a hardware accelerator for image system, improving the energy efficiency of the system. The accelerator will
    3 KB (407 words) - 10:57, 5 November 2019
  • Pirmin Vogel
    ...river, runtime and programming model support for efficient and transparent accelerator programming.
    1 KB (193 words) - 15:39, 3 March 2020
  • MatPHY: An Open-Source Physical Layer Development Framework
    ...eiver that is typically implemented on the baseband processor, assisted by accelerator blocks in dedicated hardware including TPU, digital frontend, detector and
    3 KB (360 words) - 14:14, 27 May 2015
  • Evolved EDGE Physical Layer Incremental Redundancy Architecture
    ...the RLC blocks takes place on a PHY Digital Signal Processor (DSP) and an accelerator attached to it.
    3 KB (397 words) - 14:12, 27 May 2015
  • Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
    ...rm. After verifying correct functionality, you will integrate the complete accelerator inside the PULP platform (either in the simulation platform or the FPGA emu ...field of active exciting research to develop a state-of-art neuromorphic accelerator for MPSoC and FPGA targets. You will learn:
    5 KB (784 words) - 14:50, 30 November 2016
  • Hardware Accelerator Integration into Embedded Linux
    ...ffloaded to accelerators to allow for a more efficient execution. One such accelerator determined to solve Gaussian Message Passing algorithms in an efficient way ...he accelerator. At the end of the project, you will be able to control the accelerator from the command line of the Linux system.
    2 KB (236 words) - 09:46, 12 October 2017
  • PULP
    ...alized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator. * [http://asic.ethz.ch/2021/Echoes.html Echoes] PULPissimo system with FFT accelerator, new peripherals and for the first time CV32E40P core.
    10 KB (1,563 words) - 10:09, 19 August 2022
  • Hardware Accelerator for Model Predictive Controller
    [[File:Hardware Accelerator for Model Predictive Controller1.png|400px|thumb]] [[File:Hardware Accelerator for Model Predictive Controller2.png|400px|thumb]]
    3 KB (456 words) - 08:35, 20 January 2021
  • ASIC Design of a Sigma Point Processor
    ...ication specific processors of this type are serve as an signal-processing accelerator in heterogeneous multicore processors. They offer a unique blend of flexibi
    2 KB (265 words) - 08:34, 20 January 2021
  • Design and Implementation of a Convolutional Neural Network Accelerator ASIC
    ...to 90%). The focus of this work is on speeding up this step by creating an accelerator to perform this step faster and more power-efficiently. ...t-yet-published paper of our group by F. Conti and L. Benini on a hardware-accelerator for ConvNets
    9 KB (1,289 words) - 19:45, 24 March 2015
  • Hardware/software co-programming on the Parallella platform
    all available computation resources like CPU, accelerator chip and FPGA. ...a dual-core ARM A9 processor running Linux, a powerful FPGA and a 16-core accelerator chip called "Epiphany III". All these components cores are linked tightly t
    3 KB (501 words) - 14:26, 2 September 2015
  • Convolutional Network Accelerator
    #REDIRECT [[Design and Implementation of a Convolutional Neural Network Accelerator ASIC]]
    90 bytes (11 words) - 12:55, 13 December 2014
  • Active-Set QP Solver on FPGA
    ...focus on the implementation of an Active-Set quadratic program (QP) solver accelerator on FPGA. ...ory:Digital]] [[Category:Master Thesis]] [[Category:Completed]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:ABB CHCRC]] [[Category:Model Predictive Cont
    2 KB (351 words) - 13:09, 2 November 2015
  • LAPACK/BLAS for FPGA
    [[[Category:Digital]] [[Category:Master Thesis]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:ABB CHCRC]] [[Category:Model Predictive Cont
    2 KB (328 words) - 12:38, 1 June 2017
  • Real-Time Stereo to Multiview Conversion
    dedicated hardware accelerator enables portable and energy would serve as a power-efficient hardware accelerator.
    3 KB (509 words) - 09:09, 23 October 2015
  • Acceleration and Transprecision
    ...A Tesla V100.jpg|thumb|right|A NVIDIA Tesla V100 GP-GPU. This cutting-edge accelerator provides huge computational power on a [https://arstechnica.com/gadgets/201 ...b|right|Google's Cloud TPU (Tensor Processing Unit). This machine learning accelerator can do one thing extremely well: multiply-accumulate operations.]]
    2 KB (275 words) - 17:05, 24 November 2023
  • PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
    ...requires the programmer to manually orchestrate DMA transfers between the accelerator's low latency tightly-coupled data memory (TCDM), an L1 scratchpad memory, ...h a software cache similar to [5] that uses part of the TCDM to filter the accelerator's accesses to shared data structures living in main memory, and to spare th
    5 KB (716 words) - 13:43, 29 November 2019
  • FFT-based Convolutional Network Accelerator
    ...focus of this work is on speeding up this step by creating an ASIC or FPGA accelerator to perform this step faster and more power-efficiently in the frequency dom
    8 KB (1,145 words) - 11:30, 5 February 2016
  • PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
    ...ort the accelerator coherency port (ACP) of the Zynq SoC, which allows the accelerator to access the low-latency on-chip memories of the host including L1 and L2 : 10% User-space Runtime and Application Development for Host and Accelerator
    4 KB (585 words) - 17:57, 7 November 2017
  • Optimization of a Binary Feature Extraction Core using Approximation
    #REDIRECT [[Accelerator for Boosted Binary Features]]
    53 bytes (6 words) - 18:14, 14 April 2016
  • Efficient Implementation of an Active-Set QP Solver for FPGAs
    ...ystem integration aspects. Eventually, the goal is to attach the developed accelerator to the ARM processing system on the Xilinx Zynq platform, and establish the [[Category:Digital]] [[Category:Master Thesis]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:ABB CHCRC]] [[Category:Model Predictive Cont
    4 KB (542 words) - 12:39, 1 June 2017
  • Design of State Retentive Flip-Flops
    ...ate. While this is acceptable for some sub-circuits, like a small hardware accelerator with no relevant information to be retained between two calls, it is not ac
    2 KB (364 words) - 09:34, 25 July 2017
  • FPGA System Design for Computer Vision with Convolutional Neural Networks
    ...e have several aspects which we would like to explore: porting the Origami accelerator to run efficiently on the FPGA, hardware/software-co-design configuring mem ...Mayer, S. Willi, B. Muheim, L. Benini, “Origami: A Convolutional Network Accelerator,” in Proceedings of the 25th Edition on Great Lakes Symposium on VLSI, 20
    3 KB (397 words) - 18:17, 29 August 2016
  • Rethinking our Convolutional Network Accelerator Architecture
    ...e time is spent performing the convolutions (80% to 90%). We have built an accelerator for this, Origami, which has been very successful. Nevertheless, it has som ...Samuel Willi, Beat Muheim, Luca Benini, "Origami: A Convolutional Network Accelerator", Proc. ACM/IEEE GLS-VLSI'15 [http://dl.acm.org/citation.cfm?id=2743766] [h
    9 KB (1,263 words) - 18:52, 12 December 2016
  • A Hardware Architecture for Real-Time Saliency Estimation
    #REDIRECT [[Accelerator for Spatio-Temporal Video Filtering]]
    61 bytes (6 words) - 18:44, 14 April 2016
  • PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
    ...running on the host CPU [1,2] and a dedicated helper thread running on the accelerator [3]. The first IOTLB is implemented using a fully-associative content addre ...ns through, e.g., an mmap() system call. Ideally, all data shared with the accelerator is placed in this section, requiring a single entry in the first IOTLB only
    6 KB (866 words) - 13:43, 29 November 2019
  • Bringing XNOR-nets (ConvNets) to Silicon
    ...hem better and use their structure to build an even more efficient ConvNet accelerator with almost no multipliers and relatively small adders. ...Benini, L. (2016). YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights. arXiv preprint arXiv:1606.05487. [https://arxiv.or
    10 KB (1,357 words) - 16:25, 30 October 2020
  • Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
    ...field of active exciting research to develop a state-of-art neuromorphic accelerator for MPSoC and FPGA targets. You will learn:
    9 KB (1,427 words) - 18:36, 5 September 2019
  • Single-Bit-Synapse Spiking Neural System-on-Chip
    ...field of active exciting research to develop a state-of-art neuromorphic accelerator for MPSoC and FPGA targets. You will learn:
    7 KB (1,000 words) - 12:22, 13 January 2017
  • PULP-Shield for Autonomous UAV
    ...directly connected to the Himax ULP camera [7] and a second connecting the accelerator to the existing MCU. ...Palossi, A. Marongiu, D. Rossi and L. Benini, "Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms," 2016 Design, Automatio
    6 KB (875 words) - 11:06, 23 February 2018
  • Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
    ...and Luca Benini. "YodaNN: An ultra-low power convolutional neural network accelerator based on binary weights." In VLSI (ISVLSI), 2016 IEEE Computer Society Annu
    6 KB (823 words) - 08:36, 20 January 2021
  • Autoencoder Accelerator for On-Chip Semi-Supervised Learning
    In this thesis, the students will develop an optimized Deconvolution Accelerator which can be used to implement state-of-the-art neural networks with a deco
    6 KB (842 words) - 08:37, 20 January 2021
  • Hardware Accelerators for Lossless Quantized Deep Neural Networks
    ...n a field of active exciting research to develop a state-of-art inference accelerator for MPSoC and FPGA targets. You will learn:
    6 KB (949 words) - 13:41, 10 November 2020
  • Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
    ...nstitute of Neuroinformatics designed '''''NullHop''''' [Aimar2017], a CNN accelerator architecture which can support the implementation of state of the art CNNs ...mar2017] A. Aimar et al., NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps [https://arxiv.org/pdf/1706
    7 KB (1,001 words) - 10:43, 26 June 2017
  • BigPULP: Multicluster Synchronization Extensions
    ...-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integrati ...oading of highly-parallel OpenMP function kernels from the host CPU to the accelerator [2], and
    6 KB (805 words) - 12:17, 22 January 2018
  • BigPULP: Shared Virtual Memory Multicluster Extensions
    ...-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integrati ...oading of highly-parallel OpenMP function kernels from the host CPU to the accelerator [2], and
    6 KB (801 words) - 15:05, 23 August 2018
  • Smart Virtual Memory Sharing
    The main difficulty in traditional accelerator programming stems from a widely coherent caches and virtual memory. The accelerator features local, private
    6 KB (865 words) - 12:16, 17 November 2017
  • Zksnark
    #REDIRECT [[Elliptic Curve Accelerator for zkSNARKS]]
    53 bytes (6 words) - 09:54, 24 August 2018
  • High Speed FPGA Trigger Logic for Particle Physics Experiments
    #If interested: Commissioning of the unit in particle accelerator beam line experiment at PSI
    4 KB (460 words) - 21:42, 30 January 2018
  • HERO: TLB Invalidation
    ...-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integrati ...oading of highly-parallel OpenMP function kernels from the host CPU to the accelerator [2], and
    6 KB (796 words) - 17:19, 18 November 2019
  • Shared Correlation Accelerator for an RF SoC
    ...cated circuit for each standard, we would like to share a single, flexible accelerator for all these tasks. [[File:Correlation acc.png|450px|thumb|Concept for the shared correlation accelerator.]]
    3 KB (421 words) - 09:38, 14 September 2018
  • Heterogeneous SoCs
    ...onfigurable, and extensible FPGA implementation of a programmable manycore accelerator (also developed in our group as part of the [http://pulp-platform.org/ PULP ...k that supports OpenMP 4.5 and Shared Virtual Memory (SVM) for transparent accelerator programming.
    3 KB (421 words) - 18:41, 28 October 2020
  • Predictable Execution
    ...to the removal of the need for data transfers between the host CPU and the accelerator. ...ecome a problem, as contention for the shared resource between the CPU and accelerator lead to performance degradation. This in turn introduces the risk of unboun
    2 KB (286 words) - 18:48, 10 November 2020
  • Energy Efficient Autonomous UAVs
    ...., "Exploring Single Source Shortest Path Parallelization on Shared Memory Accelerator", ''19th International Workshop on Software and Compilers for Embedded Syst
    14 KB (2,077 words) - 15:02, 13 June 2022
  • Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
    ...al Dev Board, a compact board with an edge tensor processing unit (TPU) AI accelerator chip speeds up machine learning. A new family of classification models -- N
    7 KB (1,003 words) - 17:30, 6 December 2021
  • Andreas Kurth
    ...del, runtime, compiler, and hardware support for efficient and transparent accelerator programming and data sharing.
    1 KB (123 words) - 07:40, 11 June 2021
  • A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
    * [6] F. Conti et Al., "Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms," ''2016 Design, Automat
    4 KB (605 words) - 16:35, 20 February 2018
  • Monocular Vision-based Object Following on Nano-size Robotic Blimp
    * Basic knowledge of parallel programming and ''Host/Accelerator'' paradigm.
    5 KB (623 words) - 16:14, 20 February 2018
  • Predictable Execution on GPU Caches
    .... Such platforms include multi-core CPU processors and heterogeneous CPU + accelerator system-on-chips (SoCs). Enabling the use of heterogeneous platforms in safe
    5 KB (706 words) - 17:41, 19 June 2019
  • Freedom from Interference in Heterogeneous COTS SoCs
    .... Such platforms include multi-core CPU processors and heterogeneous CPU + accelerator system-on-chips (SoCs). Enabling the use of heterogeneous platforms in safe
    4 KB (499 words) - 17:40, 19 June 2019
  • IBM Research
    | MA|| Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture || [https://iis-projects.ee.ethz.ch/images/8/83/ADS_Routing.pd
    9 KB (1,330 words) - 15:20, 15 March 2024
  • Analog Compute-in-Memory Accelerator Interface and Integration
    ...ices can be exploited as the basic cell of analog compute-in-memory (AciM) accelerator for MAC operation that can significantly outperform the current state-of-th ...ject is to design the interface for the ACiM accelerator and integrate the accelerator into a modern microcontroller system.
    3 KB (352 words) - 18:02, 16 December 2022
  • Elliptic Curve Accelerator for zkSNARKs
    ...In this project you would investigate the feasibility of an elliptic curve accelerator for the specific curves used in ZCash. You will devise an optimal architect
    5 KB (614 words) - 15:02, 4 March 2019
  • Elliptic Curve Accelerator for zkSNARKS
    #REDIRECT [[Elliptic Curve Accelerator for zkSNARKs]]
    53 bytes (6 words) - 10:18, 24 August 2018
  • Stand-Alone Edge Computing with GAP8
    ...sensing devices. Thanks to its 8 RISC-V cores and its convolution hardware accelerator, GAP8 can perform complex computation with a mW-range power budget. In our
    3 KB (363 words) - 14:38, 14 April 2021
  • NVDLA meets PULP
    ...we would like to find out if and how NVDLA can be a companion, competitor, accelerator, or encompassing framework to the PULP project and the accelerators/process ...pose of this project is to get the [http://nvdla.org/ NVIDIA Deep Learning Accelerator] up and running, implement it in a modern ASIC technology node, and compare
    6 KB (799 words) - 13:42, 10 November 2020
  • Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
    ...e. The new L1 interconnect will be tested together with a state-of-the-art accelerator for Binary Neural Networks, constituting a very important component for for ...n a field of active exciting research to develop a state-of-art inference accelerator for MPSoC and FPGA targets. You will learn:
    7 KB (961 words) - 21:21, 29 January 2019
  • ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
    ...rocessing algorithm to an ML accelerator, e.g., a Google Coral device. The accelerator will be paired with a portable IoT camera, and the algorithm's predictions * Familiarization with ML accelerator
    6 KB (735 words) - 12:12, 23 July 2023
  • Heroino: Design of the next CORE-V Microcontroller
    *Accelerator **0x230_0000 - 0x23f_ffff: Accelerator
    9 KB (1,314 words) - 00:01, 7 February 2021
  • PREM Intervals and Loop Tiling
    .... Such platforms include multi-core CPU processors and heterogeneous CPU + accelerator system-on-chips (SoCs). Enabling the use of heterogeneous platforms in safe
    4 KB (531 words) - 18:00, 19 June 2019
  • Compiler Profiling and Optimizing
    .... Such platforms include multi-core CPU processors and heterogeneous CPU + accelerator system-on-chips (SoCs). Enabling the use of heterogeneous platforms in safe
    3 KB (466 words) - 18:20, 19 June 2019
  • Manycore System on FPGA (M/S/G)
    ...is chip features an ARM host core, which we use as a host to our many-core accelerator system.
    8 KB (1,319 words) - 10:41, 6 July 2021
  • Hardware Acceleration
    ...A Tesla V100.jpg|thumb|right|A NVIDIA Tesla V100 GP-GPU. This cutting-edge accelerator provides huge computational power on a [https://arstechnica.com/gadgets/201 ...b|right|Google's Cloud TPU (Tensor Processing Unit). This machine learning accelerator can do one thing extremely well: multiply-accumulate operations.]]
    7 KB (917 words) - 17:04, 24 November 2023
  • Event-Driven Convolutional Neural Network Modular Accelerator
    ...to use, and in the number of physical computing engines instantiated. The accelerator operations are orchestrated by an RISCV core programmed through a JTAG inte
    4 KB (651 words) - 19:10, 29 January 2021
  • Spiking Neural Network for Autonomous Navigation
    ...nally the network will be quantized and deployed on Spiking Neural Network accelerator designed in the lab. 4. Quantize and deploy the network on a PULP system equipped with modular SNN accelerator, and evaluate the accuracy loss caused by the quantization
    4 KB (644 words) - 19:10, 29 January 2021
  • Semi-Custom Digital VLSI for Processing-in-Memory
    ...Bobbett, A. Gallyas-Sanhueza, and C. Studer, "PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations," IEEE 30th International Confere
    7 KB (882 words) - 14:33, 28 July 2021
  • Hyper-Dimensional Computing Based Predictive Maintenance
    ...lgorithm should be tuned to be portable to an ultra-low power HDC hardware accelerator that allows execution of HDC algorithms in the uW power envelope.
    5 KB (759 words) - 09:18, 16 September 2021
  • Mapping Networks on Reconfigurable Binary Engine Accelerator
    ...orks NEMO [2] (or Quantlab [3]) and DORY[4,5] to map networks onto the RBE accelerator and evaluate their performance and energy efficiency for real networks. The RBE accelerator consists out of three parts:
    6 KB (814 words) - 09:55, 8 March 2023
  • Improved State Estimation on PULP-based Nano-UAVs
    * Basic knowledge of parallel programming and ''Host/Accelerator'' paradigm, or willing to learn
    8 KB (1,117 words) - 22:17, 26 January 2022
  • Deep Learning-based Global Local Planner for Autonomous Nano-drones
    * Basic knowledge of parallel programming and ''Host/Accelerator'' paradigm, or willing to learn
    4 KB (571 words) - 12:11, 27 January 2022
  • An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
    ...this projet is the development of a hardware matrix-vector multiplication accelerator that solely relies on standard cells as state holding elements of the desig ...will have the oportunity to tapeout the microcontroller including your HW accelerator as part of a TSMC65nm multi-project-waver (MPW) run, which will give you pr
    7 KB (1,032 words) - 15:31, 16 November 2020
  • Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
    ...Dynamic Vision Sensors with Sparse Hyperdimensional Computing: A Low-power Accelerator with Online Learning Capability
    5 KB (707 words) - 09:23, 16 September 2021
  • (M/1-2S): A Snitch-based Compute Accelerator for HERO
    #Redirect [[A Snitch-based Compute Accelerator for HERO (M/1-2S)]]
    66 bytes (10 words) - 21:47, 10 November 2020
  • Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
    ...s are shared or recomputed, if parts of the computation is offloaded to an accelerator, and so on.
    5 KB (737 words) - 17:26, 2 November 2020
  • A Flexible Peripheral System for High-Performance Systems on Chip (M)
    ...si, A. Pullini, I. Loi, and L. Benini, “PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision,” ''J. Signal Process.
    11 KB (1,675 words) - 15:40, 15 March 2021
  • Modular Spiking Neural Network Accelerator
    #REDIRECT [[Event-Driven Convolutional Neural Network Modular Accelerator]]
    75 bytes (7 words) - 09:36, 5 August 2020
  • A Snitch-based Compute Accelerator for HERO (M/1-2S)
    <!-- (M/1-2S): A Snitch-based Compute Accelerator for HERO --> ...xchangeable. HERO features a shared virtual memory system between host and accelerator and provides a heterogeneous compiler toolchain with OpenMP support for acc
    11 KB (1,617 words) - 23:59, 6 February 2021
  • Energy Efficient SoCs
    ...A Tesla V100.jpg|small|right|A NVIDIA Tesla V100 GP-GPU. This cutting-edge accelerator provides huge computational power on a [https://arstechnica.com/gadgets/201 ...b|right|Google's Cloud TPU (Tensor Processing Unit). This machine learning accelerator can do one thing extremely well: multiply-accumulate operations.]]
    3 KB (339 words) - 15:59, 1 November 2023
  • VLSI Implementation of a 5G Ciphering Accelerator
    ...ng the low-latency demands for URLLC. In a second part of the project, the accelerator architecture will be ported to HDL and an ASIC implementation will be deriv
    3 KB (404 words) - 10:05, 9 February 2021
  • MemPool on HERO (1S)
    ...agram of HERO. It features a shared virtual memory system between host and accelerator and provides a heterogeneous compiler toolchain with OpenMP support for acc * '''Preparing the MemPool cluster for acting as an accelerator in HERO'''
    6 KB (902 words) - 19:07, 20 January 2021
  • Efficient TNN compression
    ...evaluation of the compressor and decompressor with an ultra-low power TNN accelerator (CUTIE [2])
    3 KB (438 words) - 08:41, 17 February 2021
  • A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
    ...in heterogeneous SoCs or manycore applications. Snitch features a flexible accelerator interface, allowing it to be paired with a powerful FPU to achieve high FPU ...systems, like observing and optimizing the energy consumption of a compute accelerator.
    8 KB (1,220 words) - 15:18, 9 July 2021
  • Efficient TNN Inference on PULP Systems
    ...ell-established flow for training them. While we have already developed an accelerator (CUTIE, see references), the execution of TNNs on microcontrollers - such a
    5 KB (768 words) - 15:14, 4 August 2022
  • Wearables in Fashion
    Designing the thousandth machine learning (ML) accelerator is not what you are looking for? Where others see a breakthrough in energy-
    3 KB (463 words) - 08:38, 23 November 2022
  • Implementation of an AES Hardware Processing Engine (B/S)
    ...large amounts of data. A solution to this problem is a dedicated hardware accelerator that directly operates on the data that should be en-/decrypted. This project proposes to implement an AES accelerator for the PULP platform [2], interfacing as a Hardware Processing Engine (HWP
    2 KB (267 words) - 19:14, 6 December 2021
  • Huawei Research
    ...oject, we would like to evaluate the actual benefits in HW by designing an accelerator exploiting the new algorithm. || AI Acceleration || digital VLSI design || * Mapping of data, parameters and computations from a ML framework to the HW Accelerator.
    6 KB (799 words) - 11:11, 1 August 2022
  • Ibex: Tightly-Coupled Accelerators and ISA Extensions
    ...n the context of a single-core or multi-core system such as PULP where the accelerator is shared by multiple Ibex cores. ...xperience/skill set/team/project duration, select an existing co-processor accelerator to interface or a new one to develop from scratch.
    6 KB (835 words) - 12:52, 27 April 2021
  • Ternary Neural Networks for Face Recognition
    ...e it for accuracy and prepare it for deployment on CUTIE, our in-house TNN accelerator.
    3 KB (404 words) - 09:54, 8 March 2023
  • Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
    <!-- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) --> This thesis' goal is to develop a small and energy vector accelerator unit, and integrate it with MemPool.
    11 KB (1,609 words) - 10:00, 30 June 2022
  • Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
    * Interest in embedded machine learning applications and/or accelerator design
    3 KB (497 words) - 22:15, 23 November 2022
  • XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
    ...Bobbett, A. Gallyas-Sanhueza, and C. Studer, "PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations," IEEE 30th International Confere
    7 KB (933 words) - 19:29, 21 November 2021
  • Integrating Hardware Accelerators into Snitch (1S)
    ...eexplore.ieee.org/abstract/document/8412533 XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference]
    4 KB (567 words) - 13:57, 7 September 2022
  • Non-blocking Algorithms in Real-Time Operating Systems
    ...P [6] [7] [8] compromising a single RISC-V controller core and eigh RISC-V accelerator cores extended to support real-time applications, can be used. Programs can
    4 KB (508 words) - 18:59, 10 January 2022
  • Real-Time Embedded Systems
    ...ecome a problem, as contention for the shared resource between the CPU and accelerator lead to performance degradation. This in turn introduces the risk of unboun
    4 KB (518 words) - 09:54, 10 January 2022
  • Streaming Integer Extensions for Snitch (M/1-2S)
    Recently, we explored two new accelerator-based extensions for Snitch [3], both of which aim to boost performance and ** Possibly switch to a standardized accelerator interface such as X-interface
    6 KB (770 words) - 14:19, 15 September 2022
  • Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
    ...lel Processor in Associative Content-Addressable Memory) [1] is a hardware accelerator that aims at accelerating not only matrix-vector products, but also other, ...Bobbett, A. Gallyas-Sanhueza, and C. Studer, "PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations," IEEE 30th International Confere
    7 KB (804 words) - 19:45, 21 November 2021
  • HW/SW Safety and Security
    ...ples a RISC-V controller core with a cluster of eight RISC-V cores used as accelerator for various control intensive applications in this case a control loop invo
    5 KB (614 words) - 09:49, 15 January 2024
  • Fast Accelerator Context Switch for PULP
    <!-- Fast Accelerator Context Switch For PULP --> ...troller core with a cluster of eight RISC-V cores used as accelerator. The accelerator needs a better mechanism to manage its state for context switching.]]
    6 KB (835 words) - 16:27, 7 July 2023
  • Improved Collision Avoidance for Nano-drones
    * Basic knowledge of parallel programming and ''Host/Accelerator'' paradigm, or willing to learn
    4 KB (550 words) - 21:25, 15 February 2022
  • A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
    * Basic knowledge of parallel programming and ''Host/Accelerator'' paradigm, or willing to learn
    4 KB (489 words) - 14:33, 17 May 2022
  • Event-based navigation on autonomous nano-drones
    * [3] SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions. https://arxiv.org/abs/2204.10687
    4 KB (505 words) - 18:25, 26 July 2022
  • Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
    ...that transposes matrices while they are copied throughout the system. The accelerator should work of full-precision integer and floating point formats for genera
    2 KB (214 words) - 09:39, 23 August 2023
  • Bandwidth Efficient NEureka
    * XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference https://ieeexplore.ieee.o
    4 KB (585 words) - 14:05, 15 February 2024
  • Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
    Study novel accelerator design for transformers. System and method for an optimized Winograd convolution accelerator
    4 KB (549 words) - 11:35, 3 November 2023
  • Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
    <!-- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1 [[File:maddness_floorplan.png|thumb|350px|Floorplan or the Maddness Accelerator.]]
    6 KB (846 words) - 16:50, 3 November 2022
  • Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
    <!-- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1 ...:maddness_floorplan.png|thumb|350px|Figure 1: Clock layout of the MADDness accelerator using ASAP7 technology]]
    6 KB (823 words) - 16:32, 3 November 2022
  • Virtual Memory Ara
    ...om an update to the last specifications RVV 1.0. Ara behaves like a vector accelerator coupled with CVA6, one of the most mature open-source RV64GC cores and now
    5 KB (769 words) - 11:38, 3 November 2023
  • Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
    ...ator comprising 216 energy-efficient 32-bit RISC-V Snitch cores [4,5]. The accelerator cores are tightly coupled to a set of software-managed L1 scratch-pad memor ...the host (CVA6 core), while parallel code regions can be offloaded to the accelerator to take advantage of its higher energy efficiency and peak performance.
    7 KB (944 words) - 10:47, 25 January 2024
  • All the flavours of FFT on MemPool (1-2S/B)
    ...eless communications. Another option is also the integration of a PULP FFT accelerator [[#ref-Bertaccini|&#91;3&#93;]] in the MemPool Tile.
    3 KB (460 words) - 18:54, 9 November 2022
  • Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
    ...and performance improvement. Spatz lean Processing Element (PE) acts as an accelerator to a scalar core, which is a good candidate for achieving ideal hardware ut
    6 KB (775 words) - 11:57, 31 October 2023
  • FPGA mapping of RPC DRAM
    ...ire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” https://ieeexplore.ieee.org/abstract/document/10163410 </div>
    3 KB (484 words) - 20:29, 21 February 2024
  • Cycle-Accurate Event-Based Simulation of Snitch Core
    ...ded instruction can execute as soon as all operands are available, and the accelerator interface can accept a new offloading request. ...pically used together with an FPU, whose instructions are implemented as ''accelerator instructions''. The FPU typically features SIMD, Minifloat (8-bit, 16-bit),
    14 KB (2,018 words) - 22:54, 23 November 2023
  • Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
    ...(VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at significantly lower latencies and wit
    3 KB (356 words) - 14:53, 11 October 2023
  • A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
    ...computations [1, 2]. Snitch features an integer core and a floating-point accelerator, which can operate in parallel to some extent. It implements two custom ISA
    7 KB (962 words) - 12:53, 7 March 2024
  • Transformer Deployment on Heterogeneous Many-Core Systems
    ...d operational scheme. For this reason, we developed an Integer Transformer Accelerator (ITA) that can efficiently perform self-attention and integrated it into a ...tudent will then extend the deployment pipeline made in T1 to generate the accelerator code to control ITA. Additionally, he/she will have to parallelize and tile
    6 KB (858 words) - 14:52, 23 October 2023
  • Softmax for Transformers (M/1-2S)
    ...k due to the softmax function. Addressing this limitation, our transformer accelerator ITA [2] introduces ITAmax, a hardware-friendly softmax implementation. ITAm ...://arxiv.org/abs/2307.03493 ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers]
    4 KB (573 words) - 14:46, 23 October 2023
  • Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture
    #REDIRECT [[Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)]]
    110 bytes (11 words) - 10:31, 28 August 2023
  • Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
    * 40% Implementing Snitch-based in-network accelerator, creating SsPIN ...er Timo, Beranek Jakub, Benini Luca, Hoefler Torsten. "A RISC-V in-network accelerator for flexible high-performance low-power packet processing." 2021 ACM/IEEE 4
    3 KB (374 words) - 10:24, 3 November 2023
  • Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
    ...lgorithms will be tested on an existing FZ3 Card, a powerful deep-learning accelerator card based on Xilinx Zynq UltraScale+ ZU3EG MPSoC. The overall goal will be * Devise a parallel HW accelerator for OA image reconstruction.
    3 KB (410 words) - 15:27, 23 October 2023
  • Physical Implementation of ITA (2S)
    ...ow dependencies. To solve this issue, we designed ITA, Integer Transformer Accelerator [2], that targets efficient transformer inference on embedded systems by ex ...ution cycle of the attention mechanism. In contrast to throughput-oriented accelerator designs, which typically employ systolic arrays, ITA implements its process
    4 KB (577 words) - 10:52, 12 December 2023
  • 3D Matrix Multiplication Unit for ITA (1S)
    ...ow dependencies. To solve this issue, we designed ITA, Integer Transformer Accelerator [2], that targets efficient transformer inference on embedded systems by ex ...ution cycle of the attention mechanism. In contrast to throughput-oriented accelerator designs, which typically employ systolic arrays, ITA implements its process
    3 KB (485 words) - 10:52, 12 December 2023
  • Streaming Layer Normalization in ITA (M/1-2S)
    ...ow dependencies. To solve this issue, we designed ITA, Integer Transformer Accelerator [2], that targets efficient transformer inference on embedded systems by ex ...ution cycle of the attention mechanism. In contrast to throughput-oriented accelerator designs, which typically employ systolic arrays, ITA implements its process
    4 KB (511 words) - 12:38, 21 December 2023
  • Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
    ...and performance improvement. Spatz lean Processing Element (PE) acts as an accelerator to a scalar core, which is a good candidate for achieving ideal hardware ut - Aligning the accelerator interface between the latest 64-bit Spatz Cluster, MemPool, and TeraPool-ba
    6 KB (844 words) - 11:41, 31 October 2023
  • A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
    <!-- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) -->
    3 KB (342 words) - 13:02, 12 February 2024
  • A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks
    #REDIRECT [[A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)]]
    100 bytes (13 words) - 11:05, 2 November 2023
  • Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
    ...reating Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) --> ...dedicated special-purpose buffer. Our idea is to create such a reshuffling accelerator (inside of iDMA) using the already present cluster TCDM as its buffer.
    2 KB (314 words) - 10:27, 3 November 2023
  • Taping a Safer Silicon Implementation of Snitch (M/2-3S)
    ...ently started testing Occamy, our massive 434-core general-purpose compute accelerator based on the Snitch architecture. We can successfully run code on the two L
    2 KB (314 words) - 18:47, 24 November 2023
  • Implementation of an Accelerator for Retentive Networks (1-2S)
    <!-- Implementation of an Accelerator for Retentive Networks (M/1-2S) --> In this project, we aim to lay the foundation for a retention accelerator that is able to execute the main layers in Retentive Networks with little t
    5 KB (735 words) - 14:31, 18 February 2024
  • Advanced Data Movers for Modern Neural Networks
    ...ent data movement, we developed a performant, reconfigurable data movement accelerator (iDMA) for embedded edge computing systems. ...and-true PULPissimo SoC architecture by integrating the iDMA data movement accelerator. To validate correct integration and as a concrete large-scale use case, no
    3 KB (418 words) - 16:18, 23 November 2023
  • Writing a Hero runtime for EPAC (1-3S/B)
    ...heterogeneous chip contains four RISC-V Avispado cores along with two STX accelerator tiles and one Variable floating point precision core. ''Source: [https://www.european-processor-initiative.eu/accelerator/]''
    4 KB (501 words) - 15:27, 15 February 2024
  • Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
    ...ators by explicitly specifying the code regions amenable to execute on the accelerator.
    3 KB (461 words) - 12:19, 12 February 2024
  • Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
    ...level for a future SoC gathering a Cheshire host subsystem with a Mempool accelerator subsystem. ...SoC using System Verilog and verify the communication between the Host and Accelerator subsystems.
    3 KB (482 words) - 15:57, 13 February 2024
  • Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
    <!-- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) --> ...ce with its 96 Tensix cores (each containing 5 RISC-V processors, a tensor accelerator, a vector co-processor and up to 1.5MB of SRAM). The Grayskull card comes w
    3 KB (459 words) - 13:24, 12 April 2024
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