Pages with the most revisions
From iis-projects
Showing below up to 100 results in range #251 to #350.
View (previous 100 | next 100) (20 | 50 | 100 | 250 | 500)
- Time and Frequency Synchronization in LTE Cat-0 Devices (9 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory (9 revisions)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (9 revisions)
- Integrating Hardware Accelerators into Snitch (9 revisions)
- Automatic unplugging detection for Ultrasound probes (9 revisions)
- Real-Time Pedestrian Detection For Privacy Enhancement (9 revisions)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (9 revisions)
- Harald Kröll (9 revisions)
- A Multiview Synthesis Core in 65 nm CMOS (9 revisions)
- Improved Reacquisition for the 5G Cellular IoT (9 revisions)
- DC-DC Buck converter in 65nm CMOS (9 revisions)
- Energy Efficient SoCs (9 revisions)
- Runtime partitioning of L1 memory in Mempool (M) (9 revisions)
- Configurable Ultra Low Power LDO (9 revisions)
- Gomeza old project2 (9 revisions)
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology (9 revisions)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) (8 revisions)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (8 revisions)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 revisions)
- Physical Implementation of ITA (2S) (8 revisions)
- Weekly Reports (8 revisions)
- A Unified Compute Kernel Library for Snitch (1-2S) (8 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- Streaming Layer Normalization in ITA (M/1-2S) (8 revisions)
- OTDOA Positioning for LTE Cat-M (8 revisions)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 revisions)
- Resource Partitioning of RPC DRAM (8 revisions)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (8 revisions)
- Object Detection and Tracking on the Edge (8 revisions)
- Evaluating SoA Post-Training Quantization Algorithms (8 revisions)
- (M/1-2S): A Snitch-based Compute Accelerator for HERO (8 revisions - redirect page)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- NVDLA meets PULP (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 revisions)
- An FPGA-Based Evaluation Platform for Mobile Communications (8 revisions)
- Sandro Belfanti (8 revisions)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (8 revisions)
- Learning at the Edge with Hardware-Aware Algorithms (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (8 revisions)
- Wireless EEG Acquisition and Processing (8 revisions)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- Evaluating the RiscV Architecture (8 revisions)
- Flexible Electronic Systems and Epidermal Devices (8 revisions - redirect page)
- Pirmin Vogel (8 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (8 revisions)
- Implementing Hibernation on the ARM Cortex M0 (8 revisions)
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC (8 revisions)
- BCI-controlled Drone (8 revisions)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs (8 revisions)
- Manycore System on FPGA (M/S/G) (8 revisions)
- Fast Wakeup From Deep Sleep State (8 revisions)
- Multi issue OoO Ariane Backend (M) (8 revisions)
- Deep Convolutional Autoencoder for iEEG Signals (8 revisions)
- ASIC Implementation of Jammer Mitigation (8 revisions)
- PREM Runtime Scheduling Policies (8 revisions)
- Development of a fingertip blood pressure sensor (8 revisions)
- Hypervisor Extension for Ariane (M) (8 revisions)
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications (8 revisions)
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format (8 revisions)
- Hardware/software co-programming on the Parallella platform (8 revisions)
- Ultra Low-Power Oscillator (8 revisions)
- Modular Distributed Data Collection Platform (8 revisions)
- A Trustworthy Three-Factor Authentication System (8 revisions)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (8 revisions)
- SCMI Support for Power Controller Subsystem (8 revisions)
- Linux Driver for fine-grain and low overhead access to on-chip performance counters (8 revisions)
- Fault-Tolerant Floating-Point Units (M) (8 revisions)
- A computational memory unit using phase-change memory devices (8 revisions)
- Development of an implantable Force sensor for orthopedic applications (7 revisions)
- Fault Tolerance (7 revisions)
- Streaming Integer Extensions for Snitch (M/1-2S) (7 revisions)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (7 revisions)
- Autonomous Sensing For Trains In The IoT Era (7 revisions)
- LTE IoT Network Synchronization (7 revisions)
- EEG earbud (7 revisions)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (7 revisions)
- Development of statistics and contention monitoring unit for PULP (7 revisions)
- IoT Turbo Decoder (7 revisions)
- Charging System for Implantable Electronics (7 revisions)
- Internet of Things Network Synchronizer (7 revisions)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (7 revisions)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (7 revisions)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S) (7 revisions)
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients (7 revisions)
- Gomeza old project5 (7 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (7 revisions)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (7 revisions)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (7 revisions)
- Bateryless Heart Rate Monitoring (7 revisions)
- SW/HW Predictability and Security (7 revisions)
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT (7 revisions)
- FFT HDL Code Generator for Multi-Antenna mmWave Communication (7 revisions)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver (7 revisions)
- RVfplib (7 revisions)
- Compressed Sensing for Wireless Biosignal Monitoring (7 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (1M) (7 revisions)
