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From iis-projects
Showing below up to 100 results in range #51 to #150.
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- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration (20 revisions)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (20 revisions)
- Accelerator for Boosted Binary Features (20 revisions)
- Accelerator for Spatio-Temporal Video Filtering (20 revisions)
- FFT-based Convolutional Network Accelerator (19 revisions)
- Trace Debugger for custom RISC-V Core (19 revisions)
- Wireless Communication Systems for the IoT (19 revisions)
- PULP’s CLIC extensions for fast interrupt handling (19 revisions)
- 4th Generation Synchronization (19 revisions)
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE (18 revisions)
- Improving Scene Labeling with Hyperspectral Data (18 revisions)
- Flexfloat DL Training Framework (18 revisions)
- David J. Mack (18 revisions)
- Mapping Networks on Reconfigurable Binary Engine Accelerator (18 revisions)
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders (18 revisions)
- Baseband Meets CPU (17 revisions)
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs (17 revisions)
- Energy Efficient AXI Interface to Serial Link Physical Layer (17 revisions)
- Fast Accelerator Context Switch for PULP (17 revisions)
- Streaming Integer Extensions for Snitch (M) (17 revisions - redirect page)
- Energy Efficient Circuits and IoT Systems Group (17 revisions)
- Compressed Sensing vs JPEG (17 revisions)
- A Snitch-based Compute Accelerator for HERO (17 revisions)
- BLISS - Battery-Less Identification System for Security (17 revisions)
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (17 revisions)
- Heterogeneous SoCs (16 revisions)
- Optimal System Duty Cycling for a Mobile Health Platform (16 revisions)
- LightProbe (16 revisions)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S) (16 revisions)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications (16 revisions)
- 3D Turbo Decoder ASIC Realization (16 revisions)
- Rethinking our Convolutional Network Accelerator Architecture (16 revisions)
- Completed (15 revisions)
- Active-Set QP Solver on FPGA (15 revisions)
- Digital Transmitter for Mobile Communications (15 revisions)
- PULP-Shield for Autonomous UAV (15 revisions)
- Vector Processor for In-Memory Computing (15 revisions)
- Elliptic Curve Accelerator for zkSNARKs (15 revisions)
- Big Data Analytics Benchmarks for Ara (15 revisions)
- Digital Beamforming for Ultrasound Imaging (15 revisions)
- DMA Streaming Co-processor (15 revisions)
- Advanced 5G Repetition Combining (15 revisions)
- Design of an LTE Module for the Internet of Things (15 revisions)
- Application Specific Frequency Synthesizers (Analog/Digital PLLs) (14 revisions)
- Ultra low power wearable ultrasound probe (14 revisions)
- ASIC Design of a Gaussian Message Passing Processor (14 revisions)
- Beamspace processing for 5G mmWave massive MIMO on GPU (14 revisions)
- HW/SW Safety and Security (14 revisions)
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B) (14 revisions)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S) (14 revisions)
- Heroino: Design of the next CORE-V Microcontroller (14 revisions)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications (14 revisions)
- Finite Element Simulations of Transistors for Quantum Computing (14 revisions)
- High-speed Scene Labeling on FPGA (14 revisions)
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC (13 revisions)
- Deep Learning for Brain-Computer Interface (13 revisions)
- Efficient collective communications in FlooNoC (1M) (13 revisions)
- Towards global Brain-Computer Interfaces (13 revisions)
- CLIC for the CVA6 (13 revisions)
- Level Crossing ADC For a Many Channels Neural Recording Interface (13 revisions)
- Shared Correlation Accelerator for an RF SoC (13 revisions)
- Turbo Equalization for Cellular IoT (13 revisions)
- On-chip clock synthesizer design and porting (13 revisions)
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT (13 revisions)
- Integrated silicon photonic structures (13 revisions)
- LAPACK/BLAS for FPGA (13 revisions)
- GUI-developement for an action-cam-based eye tracking device (13 revisions)
- Online Learning of User Features (1S) (13 revisions)
- Cycle-Accurate Event-Based Simulation of Snitch Core (13 revisions)
- Gomeza old project1 (13 revisions)
- MatPHY: An Open-Source Physical Layer Development Framework (13 revisions)
- Acceleration and Transprecision (13 revisions)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (13 revisions)
- On-Board Software for PULP on a Satellite (13 revisions)
- A Wireless Sensor Network for a Smart LED Lighting control (13 revisions)
- Neural Recording Interface and Signal Processing (13 revisions)
- ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G (13 revisions)
- ASIC implementation of an interpolation-based wideband massive MIMO detector (12 revisions)
- Peak-to-average power Reduction (12 revisions)
- Sensor Fusion for Rockfall Sensor Node (12 revisions)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (12 revisions)
- Deep neural networks for seizure detection (12 revisions)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (12 revisions)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) (12 revisions)
- Investigation of Quantization Strategies for Retentive Networks (1S) (12 revisions)
- Digital Audio High Level Synthesis for FPGAs (12 revisions - redirect page)
- Scattering Networks for Scene Labeling (12 revisions)
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device (12 revisions)
- Stand-Alone Edge Computing with GAP8 (12 revisions)
- BigPULP: Multicluster Synchronization Extensions (12 revisions)
- Event-Driven Computing (12 revisions)
- Bridging QuantLab with LPDNN (12 revisions)
- Investigation of Redox Processes in CBRAM (12 revisions)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device (12 revisions)
- SmartRing (12 revisions)
- Ultrasound Doppler system development (12 revisions)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (12 revisions)
- Event-Driven Convolutional Neural Network Modular Accelerator (12 revisions)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture (12 revisions)
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex (12 revisions)