Pages that link to "User:Tbenz"
From iis-projects
The following pages link to User:Tbenz:
View (previous 100 | next 100) (20 | 50 | 100 | 250 | 500)- High Performance SoCs (← links)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (← links)
- A Flexible Peripheral System for High-Performance Systems on Chip (M) (← links)
- A Snitch-based Compute Accelerator for HERO (M/1-2S) (← links)
- SSR combined with FREP in LLVM/Clang (M/1-3S) (← links)
- DaCe on Snitch (M/1-3S) (← links)
- Software-Defined Paging in the Snitch Cluster (2-3S) (← links)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G) (← links)
- IP-Based SoC Generation and Configuration (1-3S/B) (← links)
- RISC-V base ISA for ultra-low-area cores (2-3G) (← links)
- Quest for the smallest Turing-complete core (2-3G) (← links)
- Snitch meets iCE40 (1-2S/B) (← links)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (← links)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (← links)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (← links)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (← links)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (← links)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (← links)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S) (← links)
- Adding Linux Support to our DMA Engine (1-2S/B) (← links)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (← links)
- Enhancing our DMA Engine with Fault Tolerance (← links)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (← links)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (← links)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (← links)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) (← links)
- Towards Formal Verification of the iDMA Engine (1-3S/B) (← links)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (← links)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (← links)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (← links)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (← links)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (← links)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) (← links)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (← links)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (← links)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (← links)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (← links)
- Resource Partitioning of RPC DRAM (← links)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems (← links)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M) (← links)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (← links)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (← links)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (← links)
- Creating A Boundry Scan Generator (1-3S/B/2-3G) (← links)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) (← links)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B) (← links)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) (← links)
- Taping a Safer Silicon Implementation of Snitch (M/2-3S) (← links)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) (← links)
- Advanced Data Movers for Modern Neural Networks (← links)
- FPGA mapping of RPC DRAM (← links)