Latest revision as of 21:08, 2 August 2022

Thomas Benz

I am currently pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini. I completed my B.Sc. and M.Sc. in electrical engineering at ETH Zürich in 2018 and 2020, respectively.

My interests include:

• Memory systems for high-performance Systems
• Energy-efficient high-performance SoCs
• Energy estimation and energy-aware scheduling in embedded systems
• Design, fabrication, and testing of application-specific integrated circuits

Contact

• e-mail: tbenz@iis.ee.ethz.ch
• phone: +41 44 632 05 18
• office: ETZ J85

Projects

Available Projects

• Creating A Boundry Scan Generator (1-3S/B/2-3G)
• Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
• Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
• Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
• Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
• Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
• Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
• Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
• Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
• Resource Partitioning of RPC DRAM
• Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
• Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
• Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
• Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
• Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
• Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
• Towards Formal Verification of the iDMA Engine (1-3S/B)
• Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
• Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
• Enhancing our DMA Engine with Fault Tolerance
• IP-Based SoC Generation and Configuration (1-3S/B)

Projects In Progress

• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)

Completed Projects

• Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
• A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
• Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
• Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
• Adding Linux Support to our DMA Engine (1-2S/B)
• Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
• Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
• A Snitch-based Compute Accelerator for HERO (M/1-2S)

Reserved Projects