Category:Digital
From iis-projects
The printable version is no longer supported and may have rendering errors. Please update your browser bookmarks and please use the default browser print function instead.
Projects that are part of the Digital Circuits and Systems group
Active Projects
These are the projects that are currently active
- On-Device Federated Continual Learning on Nano-Drone Swarms
- ASR-Waveformer
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Fault-Tolerant Floating-Point Units (M)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Implementation of a Cache Reliability Mechanism (1S/M)
- Efficient collective communications in FlooNoC (1M)
- On-Board Software for PULP on a Satellite
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Zephyr RTOS on PULP
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Physical Implementation of ITA (2S)
- 3D Matrix Multiplication Unit for ITA (1S)
- Virtual Memory Ara
- New RVV 1.0 Vector Instructions for Ara
- Big Data Analytics Benchmarks for Ara
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Runtime partitioning of L1 memory in Mempool (M)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Radiation Testing of a PULP ASIC
- On - Device Continual Learning for Seizure Detection on GAP9
- Ternary Neural Networks for Face Recognition
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Efficient TNN compression
- Event-Driven Vision on an embedded platform
- ASIC Development of 5G-NR LDPC Decoder
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
Available Projects
We are still looking for students/partners to work on the following projects
- Extending the HERO SDK to support asynchronous offloading (M/1-3S)
- Structural Health Monitoring (SHM) System (1-2S/M)
- Spectrometry for Environmental Monitoring (1-2S/M)
- Waterflow Monitoring with Doppler Ultrasound (1S)
- Sound-Based Vehicle Classification and Counting (1-2S)
- Multi-Modal Environmental Sensing With GAP9 (1-2S)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- On-Device Learnable Embeddings for Acoustic Environments
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extreme-Edge Experience Replay for Keyword Spotting
- Low Precision Ara for ML
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- FPGA mapping of RPC DRAM
- GPT on the edge
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Modeling FlooNoC in GVSoC (S/M)
- Advanced Data Movers for Modern Neural Networks
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- EEG-based drowsiness detection
- In-ear EEG signal acquisition
- EEG earbud
- NeuroSoC RISC-V Component (M/1-2S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Realtime Gaze Tracking on Siracusa
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- System Emulation for AR and VR devices
- Learning at the Edge with Hardware-Aware Algorithms
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Advanced EEG glasses
- Softmax for Transformers (M/1-2S)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Modular Distributed Data Collection Platform
- Cycle-Accurate Event-Based Simulation of Snitch Core
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- Object Detection and Tracking on the Edge
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- BirdGuard
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Audio Visual Speech Separation and Recognition (1S/1M)
- Predict eye movement through brain activity
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Resource Partitioning of RPC DRAM
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- All the flavours of FFT on MemPool (1-2S/B)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Ultrasound image data recycler
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Extended Verification for Ara
- Design of combined Ultrasound and PPG systems
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- An Efficient Compiler Backend for Snitch (1S/B)
- PULP Freertos with LLVM
- Integration Of A Smart Vision System
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Event-based navigation on autonomous nano-drones
- Improving datarate and efficiency of ultra low power wearable ultrasound
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Battery indifferent wearable Ultrasound
- Wearable Ultrasound for Artery monitoring
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Improved Collision Avoidance for Nano-drones
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Ultra-wideband Concurrent Ranging
- Enhancing our DMA Engine with Fault Tolerance
- Fast Accelerator Context Switch for PULP
- Visualization of Neural Architecture Search Spaces
- Self Aware Epilepsy Monitoring
- Serverless Benchmarks on RISC-V (M)
- Non-blocking Algorithms in Real-Time Operating Systems
- EEG artifact detection with machine learning
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- EEG artifact detection for epilepsy monitoring
- Fast Simulation of Manycore Systems (1S)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Automatic unplugging detection for Ultrasound probes
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Huawei Research
- Securing Block Ciphers against SCA and SIFA
- RVfplib
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Short Range Radars For Biomedical Application
- Smart Patch For Heath Care And Rehabilitation
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Machine Learning on Ultrasound Images
- IP-Based SoC Generation and Configuration (1-3S/B)
- Efficient Search Design for Hyperdimensional Computing
- PREM Runtime Scheduling Policies
- IBM Research
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- BCI-controlled Drone
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Accurate deep learning inference using computational memory
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Visualizing Functional Microbubbles using Ultrasound Imaging
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Extending the RISCV backend of LLVM to support PULP Extensions
- Compiler Profiling and Optimizing
- PREM Intervals and Loop Tiling
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- PREM on PULP
- Edge Computing for Long-Term Wearable Biomedical Systems
- AMZ Driverless Competition Embedded Systems Projects
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Wireless Sensing With Long Range Comminication (LoRa)
- Indoor Smart Tracking of Hospital instrumentation
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- Physics is looking for PULP
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- An Industrial-grade Bluetooth LE Mesh Network Solution
- BLISS - Battery-Less Identification System for Security
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Zero Power Touch Sensor and Reciever For Body Communication
- Wake Up Radio For Energy Efficient Communication System and IC Design
- A Wireless Sensor Network for HPC monitoring
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Power Geolocalization And Indoor Localization
- Real-Time Implementation of Quantum State Identification using an FPGA
- Neural Networks Framwork for Embedded Plattforms
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Single-Bit-Synapse Spiking Neural System-on-Chip
- OpenRISC SoC for Sensor Applications
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- PVT Dynamic Adaptation in PULPv3
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Towards The Integration of E-skin into Prosthetic Devices
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Towards Self Sustainable UAVs
- Using Motion Sensors to Support Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Bateryless Heart Rate Monitoring
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Kinetic Energy Harvesting For Autonomous Smart Watches
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomous Smart Watches: Hardware and Software Desing
- A Wireless Sensor Network for a Smart LED Lighting control
- Compressed Sensing vs JPEG
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Real-Time Pedestrian Detection For Privacy Enhancement
- Thermal Control of Mobile Devices
- Android reliability governor
- Infrared Wake Up Radio
- Ambient RF Energy harvesting for Wireless Sensor Network
- Hardware Support for IDE in Multicore Environment
- Audio DAC Conversion Jitter Measurement System
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
Completed Projects
These are projects that were completed in the last few years
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
2012
- A Multiview Synthesis Core in 65 nm CMOS
- Real-time View Synthesis using Image Domain Warping
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
2011
Pages in category "Digital"
The following 200 pages are in this category, out of 617 total.
(previous page) (next page)N
O
- Object Detection and Tracking on the Edge
- On - Device Continual Learning for Seizure Detection on GAP9
- On-Board Software for PULP on a Satellite
- On-chip clock synthesizer design and porting
- On-Device Federated Continual Learning on Nano-Drone Swarms
- On-Device Learnable Embeddings for Acoustic Environments
- Online Learning of User Features (1S)
- OpenRISC SoC for Sensor Applications
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- OTDOA Positioning for LTE Cat-M
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- Outdoor Precision Object Tracking for Rockfall Experiments
P
- Pascal Hager
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- User:Paulin
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of ITA (2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Physics is looking for PULP
- Pirmin Vogel
- Power Optimization in Multipliers
- User:Prasadar
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
- Predict eye movement through brain activity
- Predictable Execution on GPU Caches
- PREM Intervals and Loop Tiling
- PREM on PULP
- PREM Runtime Scheduling Policies
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Probabilistic training algorithms for quantized neural networks
- Probing the limits of fake-quantised neural networks
- PULP Freertos with LLVM
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULP-Shield for Autonomous UAV
- PULPonFPGA: Hardware L2 Cache
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
- PULP’s CLIC extensions for fast interrupt handling
- Putting Together What Fits Together - GrÆStl
- PVT Dynamic Adaptation in PULPv3
R
- Radiation Testing of a PULP ASIC
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- RazorEDGE: An Evolved EDGE DBB ASIC
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time Implementation of Quantum State Identification using an FPGA
- Real-time Linux on RISC-V
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor
- Real-Time Optical Flow Using Neural Networks
- Real-Time Pedestrian Detection For Privacy Enhancement
- Real-Time Stereo to Multiview Conversion
- Real-time View Synthesis using Image Domain Warping
- Realtime Gaze Tracking on Siracusa
- Reconfigurability of SHA-3 candidates
- RedCap-5G for IOT application on prototype taped-out silicon
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Resource Partitioning of Caches
- Resource Partitioning of RPC DRAM
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Rethinking our Convolutional Network Accelerator Architecture
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Running Rust on PULP
- Runtime partitioning of L1 memory in Mempool (M)
- RVfplib
S
- Sandro Belfanti
- User:Sarjmandpour
- Satellite Internet of Things
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- User:Scheremo
- SCMI Support for Power Controller Subsystem
- Securing Block Ciphers against SCA and SIFA
- Self Aware Epilepsy Monitoring
- Self-Learning Drones based on Neural Networks
- Sensor Fusion for Rockfall Sensor Node
- Serverless Benchmarks on RISC-V (M)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Shared Correlation Accelerator for an RF SoC
- Short Range Radars For Biomedical Application
- Signal to Noise Ratio Estimation for 3G standards
- Single-Bit-Synapse Spiking Neural System-on-Chip
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Smart Agriculture System (1-2S)
- Smart e-glasses for concealed recording of EEG signals
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Smart Meters
- Smart Patch For Heath Care And Rehabilitation
- Smart Virtual Memory Sharing
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- SmartRing
- Softmax for Transformers (M/1-2S)
- Sound-Based Vehicle Classification and Counting (1-2S)
- Spatio-Temporal Video Filtering
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Spectrometry for Environmental Monitoring (1-2S/M)
- Spiking Neural Network for Autonomous Navigation
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- User:Sriedel
- Standard Cell Compatible Memory Array Design
- State-Saving @ NXP
- Stefan Lippuner
- Stefan Mach
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Streaming Integer Extensions for Snitch (M/1-2S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Structural Health Monitoring (SHM) System (1-2S/M)
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Subject specific embeddings for transfer learning in brain-computer interfaces
- User:Susman
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- System Emulation for AR and VR devices
T
- Taimir Aguacil
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- TCNs vs. LSTMs for Embedded Platforms
- Ternary Neural Networks for Face Recognition
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Testbed Design for Self-sustainable IoT Sensors
- Thermal Control of Mobile Devices
- User:Thoriri
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Time Gain Compensation for Ultrasound Imaging
- Time Synchronization for 3G Mobile Communications
- Timing Channel Mitigations for RISC-V Cores
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Toward Superposition of Brain-Computer Interface Models
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards Autonomous Navigation for Nano-Blimps
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards global Brain-Computer Interfaces
- Towards Self Sustainable UAVs
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Towards The Integration of E-skin into Prosthetic Devices
- Trace Debugger for custom RISC-V Core
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Equalization for Cellular IoT
U
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Ultra low power wearable ultrasound probe
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Ultra-low power processor design
- Ultra-wideband Concurrent Ranging
- Ultrafast Medical Ultrasound imaging on a GPU
- Ultrasound based hand gesture recognition
- Ultrasound Doppler system development
- Ultrasound High Speed Microbubble Tracking
- Ultrasound image data recycler
- Ultrasound Low power WiFi with IMX7
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- Ultrasound signal processing acceleration with CUDA
- Ultrasound-EMG combined hand gesture recognition
- Using Motion Sensors to Support Indoor Localization
V
- Variability Tolerant Ultra Low Power Cluster
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Vector Processor for In-Memory Computing
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- Virtual Memory Ara
- Visualization of Neural Architecture Search Spaces
- Visualizing Functional Microbubbles using Ultrasound Imaging
- User:Vladn
- VLSI Implementation of a 5G Ciphering Accelerator
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- VLSI Implementation Polar Decoder using High Level Synthesis
W
- Wake Up Radio For Energy Efficient Communication System and IC Design
- Watchdog Timer for PULP
- Waterflow Monitoring with Doppler Ultrasound (1S)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Wearable Ultrasound for Artery monitoring
- Wearables in Fashion
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
- Wireless Communication Systems for the IoT
- Wireless EEG Acquisition and Processing