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- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Efficient SoCs
- Engineering For Kids
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Evaluating An Ultra low Power Vision Node
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Event-based navigation on autonomous nano-drones
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring NAS spaces with C-BRED
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- FFT-based Convolutional Network Accelerator
- FFT HDL Code Generator for Multi-Antenna mmWave Communication
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
- FPGA mapping of RPC DRAM
- Fast Accelerator Context Switch for PULP
- Fast Simulation of Manycore Systems (1S)
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fault-Tolerant Floating-Point Units (M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Finite Element Simulations of Transistors for Quantum Computing
- Finite element modeling of electrochemical random access memory
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Flexible Front-End Circuit for Biomedical Data Acquisition
- Floating-Point Divide & Square Root Unit for Transprecision
- Forward error-correction ASIC using GRAND
- Freedom from Interference in Heterogeneous COTS SoCs
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- GPT on the edge
- GRAND Hardware Implementation
- GSM Voice Capacity Evolution - VAMOS
- GUI-developement for an action-cam-based eye tracking device
- Glitches Reduce Listening Time of Your iPod
- Gomeza old project1
- Gomeza old project2
- Gomeza old project3
- Gomeza old project4
- Gomeza old project5
- Graph neural networks for epileptic seizure detection
- HERO: TLB Invalidation
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Hardware Accelerated Derivative Pricing
- Hardware Accelerator Integration into Embedded Linux
- Hardware Accelerator for Model Predictive Controller
- Hardware Constrained Neural Architechture Search
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Hardware Support for IDE in Multicore Environment
- Herschmi
- High-Resolution, Calibrated Folding ADCs
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- High-speed Scene Labeling on FPGA
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- High Performance Cellular Receivers in Very Advanced CMOS
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hypervisor Extension for Ariane (M)
- IBM A2O Core
- IBM Research–Zurich
- IP-Based SoC Generation and Configuration (1-3S)
- IP-Based SoC Generation and Configuration (1-3S/B)
- ISA extensions in the Snitch Processor for Signal Processing (1M)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Image Sensor Interface and Pre-processing
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Implementation of a 2-D model for Li-ion batteries
- Implementation of a Cache Reliability Mechanism (1S/M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementation of an Accelerator for Retentive Networks (1-2S)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing A Low-Power Sensor Node Network
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Implementing Hibernation on the ARM Cortex M0
- Improved Collision Avoidance for Nano-drones
- Improved Reacquisition for the 5G Cellular IoT
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Improving Resiliency of Hyperdimensional Computing
- Improving Scene Labeling with Hyperspectral Data
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Improving datarate and efficiency of ultra low power wearable ultrasound
- Improving our Smart Camera System
- In-ear EEG signal acquisition
- Indoor Positioning with Bluetooth
- Indoor Smart Tracking of Hospital instrumentation
- Inductive Charging Circuit for Implantable Devices
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Infrared Wake Up Radio
- Integrated silicon photonic structures
- Integrated silicon photonic structures-Lumiphase
- Integrating Hardware Accelerators into Snitch
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Integration Of A Smart Vision System
- Intelligent Disaster Early-Warning System (1-2S/M)
- Intelligent Power Management Unit (iPMU)
- Interference Cancellation for EC-GSM-IoT
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Interference Cancellation for the cellular Internet of Things
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Investigation of the source starvation effect in III-V MOSFET
- IoT Turbo Decoder
- Jammer-Resilient Synchronization for Wireless Communications
- Jammer Mitigation Meets Machine Learning
- Kinetic Energy Harvesting For Autonomous Smart Watches
- Knowledge Distillation for Embedded Machine Learning
- LAPACK/BLAS for FPGA
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
- LTE IoT Network Synchronization
- Learning Image Compression with Convolutional Networks
- Learning Image Decompression with Convolutional Networks
- Learning at the Edge with Hardware-Aware Algorithms
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Libria
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - CNN-Based-Image-Reconstruction
- LightProbe - Design of a High-Speed Optical Link
- LightProbe - Frontend Firmware and Control Side Channel
- LightProbe - Implementation of compressed-sensing algorithms
- LightProbe - Thermal-Power aware on-head Beamforming
- LightProbe - Ultracompact Power Supply PCB
- LightProbe - WIFI extension (PCB)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
- Linux Driver for fine-grain and low overhead access to on-chip performance counters
- Low-Complexity MIMO Detection
- Low-Dropout Regulators for Magnetic Resonance Imaging
- Low-Power Time Synchronization for IoT Applications
- Low-Resolution 5G Beamforming Codebook Design
- Low-power Clock Generation Solutions for 65nm Technology
- Low-power Temperature-insensitive Timer
- Low-power chip-to-chip communication network
- Low-power time synchronization for IoT applications
- Low Latency Brain-Machine Interfaces
- Low Power Embedded Systems and Wireless Sensors Networks
- Low Power Geolocalization And Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Precision Ara for ML
- Low Resolution Neural Networks
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Machine Learning on Ultrasound Images
- Main Page
- Make Cellular Internet of Things Receivers Smart
- Manycore System on FPGA (M/S/G)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Matheus Cavalcante
- Mattia
- MemPool on HERO
- MemPool on HERO (1S)
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Minimal Cost RISC-V core
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- Modeling FlooNoC in GVSoC (S/M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Modular Distributed Data Collection Platform
- Modular Frequency-Modulation (FM) Music Synthesizer
- Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- Moritz Schneider
- Multi-Band Receiver Design for LTE Mobile Communication
- Multi-Modal Environmental Sensing With GAP9 (1-2S)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
- NAND Flash Open Research Platform
- NORX - an AEAD algorithm for the CAESAR competition
- NVDLA meets PULP
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Near-Memory Training of Neural Networks
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- Network-off-Chip (M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Neural Processing
- Neural Recording Interface and Signal Processing
- Neural Recording Interface and Spike Sorting Algorithm
- NeuroSoC RISC-V Component (M/1-2S)
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
- NextGenChannelDec
- Next Generation Synchronization Signals
- Non-binary LDPC Decoder for Deep-Space Optical Communications
- Non-blocking Algorithms in Real-Time Operating Systems
- Novel Metastability Mitigation Technique
- Novel Methods for Jammer Mitigation
- Object Detection and Tracking on the Edge
- On-Board Software for PULP on a Satellite
- On-Device Federated Continual Learning on Nano-Drone Swarms
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
- On-chip clock synthesizer design and porting
- On - Device Continual Learning for Seizure Detection on GAP9
- Online Learning of User Features (1S)
- OpenRISC SoC for Sensor Applications
- Open Power-On Chip Controller Study and Integration
- Optimal System Duty Cycling
- Optimal System Duty Cycling for a Mobile Health Platform
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Outdoor Precision Object Tracking for Rockfall Experiments
- PREM Intervals and Loop Tiling
- PREM Runtime Scheduling Policies
- PREM on PULP
- PULP-Shield for Autonomous UAV
- PULP Freertos with LLVM
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULPonFPGA: Hardware L2 Cache
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
- PULP’s CLIC extensions for fast interrupt handling
- PVT Dynamic Adaptation in PULPv3
- Palm size chip NMR
- Passive Radar for UAV Detection using Machine Learning
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- Peak-to-average power Reduction
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Phase-change memory devices for emerging computing paradigms
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of ITA (2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
- Positioning for the cellular Internet of Things
- Power Optimization in Multipliers
- Power Saver Mode for Cellular Internet of Things Receivers
- Practical Reconfigurable Intelligent Surfaces (RIS)
- Prasadar
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
- Precise Ultra-low-power Timer
- Predict eye movement through brain activity
- Predictable Execution on GPU Caches
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Probabilistic training algorithms for quantized neural networks
- Probing the limits of fake-quantised neural networks
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
- Pulse Oximetry Fachpraktikum
- Putting Together What Fits Together - GrÆStl
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Quantum Transport Modeling of Interband Cascade Lasers (ICL)
- Quantum transport in 2D heterostructures
- RISC-V base ISA for ultra-low-area cores (2-3G)
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- RVfplib
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time Implementation of Quantum State Identification using an FPGA
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor
- Real-Time Optical Flow Using Neural Networks
- Real-Time Pedestrian Detection For Privacy Enhancement
- Real-time Linux on RISC-V
- Real-time View Synthesis using Image Domain Warping
- Real-time eye movement analysis on a tablet computer
- Realtime Gaze Tracking on Siracusa
- Receiver design for the DigRF 4G high speed serial link
- Reconfigurability of SHA-3 candidates
- Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication
- RedCap-5G for IOT application on prototype taped-out silicon
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Resource Partitioning of Caches
- Resource Partitioning of RPC DRAM
- Rethinking our Convolutional Network Accelerator Architecture
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Running Rust on PULP
- Runtime partitioning of L1 memory in Mempool (M)
- SCMI Support for Power Controller Subsystem
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- SSR combined with FREP in LLVM/Clang
- Satellite Internet of Things
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Scattering Networks for Scene Labeling
- Securing Block Ciphers against SCA and SIFA
- Self-Learning Drones based on Neural Networks
- Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
- Self Aware Epilepsy Monitoring
- Semi-Custom Digital VLSI for Processing-in-Memory
- Sensor Fusion for Rockfall Sensor Node
- Serverless Benchmarks on RISC-V (M)
- Shared Correlation Accelerator for an RF SoC
- Short Range Radars For Biomedical Application
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
- Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
- Signal to Noise Ratio Estimation for 3G standards
- Simulation of 2D artificial cilia metasurface in COMSOL
- Simulation of Li-ion batteries and comparison with experimental data
- Simulation of Negative Capacitance Ferroelectric Transistor
- Single-Bit-Synapse Spiking Neural System-on-Chip
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Skin coupling media characterization for fitnesstracker applications (1 B/S)
- SmartRing
- Smart Agriculture System (1-2S)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S)
- Smart Meters
- Smart Patch For Heath Care And Rehabilitation
- Smart Virtual Memory Sharing
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Smart e-glasses for concealed recording of EEG signals
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- Softmax for Transformers (M/1-2S)
- Software-Defined Paging in the Snitch Cluster (2-3S)
- Sound-Based Vehicle Classification and Counting (1-2S)
- Spatio-Temporal Video Filtering
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Spectrometry for Environmental Monitoring (1-2S/M)
- Spiking Neural Network for Autonomous Navigation
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Stand-Alone Edge Computing with GAP8
- Standard Cell Compatible Memory Array Design
- State-Saving @ NXP
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Streaming Layer Normalization in ITA (M/1-2S)
- Structural Health Monitoring (SHM) System (1-2S/M)
- Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub-Noise Floor Channel Tracking
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Subject specific embeddings for transfer learning in brain-computer interfaces
- Successive Approximation Register (SAR) ADC
- Successive Interference Cancellation for 3G Downlink
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Switched Capacitor Based Bandgap-Reference
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- System Emulation for AR and VR devices
- TCNs vs. LSTMs for Embedded Platforms
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- Tbenz
- Telecommunications
- Template
- Ternary Neural Networks for Face Recognition
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Test page
- Test project
- Testbed Design for Self-sustainable IoT Sensors
- Thermal Control of Mobile Devices
- Through Wall Radar Imaging using Machine Learning
- Time Gain Compensation for Ultrasound Imaging
- Time Synchronization for 3G Mobile Communications
- Timing Channel Mitigations for RISC-V Cores
- Toward Superposition of Brain-Computer Interface Models
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Towards Autonomous Navigation for Nano-Blimps
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards The Integration of E-skin into Prosthetic Devices
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards global Brain-Computer Interfaces
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Trace Debugger for custom RISC-V Core
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Decoder Design for High Code Rates
- Turbo Equalization for Cellular IoT
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Ultra-low power sampling front-end for acquisition of physiological signals
- Ultra-low power transceiver for implantable devices
- Ultra-wideband Concurrent Ranging
- Ultra Low-Power Oscillator
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Ultra low power wearable ultrasound probe
- Ultrafast Medical Ultrasound imaging on a GPU
- Ultrasound-EMG combined hand gesture recognition
- Ultrasound Doppler system development
- Ultrasound High Speed Microbubble Tracking
- Ultrasound Low power WiFi with IMX7
- Ultrasound based hand gesture recognition
- Ultrasound image data recycler
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- Ultrasound signal processing acceleration with CUDA
- Unconventional phase change memory device concepts for in-memory and neuromorphic computin
- Using Motion Sensors to Support Indoor Localization
- VLSI Design of an Asynchronous LDPC Decoder
- VLSI Implementation Polar Decoder using High Level Synthesis
- VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM
- Variability Tolerant Ultra Low Power Cluster
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- Vector Processor for In-Memory Computing
- Versatile HW SW Digital PHY for inter chip communication
- Virtual Memory Ara
- Visualization of Neural Architecture Search Spaces
- Visualizing Functional Microbubbles using Ultrasound Imaging
- Wake Up Radio For Energy Efficient Communication System and IC Design
- Watchdog Timer for PULP
- Waterflow Monitoring with Doppler Ultrasound (1S)
- Weak-strong massive MIMO communication with low-resolution ADCs
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Wearable Ultrasound for Artery monitoring
- Wearables for Sports and Life Enhancement
- Wearables in Fashion
- Weekly Reports
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
- Wireless Biomedical Signal Acquisition Device
- Wireless EEG Acquisition and Processing
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- Wireless Sensing With Long Range Comminication (LoRa)
- Writing a Hero runtime for EPAC (1-3S/B)
- XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
- Zephyr RTOS on PULP
- Zero Power Touch Sensor and Reciever For Body Communication
