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  • Main Page
    * [[Noise Figure Measurement for Cryogenic System]] * [[A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities]]
    5 KB (537 words) - 15:22, 23 February 2024
  • Ultra-low power processor design
    ...er, there is a lot of functionality which will never be used in the target system and it is therefore not necessary to maintain all this functionality. Remov ...Adding User I/O to the Processor''': If the processor is not embedded in a system, it is like a blackbox which computes something and stores the result in th
    10 KB (1,669 words) - 19:01, 30 January 2014
  • Coding Guidelines
    ...ilog code, is the '''emacs''' editor, as it has a really advanced VHDL and System Verilog mode. Because of this, you should get comfortable with the idea of
    841 bytes (137 words) - 14:42, 16 January 2014
  • Variability Tolerant Ultra Low Power Cluster
    dynamically modify the timing constrains aiming to tolerate at system level reliable computing system in nano-meter technology operating in
    3 KB (409 words) - 10:52, 27 March 2014
  • Template
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    4 KB (397 words) - 15:44, 14 February 2023
  • Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
    ...-process this data in order to compact it for the transport to the imaging system. A special challenge pose the high-speed output pin drivers. In case of int ...o reduce the incidental data rates between the sensor head and the backend system, and second, new beamforming strategies to minimize the computational burde
    4 KB (614 words) - 20:10, 17 February 2015
  • Multiuser Equalization and Detection for 3GPP TD-SCDMA
    TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD na
    1 KB (206 words) - 14:07, 9 February 2015
  • Channel Estimation for 3GPP TD-SCDMA
    TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD na
    1 KB (160 words) - 11:17, 23 September 2016
  • Flexible Electronic Systems and Embedded Epidermal Devices
    ...le or strechable materials to form wearable and conformable devices. These system are often composed of various flexible, bendable but also small ridgid comp
    4 KB (444 words) - 12:43, 23 July 2023
  • Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
    ...ure in such a way that later studies will allow '''ML-based control of the system'''. ...architecture is to be designed in such a way that ML-based control of the system is possible.
    6 KB (741 words) - 18:14, 21 July 2023
  • Synchronization and Power Control Concepts for 3GPP TD-SCDMA
    TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD na
    1 KB (158 words) - 11:17, 23 September 2016
  • Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
    TD-HSPA is a 3GPP standard that combines an advanced TDMA/TDD system with an adap- MLSD computation for a system with such dimensions practically impossible given the current
    5 KB (684 words) - 10:43, 6 November 2017
  • Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
    ...ject, you will assess the effect of carrier aggregation in an LTE-Advanced system. You will start by implementing a MATLAB framework to simulate the LTE-Adva
    3 KB (405 words) - 16:13, 29 December 2016
  • Digital Transmitter for Mobile Communications
    ...he chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emer ...ring the VLSI III lecture. For an implementation on an FPGA, the resulting system (combined with the existing analog transceiver) can be tested using a proto
    3 KB (382 words) - 20:00, 26 September 2017
  • ASIC Implementation of High-Throughput Next Generation Turbo Decoders
    Forward error correction is a crucial part in any communication system, since it enables reliable transmission over unreliable channels. In mobile
    3 KB (508 words) - 11:12, 14 April 2016
  • Low-power chip-to-chip communication network
    ...ill form the standard chip to chip communication standard for the [[PULP]] system.
    3 KB (492 words) - 12:34, 7 November 2017
  • Accelerators for object detection and tracking
    applications for this system is in real-time video applications, expecially system, improving the energy efficiency of the system. The accelerator will
    3 KB (407 words) - 10:57, 5 November 2019
  • Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
    The IIS 2G testbed has no operating system (OS) running on [4] FreeRTOS - Market leading RTOS (Real Time Operating System) for embedded systems
    3 KB (421 words) - 10:40, 6 November 2017
  • Open Source Baseband Firmware for 2G Cellular Networks
    ...tp://www.freertos.org/ FreeRTOS - Market leading RTOS (Real Time Operating System) for embedded systems with Internet of Things extensions], June 2015.
    2 KB (273 words) - 11:30, 24 February 2017
  • CPS Software-Configurable State-Machine
    ...data over a wireless link. Some of these system even include an actuation system, which reacts depending on the captured data. ...nnected and operate and act collaboratively it is called a 'cyper-physical system' (CPS).
    3 KB (418 words) - 11:24, 10 November 2017
  • Design and Implementation of an Approximate Floating Point Unit
    ...tion of the FPUs and therefore reduce the overall power consumption of the system. Sharing FPUs allows to employ several different units, which can be either ...nd is a promising approach to further improve the energy efficiency of the system. One way to approximate FP-operations is to use Newton's method to compute
    3 KB (377 words) - 10:58, 21 February 2018
  • Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
    ...egory:Qcrypt|QCRYPT]] was the development of the 100 Gbit/s link encryptor system with a variety of optical interfaces on the plain-text side and a 100 Gbit ...main focus lay on the development of a second version of the PCB for this system. The layer stackup was modified to enhance the high-frequency quality of th
    2 KB (359 words) - 20:06, 17 February 2015
  • High-Throughput Authenticated Encryption Architectures based on Block Ciphers
    ''2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)'', Santa Cruz, California, USA, 7-10 Oct 2012
    3 KB (392 words) - 12:25, 26 March 2015
  • Real-time View Synthesis using Image Domain Warping
    ...erent mobile platforms, most productions are captured with one acquisition system at fixed parameters. Examples for content adaption algorithms are content-a ...ons and VLSI Implementations", ''VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, volume 418 of IFIP Advances in Information and Communicatio
    4 KB (520 words) - 16:04, 13 May 2015
  • Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
    ...IC/FPGA system which implements the first three steps of this process. Our system is able to extract SKB features from one 720p video stream in real time (30
    3 KB (487 words) - 15:57, 13 May 2015
  • Pirmin Vogel
    ...ing and embedded heterogeneous systems on a chip with a focus on operating system, driver, runtime and programming model support for efficient and transparen
    1 KB (193 words) - 15:39, 3 March 2020
  • Image Sensor Interface and Pre-processing
    ...the image is being acquired and forward this information to a larger host system for further processing. ...algorithm steps directly ion hardware and interface with the host computer system.
    3 KB (357 words) - 18:53, 6 December 2014
  • High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
    ...bits. Such data converters are intended to be embedded in a mostly digital system, and this legitimates the adoption of ultra-scaled CMOS technologies from w
    2 KB (277 words) - 17:28, 29 January 2014
  • Wireless Biomedical Signal Acquisition Device
    Although the wireless and battery-powered nature of this system reduces the impact of mains interference, its amplitude might nonetheless b ...ed by an off-the-shelf mobile phone battery which is sufficient to run the system for several hours - the battery life-time is mainly limited by the Bluetoot
    2 KB (280 words) - 10:54, 10 March 2015
  • Benjamin Weber
    his PhD thesis entitled "An Evolved EDGE System on Chip for the Cellular
    894 bytes (115 words) - 17:17, 30 November 2021
  • Digitally-Controlled Analog Subtractive Sound Synthesis
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (597 words) - 12:56, 4 December 2021
  • MatPHY: An Open-Source Physical Layer Development Framework
    ...upper layers of the OsmocomBB GSM protocol stack. The functionality of the system is verified with a testbed comprising a base station and a receiver board w
    3 KB (360 words) - 14:14, 27 May 2015
  • Evolved EDGE Physical Layer Incremental Redundancy Architecture
    ...ssor and the unit where RLC blocks are processed for IR is attached to the system processor. The decoding of the RLC blocks takes place on a PHY Digital Sign
    3 KB (397 words) - 14:12, 27 May 2015
  • A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
    ...ons such as those in the time-duplexing high speed packet access (TD-HSPA) system.
    2 KB (266 words) - 10:43, 9 February 2015
  • IcySoC
    ...terms of parallelism, performances and robustness. One has to revisit the system design in terms of usage of hardware accelerators, heterogeneous or homogen
    4 KB (568 words) - 12:48, 9 February 2015
  • Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
    ...communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect rates.]] ...Q operation that is critical for the average throughput performance of the system.
    2 KB (343 words) - 13:56, 9 February 2015
  • Data Mapping for Unreliable Memories
    ...channel with unreliable memory. Bottom: Bit-error rate performance of the system assuming convolutional coding for different data representations.]] ...ion-specific cost functions) substantially increases the robustness of the system to unreliable memory operation, compared to the data representations most c
    3 KB (352 words) - 13:56, 9 February 2015
  • Design and Implementation of ultra low power vision system
    ...t role in this type of devices and in general in battery-operated embedded system. : Interest in Computer Architectures at system level
    2 KB (342 words) - 16:46, 11 February 2015
  • A Wireless Sensor Network for a Smart LED Lighting control
    ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors, intelligence and actuator interconnected ...e power consumption reduction, reliability, functionality and optimize the system.
    3 KB (487 words) - 12:02, 27 January 2016
  • Ultra Low Power Wake Up Radio for Wireless Sensor Network
    ...a low power radio wake up receiver can reduce the power consumption of the system while still keeping its response time low. Another role of the wake-up radi ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe
    4 KB (613 words) - 19:54, 9 February 2015
  • Infrared Wake Up Radio
    ...ices while still keeping its wake up time low. Another role of the wake-up system is that based on "intelligence" to select a specific device which has to be ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe
    3 KB (515 words) - 19:55, 9 February 2015
  • Accelerator for Boosted Binary Features
    [[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]] ...rrently used in the video analysis part of a more complex video processing system which performs [[Real-Time_Stereo_to_Multiview_Conversion|automatic multiv
    3 KB (373 words) - 11:51, 19 August 2017
  • Audio DAC Conversion Jitter Measurement System
    ...o experienced students) comprises the implementation of such a measurement system. Possible approaches include a cross-correlating spectrum analyzer or the u
    2 KB (251 words) - 20:06, 17 February 2015
  • Improving Scene Labeling with Hyperspectral Data
    ...uld be to evaluate and integrate this camera into a working scene labeling system [[http://dl.acm.org/citation.cfm?id=2744788 paper]] and would be very diver * create a system from the individual parts (build a case/box mounting the cameras, dev board
    6 KB (941 words) - 11:29, 5 February 2016
  • Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
    ...e with basic engineering tools (web search, basic usage of Linux operating system, compilers…) and of work independence
    5 KB (784 words) - 14:50, 30 November 2016
  • Android Software Design
    [[Category:Biomedical System on Chips]]
    2 KB (278 words) - 16:57, 12 July 2022
  • FPGA-Based Digital Frontend for 3G Receivers
    [[Category:System Design]]
    2 KB (348 words) - 20:01, 26 September 2017
  • ASIC
    * Designing the system architecture * Defining the circuit using hardware description languages (HDL) such as (System Verilog or VHDL) for [[:Category:Digital|digital projects]], and schematic
    1 KB (165 words) - 19:52, 10 February 2015
  • FPGA
    * Understand the different available peripherals on your system board * Run your system on the development board and collect the results.
    1,020 bytes (132 words) - 19:50, 10 February 2015
  • Hardware Accelerator Integration into Embedded Linux
    ...will be able to control the accelerator from the command line of the Linux system. :[3] [http://www.arm.com/products/system-ip/amba/amba-open-specifications.php ARM AMBA Specification]
    2 KB (236 words) - 09:46, 12 October 2017
  • PULP
    [[File:pulp_block_diag.png|thumb|400px|Basic block diagram of a PULP system.]] * [http://asic.ethz.ch/2020/Thestral.html Thestral] Snitch based system with 1x cluster (8x compute + 1x DMA core) and 1x governor core. Designed t
    10 KB (1,563 words) - 10:09, 19 August 2022
  • Indoor Positioning with Bluetooth
    [[Category:System Design]]
    3 KB (449 words) - 12:12, 4 November 2019
  • OpenRISC SoC for Sensor Applications
    ...r OpenRISC core with the following capabilities so that a standalone small system can be designed that can directly interface with various sensors and can co : For low power operations, we would like to shutdown most of the system including the processor, and wait until there is an event that requires the
    4 KB (667 words) - 15:23, 23 December 2016
  • Hardware Accelerator for Model Predictive Controller
    In recent years reseach works shows that thermal evolution of a multicore system can be effectively modelled with linear state-space representation enabling ...will then be part of a larger system and be part of the thermal management system. In this project the goal is to implement a novel MPC algorithm in hardware
    3 KB (456 words) - 08:35, 20 January 2021
  • 4th Generation Synchronization
    ..., R.N. Challa, and H.A. Mahmoud. Frequency Scan Method for Determining the System Center Frequency for LTE TDD, September 6 2013. WO Patent App. PCT/US2013/0
    2 KB (350 words) - 17:56, 14 April 2016
  • Analog
    ====[[Biomedical System on Chips|Biomedical System on Chips]]==== ...f wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless transmis
    3 KB (369 words) - 18:11, 1 March 2023
  • Ambient RF Energy harvesting for Wireless Sensor Network
    ...method by implementing our system.. Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe : Interest in Computer Architectures at system level
    3 KB (378 words) - 19:56, 9 February 2015
  • Android reliability governor
    Reliability (R(t)) is the probability that a given system does not fail before time t. It is becoming a major concern in modern multi ...bile]] [[Category:Temperature]] [[Category:Dynamic Management]] [[Category:System Design]]
    4 KB (573 words) - 17:24, 9 February 2015
  • Thermal Control of Mobile Devices
    ...s an heterogeneous thermal profile which is highly dependent on the actual system usage. As a matter of fact today and future mobile devices are thermally li ...thermal model can be directly identified from the target device by mean of system identification and self-calibrating routines.
    3 KB (452 words) - 11:03, 10 February 2015
  • Real-Time Pedestrian Detection For Privacy Enhancement
    [[Category:System Design]]
    3 KB (408 words) - 13:17, 5 February 2016
  • Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
    ...stem was proposed alongside the release-8 of the Long Term Evolution (LTE) system for the fourth generation (4G) of mobile communication. While the air inter ...tionality of a standard-compliant physical layer of a mobile communication system. Possibly, the student can also investigate and analyze an interesting perf
    1 KB (159 words) - 11:16, 23 September 2016
  • Digital Transmitter for Cellular IoT
    [1] ''Cellular system support for ultra-low complexity and low throughput Internet of Things (CIo
    3 KB (384 words) - 16:41, 17 July 2016
  • Design of an LTE Module for the Internet of Things
    ...E transceiver [2] will be used. You will start with your design by doing a system analysis on the required building blocks (Synchronization, FFT, Symbol dete [[Category:System Design]]
    3 KB (335 words) - 14:20, 4 November 2019
  • Active-Set QP Solver on FPGA
    : Matlab, C++, VHDL or System Verilog
    2 KB (351 words) - 13:09, 2 November 2015
  • LAPACK/BLAS for FPGA
    : Matlab, C++, VHDL or System Verilog
    2 KB (328 words) - 12:38, 1 June 2017
  • Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
    ...er, a careful design of each regulator is extremely important. A PCB-based system, containing of-the-shelf converter chips where available, and discrete-comp [[Category:System Design]]
    3 KB (438 words) - 18:06, 3 February 2015
  • Gomeza old project1
    ...be mapped to both cores. This results in a lower active time, allowing the system to enter a low-power sleep mode, and reduce the total energy consumption.
    3 KB (431 words) - 18:04, 28 January 2017
  • Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
    [[Category:System Design]]
    4 KB (589 words) - 10:14, 3 August 2018
  • Energy Neutral Multi Sensors Wearable Device
    : Interest in Computer Architectures at system level : Wearable system I (prof. Troester lectures)
    2 KB (319 words) - 16:24, 30 October 2020
  • Real-Time Stereo to Multiview Conversion
    [[File:mvSystem.jpg|thumb|600px|a) Multiview system in action and b) closeup of the hardware prototype.]] Ideally, a 3D display system should not require the users to
    3 KB (509 words) - 09:09, 23 October 2015
  • Digital
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    7 KB (811 words) - 15:21, 23 February 2024
  • Modeling FlooNoC in GVSoC (S/M)
    ...event-driven simulator designed for simulating IoT processors and complex system-on-chips (SoCs). It plays a crucial role in enabling agile design space exp * Experience with System Verilog is recommended but not strictly necessary
    4 KB (520 words) - 15:15, 4 December 2023
  • Time and Frequency Synchronization in LTE Cat-0 Devices
    ...k, Nitin Mangalvedhe, Amitava Ghosh, and Benny Vejlgaard. Narrowband LTE-M system for M2M communication. 2014.
    4 KB (561 words) - 10:43, 6 November 2017
  • Baseband Meets CPU
    is indispensable. Ideally, System-on-a-Chip (SoC) or System-in-a-Package (SiP) modems such as [1] are
    7 KB (1,105 words) - 20:02, 26 September 2017
  • Real-Time Optical Flow Using Neural Networks
    [[Category:Digital]] [[Category:System Design]]
    5 KB (707 words) - 11:22, 5 February 2016
  • An FPGA-Based Testbed for 3G Mobile Communications Receivers
    [[Category:System Design]]
    1 KB (169 words) - 16:42, 9 December 2015
  • PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
    ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...L1 scratchpad memory, and the shared main memory to optimally exploit the system's memory hierarchy and to achieve high performance.
    5 KB (716 words) - 13:43, 29 November 2019
  • DigitalUltrasoundHead
    ...e piezoelectric elements in the transducer head are connected to a backend system over a large cable containing hundreds of small coaxial cables. This is sho In order to do so, the entire analog frontend of the ultrasound system needs to be integrated into the transducer head and a digital link needs to
    3 KB (378 words) - 11:52, 10 January 2017
  • High-speed Scene Labeling on FPGA
    ...tation of an entire scene labeling network. In order to keep the developed system flexible in terms of the convolutional neural network that is applied as we ...rt software blocks to programmable logic and design an entire hetergeneous system using with software, FPGA fabric and hardwired interfaces.
    8 KB (1,197 words) - 18:18, 29 August 2016
  • Time Synchronization for 3G Mobile Communications
    [[Category:System Design]]
    3 KB (420 words) - 11:22, 14 April 2016
  • PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
    ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e This system design project requires work to be done at several layers of abstraction. M
    4 KB (585 words) - 17:57, 7 November 2017
  • PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
    ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e : VHDL/System Verilog, C
    4 KB (554 words) - 17:57, 7 November 2017
  • Autonomous Sensing For Trains In The IoT Era
    ...ment of novel zero-power sensors that act as a trigger for the rest of the system when an important event is detected and consume zero-power between two dete ...classification accuracy and energy efficiency and to further optimize the system.
    6 KB (774 words) - 08:36, 23 November 2022
  • Switched Capacitor Based Bandgap-Reference
    [[Category:System Design]] [[Category:System Design]]
    4 KB (471 words) - 11:13, 3 May 2018
  • Compressed Sensing for Wireless Biosignal Monitoring
    ...we have implemented and fabricated an 8-channel biosignal acquisition SoC (System-on-Chip) [http://asic.ee.ethz.ch/2014/CerebroV4.0_Homer.html] including ana
    2 KB (353 words) - 08:35, 20 January 2021
  • Scattering Networks for Scene Labeling
    [[Category:System Design]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Luk [[Category:Digital]] [[Category:System Design]]
    4 KB (563 words) - 11:29, 5 February 2016
  • Autonomous Smart Watches: Hardware and Software Desing
    ...classification accuracy and energy efficiency and to further optimize the system. : Interest in Computer Architectures at system level
    3 KB (448 words) - 11:59, 28 July 2015
  • A Wearable System for long term monitoring of human physiological parameters with E skin sensors
    : Interest in Computer Architectures at system level ...arning would be beneficial (i.e. semester project or exam done in Wearable system I prof. Troester)
    3 KB (380 words) - 11:59, 28 July 2015
  • Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
    [[Category:System Design]]
    4 KB (507 words) - 12:11, 16 February 2016
  • Low Power Neural Network For Multi Sensors Wearable Devices
    ...otal power spent for event detection, we propose an alternative, two-stage system architecture consisting of: 1. "wake-up sensing" (WUS) circuit, and 2. main [[Category:System Design]]
    7 KB (895 words) - 17:02, 28 July 2017
  • Improving our Smart Camera System
    ...hose in our prototype, and otherwise improve it by building a more compact system, adding communication capabilities to transmit suspicious cases to a remote [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]]
    8 KB (1,176 words) - 16:26, 30 October 2020
  • Eye movements
    ...by canceling self-induced motion blur. The VOR is driven by the vestibular system and induces short-latency eye movements in the opposite direction to the he
    2 KB (376 words) - 14:43, 29 July 2015
  • VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
    ...l-diversity streams have been introduced with the Evolved EDGE 2G cellular system [1], the recent EC-GSM-IoT standard achieves up to 20 dB coverage extension
    3 KB (418 words) - 10:39, 6 November 2017
  • Beat DigRF
    ...ration of the communication portion of the node is indispensable. Ideally, System-on-a-Chip (SoC) modems are used.
    2 KB (299 words) - 17:58, 14 April 2016
  • Implementing Hibernation on the ARM Cortex M0
    [[Category:System Design]]
    3 KB (390 words) - 11:59, 20 June 2016
  • Ultra-Efficient Visual Classification on Movidius Myriad2
    [[Category:System Design]]
    4 KB (593 words) - 14:57, 30 November 2016
  • Efficient Implementation of an Active-Set QP Solver for FPGAs
    ...lly, the goal is to attach the developed accelerator to the ARM processing system on the Xilinx Zynq platform, and establish the corresponding software inter : Matlab, C++, VHDL or System Verilog
    4 KB (542 words) - 12:39, 1 June 2017
  • Design of State Retentive Flip-Flops
    ...stablished method to save power in circuit parts currently not in use in a system on chip (SoC). In contrast to clock gating, where the clock signal is disab
    2 KB (364 words) - 09:34, 25 July 2017
  • Standard Cell Compatible Memory Array Design
    Memories are central building blocks of any processing system, in fact most of the performance of a modern processor is determined by its
    5 KB (769 words) - 15:54, 23 May 2018
  • Development of a Rockfall Sensor Node
    [[Category:System Design]]
    2 KB (340 words) - 11:55, 21 August 2018
  • FPGA System Design for Computer Vision with Convolutional Neural Networks
    [[File:origami-fpga-system.png|400px|thumb]] ...o finish the processing pipeline (activation, pooling), and completing the system by connecting a camera or loading a video stream and displaying the results
    3 KB (397 words) - 18:17, 29 August 2016
  • Learning Image Decompression with Convolutional Networks
    <!--[[File:origami-fpga-system.png|400px|thumb]] --> [[Category:Hot]] [[Category:Digital]] [[Category:System Design]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Mas
    2 KB (285 words) - 18:16, 29 August 2016
  • Internet of Things Network Synchronizer
    [1] 3GPP. Cellular System Support for Ultra Low Complexity and Low Throughput Internet of Things. htt
    4 KB (582 words) - 20:00, 26 September 2017
  • Intelligent Power Management Unit (iPMU)
    [[File:iPMU.png|600px|thumb|right|iPMU within a Generalized System]] ...ilable energy for the system and learn the energy consumption of different system tasks. Moreover, the iPMU should profile the available power input from the
    2 KB (292 words) - 11:40, 2 June 2021
  • Gomeza old project3
    ...such as battery or supercapacitor for future use. A correctly dimensioned system will guarantee the node’s operation during periods of energy unavailabili
    3 KB (366 words) - 18:04, 28 January 2017
  • Bateryless Heart Rate Monitoring
    ...rs. In our lab, we have developed a energy management unit, which allows a system designer to provide energy guarantees solely from volatile energy harvestin [[Category:System Design]]
    3 KB (413 words) - 15:21, 28 January 2016
  • Change-based Evaluation of Convolutional Neural Networks
    [[Category:Software]] [[Category:System]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:2016]] * Interest in computer vision and system engineering
    5 KB (747 words) - 18:04, 29 August 2016
  • Using Motion Sensors to Support Indoor Localization
    [[Category:System Design]]
    3 KB (426 words) - 11:41, 21 July 2017
  • Design of a VLIW processor architecture based on RISC-V
    : VHDL/System Verilog knowledge
    3 KB (377 words) - 10:25, 5 November 2019
  • Minimal Cost RISC-V core
    ...ultra low power consumption are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is : VHDL/System Verilog knowledge
    3 KB (384 words) - 17:24, 21 August 2019
  • Turbo Equalization for Cellular IoT
    ...wn approach to improve the overall performance of a wireless communication system. The underlying principle is to feed back soft information from the channel [[Category:System Design]]
    3 KB (450 words) - 11:43, 13 November 2018
  • PULPonFPGA: Hardware L2 Cache
    ...w evaluation platform based on the Juno ARM Development Platform [3]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F : VHDL/System Verilog, C
    5 KB (711 words) - 10:27, 5 November 2019
  • NextGenChannelDec
    [[Category:System Design]]
    3 KB (402 words) - 15:31, 13 April 2016
  • Next Generation Channel Decoder
    [[Category:System Design]]
    3 KB (418 words) - 14:01, 13 November 2020
  • Fast Wakeup From Deep Sleep State
    Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power c *Control system DMA to save/restore L1 data memory
    2 KB (236 words) - 08:35, 20 January 2021
  • Audio Video Preprocessing In Parallel Ultra Low Power Platform
    ...o maintain as much as possible the general purpouse phylosofy of the whole system.
    2 KB (237 words) - 10:27, 5 November 2019
  • Implementation of a NB-IoT Positioning System
    [[Category:System Design]]
    4 KB (555 words) - 16:36, 23 May 2018
  • Design of a Fused Multiply Add Floating Point Unit
    ...tion of the FPUs and therefore reduce the overall power consumption of the system. We have already designed a FPU unit with support for FP-additions, FP-subt ...dware efficient architecture for a fused multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.
    2 KB (346 words) - 10:26, 5 November 2019
  • A Recurrent Neural Network Speech Recognition Chip
    : Knowledge of a hardware design language such as (System)Verilog or VHDL. [[Category:System Design]]
    4 KB (522 words) - 13:38, 10 November 2020
  • Towards Self Sustainable UAVs
    [[Category:System Design]]
    3 KB (403 words) - 20:45, 9 August 2016
  • PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
    : 20% VHDL/System Verilog, FPGA Design : VHDL/System Verilog, C
    5 KB (712 words) - 17:57, 7 November 2017
  • PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
    ...ngs of arbitrary size, independent of the page size of the Linux operating system running on the host CPU. In a student project [4], a second, set-associativ ...and give access to it to user-space applications through, e.g., an mmap() system call. Ideally, all data shared with the accelerator is placed in this secti
    6 KB (866 words) - 13:43, 29 November 2019
  • WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
    ...al-world handset operations in the wide-band code-division multiple-access system. Large-frequency and clock errors are induced at initial search due to an i
    2 KB (340 words) - 10:39, 6 November 2017
  • Self-Learning Drones based on Neural Networks
    [4] Scaramuzza et al., Vision-Controlled Micro Flying Robots: From System Design to Autonomous Navigation and Mapping in GPS-Denied Environments, htt
    6 KB (828 words) - 16:26, 20 February 2018
  • Ultra Low Power Conversion Circuit For Batteryless Applications
    ...nd obtrusive storage element. One of the biggest challenges in batteryless system design is the cold start phase, where the harvesting circuit needs to self- Finally a full system which include the energy harvesting and a sensor (a ultra low power camera
    3 KB (485 words) - 17:46, 10 August 2016
  • 3D Ultrasound Bubble Tracking
    ...setup a basic ultrasound simulation for a moderate (1024) channel count 3D system based on existing scripts. Then he has to assess several tracking algorithm [[Category:System Design]]
    2 KB (253 words) - 20:52, 12 November 2020
  • LightProbe - Ultracompact Power Supply PCB
    [[Category:System Design]]
    2 KB (320 words) - 10:56, 10 January 2017
  • Towards The Integration of E-skin into Prosthetic Devices
    ...nd eventually supply it with energy harvesting from the human body. A full system will be developed that will incldue the processing part, the wireless inter [[Category:System Design]]
    4 KB (631 words) - 11:39, 21 July 2017
  • A Wireless Sensor Network for a Smart Building Monitor and Control
    ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors, intelligence and actuator interconnected ...e power consumption reduction, reliability, functionality and optimize the system.
    4 KB (571 words) - 21:42, 30 July 2018
  • A Wearable System To Control Phone And Electronic Device Without Hands
    ..., televisions, pc among others. The main goal is to achieve an intelligent system that process the data from one or more sensors to understand the context an ...classification accuracy and energy efficiency and to further optimize the system.
    5 KB (669 words) - 17:22, 31 January 2018
  • Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
    ...s kind of communication. The project will also focus on how make the whole system self-sustaining using RF energy harvesting or other kind of energy harvesti [[Category:System Design]]
    4 KB (576 words) - 16:58, 28 July 2017
  • A Wireless Sensor Network for HPC monitoring
    ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors interconnected by wireless links. We want ...e power consumption reduction, reliability, functionality and optimize the system.
    5 KB (617 words) - 16:22, 27 February 2018
  • LightProbe - Frontend Firmware and Control Side Channel
    ...ard-FPGA and to implement the control sidechannel interface to the backend system (a PC in our case). * Design an interface/API such that the firmware can talk to the backend system (UART based)
    3 KB (458 words) - 20:51, 12 November 2020
  • Charging System for Implantable Electronics
    Using mixed-signal SoCs developed at IIS it is possible to integrate a system to conducting medical research. Despite low power consumption of the system the
    3 KB (366 words) - 13:05, 27 April 2018
  • Learning Image Compression with Convolutional Networks
    <!--[[File:origami-fpga-system.png|400px|thumb]] --> [[Category:Hot]] [[Category:Digital]] [[Category:System Design]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category
    3 KB (362 words) - 16:25, 30 October 2020
  • Open Power-On Chip Controller Study and Integration
    ...nodes. Computing nodes based on ARM SoCs are facing the market, as well as system based on the IBM power architecture. To create more market opportunities IB *Good computer architecture and real-time system background.
    3 KB (462 words) - 15:57, 9 September 2016
  • Linux Driver for fine-grain and low overhead access to on-chip performance counters
    *Knowledge of the Linux Operating System architecture
    3 KB (417 words) - 15:55, 9 September 2016
  • LightProbe - Design of a High-Speed Optical Link
    ...ansport this data-rate efficiently from the head to the backend processing system, we use a optical high-speed link. ...d software IPs. Using these IPs allows to build rather easily very complex system. You will be extensively working with the Xilinx Vivado Tool.
    3 KB (409 words) - 10:55, 10 January 2017
  • Ultra Low-Power Oscillator
    ...on the power consumption of those circuits that are always on, like e.g. a system clock. So this topic has seen a lot of attention in recent years. The aim o
    2 KB (368 words) - 18:58, 19 December 2016
  • High performance continous-time Delta-Sigma ADC for biomedical applications
    ...nm CMOS. It will be possible to learn the whole the design cycle including system simulation and layout as a master student, for a semester thesis the work w : 20% System Simulation (Matlab/Simulink)
    3 KB (375 words) - 17:46, 2 May 2017
  • High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
    ...nm CMOS. It will be possible to learn the whole the design cycle including system simulation and layout as a master student. : 20% System Simulation (Matlab/Simulink)
    3 KB (358 words) - 11:40, 20 August 2021
  • PVT Dynamic Adaptation in PULPv3
    ...esis]] [[Category:2016]] [[Category:Barandre]][[Category:PULP]][[Category:System Design]] ...nts the software control loop which maximizes the energy efficiency of the system dynamically tracking the PVT variations
    3 KB (348 words) - 15:31, 13 September 2016
  • Design of low-offset dynamic comparators
    ...ors that are always on are usually slow and exhibit too much noise. When a system clock is available dynamic comparators are an attractive alternative, as th
    3 KB (362 words) - 17:35, 21 December 2017
  • On-chip clock synthesizer design and porting
    Mixed-signal system-on-chips (SoCs) often consist of various independent subsystems (e.g., diff
    3 KB (389 words) - 11:20, 14 September 2016
  • Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
    The student will design and implement an ultra low power system testing the performances of the whole system by using a commercial RF
    4 KB (609 words) - 11:38, 21 July 2017
  • Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
    ...main goal of the design is to optimize the power consumption to allow the system to life several months without change the battery. THe project will be done : Interest in Computer Architectures at system level
    4 KB (502 words) - 11:38, 21 July 2017
  • Efficient NB-IoT Uplink Design
    system.
    6 KB (900 words) - 16:58, 7 May 2018
  • Design of Charge-Pump PLL in 22nm for 5G communication applications
    As the key for wireless transceiver system, Phase-locked loop (PLL) is a general solution for frequency synthesize. In
    4 KB (514 words) - 15:51, 20 August 2021
  • System Analysis and VLSI Design of LTE Cat-M Baseband Processing
    #REDIRECT [[System Analysis and VLSI Design of LTE NB-IoT Baseband Processing]]
    79 bytes (11 words) - 09:49, 19 October 2016
  • System Analysis and VLSI Design of LTE NB-IoT Baseband Processing
    #REDIRECT [[System Analysis and VLSI Design of NB-IoT Baseband Processing]]
    75 bytes (10 words) - 09:49, 19 October 2016
  • State-Saving @ NXP
    [[Category:System Design]]
    2 KB (259 words) - 11:34, 10 November 2017
  • Sensor Fusion for Rockfall Sensor Node
    [[Category:System Software]]
    2 KB (352 words) - 11:51, 21 August 2018
  • Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
    ...(IIS) we have been working on a Parallel Ultra-Low Power Processor (PULP) System for the past two years. PULP is intended to be used for near-sensor computi ...e with basic engineering tools (web search, basic usage of Linux operating system, compilers…) and of work independence
    9 KB (1,427 words) - 18:36, 5 September 2019
  • Towards Online Training of CNNs: Hebbian-Based Deep Learning
    ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne
    6 KB (909 words) - 19:50, 30 May 2017
  • WCDMA/HSPA+ Modem System Design, Implementation, and Testing
    #REDIRECT [[WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing]]
    84 bytes (9 words) - 15:33, 1 December 2016
  • LightProbe - Implementation of compressed-sensing algorithms
    ...in which the signal is digitized directly in the probe and sent to the US system through an optical fiber. This digitization enables a higher flexibility fo [[Category:System Design]]
    4 KB (521 words) - 10:37, 26 October 2021
  • LightProbe
    [[File:Ultralight.jpg|thumb|400px|Current Prototype System]] * Programming of software functions: Microcontroller Programming / Processing system programming (C/C++/CUDA)
    2 KB (254 words) - 14:14, 31 October 2020
  • LightProbe - Thermal-Power aware on-head Beamforming
    ...head. The beamformer is the core processing unit in any ultrasound imaging system as it produces the image from the raw sensor data. Similar to other handhel ...figures the beamformer based on real-time temperature sensor data from the system.
    3 KB (374 words) - 20:50, 12 November 2020
  • Sub Noise Floor Channel Estimation for the Cellular Internet of Things
    ...rly defined algorithmic problem and actually test the result in a complete system with real world data.
    2 KB (295 words) - 11:27, 6 November 2017
  • Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
    ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne
    6 KB (920 words) - 16:33, 3 October 2019
  • Single-Bit-Synapse Spiking Neural System-on-Chip
    ...his project we would like to develop a concrete proof of concept low power System-on-Chip where (small) practical applications such as Spiking Convolutional ...connected. With regard to this, a higher-level synaptic array for the full System-on-Chip must be designed, taking into account even more strict area constra
    7 KB (1,000 words) - 12:22, 13 January 2017
  • Tiny CNNs for Ultra-Efficient Object Detection on PULP
    ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne
    5 KB (794 words) - 13:19, 13 January 2017
  • PULP-Shield for Autonomous UAV
    * Familiarity with embedded system programming in C. [3] Altium Design System http://www.altium.com/
    6 KB (875 words) - 11:06, 23 February 2018
  • Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
    ...classification accuracy and energy efficiency and to further optimize the system. [[Category:System Design]]
    5 KB (703 words) - 17:21, 31 January 2018
  • VLSI Implementation Polar Decoder using High Level Synthesis
    [[Category:System Design]]
    3 KB (392 words) - 14:17, 5 April 2022
  • Development of a syringe label reader for the neurocritical care unit
    Within this project, you will built such a system. It should be able to quickly and robustly scan the labels and provide the ...care, image processing and interface design. A successful implement of the system will improve patient care by reducing the workload on the intensive care st
    2 KB (315 words) - 13:00, 22 February 2017
  • FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
    [[Category:System Design]]
    3 KB (462 words) - 13:54, 13 November 2020
  • Energy-Efficient Brain-Inspired Hyperdimensional Computing
    ...L implementation of HD computing for an EMG-based hand gesture recognition system with fast learning using much lower power than ever before. [[Category:System Design]]
    4 KB (467 words) - 13:38, 10 November 2020
  • Autoencoder Accelerator for On-Chip Semi-Supervised Learning
    * Knowledge of a hardware design language: e.g. (System)Verilog or VHDL
    6 KB (842 words) - 08:37, 20 January 2021
  • Hardware Accelerators for Lossless Quantized Deep Neural Networks
    ...ry purpose of this project is to contribute to the ''Ergo'' deep inference System-on-Chip by designing HW/SW techniques for the acceleration of aggressively ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended
    6 KB (949 words) - 13:41, 10 November 2020
  • Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
    ...f hardware design and computer architecture - having followed the Advanced System-on-Chip Design course is recommended * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics [https://arxi
    6 KB (916 words) - 15:50, 7 December 2018
  • Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
    The prototype system on which the source localization application will be implemented is constit ...of sound waves, at the two ears. Similarly to what is done by our auditory system to detect the azimuthal direction of a sound, by looking at the time differ
    7 KB (1,025 words) - 19:52, 30 May 2017
  • A computational memory unit using phase-change memory devices
    [[Category:System Design]]
    4 KB (546 words) - 11:33, 17 April 2020
  • Deep Learning for Brain-Computer Interface
    [[Category:System Design]]
    3 KB (372 words) - 20:22, 1 April 2019
  • Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
    ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx
    7 KB (1,001 words) - 10:43, 26 June 2017
  • Resilient Brain-Inspired Hyperdimensional Computing Architectures
    [[Category:System Design]]
    3 KB (401 words) - 19:08, 29 January 2021
  • Trace Debugger for custom RISC-V Core
    ...e HDL (hardware description language) of your choice (for example VHDL or (System)-Verilog) as thought in VLSI I and II ...lel Computing Systems for Data Analytics class (formerly known as Advanced System on a Chip)
    5 KB (729 words) - 11:27, 11 December 2018
  • Efficient Search Design for Hyperdimensional Computing
    [[File:Hyperdimensional-Solar-System.jpg|thumb]] [[Category:System Design]]
    3 KB (366 words) - 15:39, 10 November 2020
  • LightProbe - WIFI extension (PCB)
    ...he existing LightProbe prototype with a Wireless LAN module to provide the system with a low-rate (Mbit/s) interface to connect directly with a mobile phone ...ples are provided) and write the required scripts/program on the receiving system (can be a laptop) to capture the sent data.
    2 KB (324 words) - 16:59, 16 September 2022
  • Creating a HDMI Video Interface for PULP
    * VHDL or (System)-Verilog knowledge, VLSI I & II
    4 KB (603 words) - 09:37, 10 July 2018
  • BigPULP: Multicluster Synchronization Extensions
    both dramatically simplifying the programmability of such a heterogeneous system. ...aluation platform [5] based on the Juno ARM Development Platform [6]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F
    6 KB (805 words) - 12:17, 22 January 2018
  • BigPULP: Shared Virtual Memory Multicluster Extensions
    both dramatically simplifying the programmability of such a heterogeneous system. ...aluation platform [5] based on the Juno ARM Development Platform [6]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F
    6 KB (801 words) - 15:05, 23 August 2018
  • Smart Virtual Memory Sharing
    initiatives such as the Heterogeneous System Architecture foundation (HSA) are access to system memory from both sides, eliminating the need for explicit
    6 KB (865 words) - 12:16, 17 November 2017
  • Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
    ...detectors) to reduce the power consumption but also use energy harvesting system such as microbial fuel cell. The communication plays also an important role ...ment of novel zero-power sensors that act as a trigger for the rest of the system when important event is detected and consume zero-power between two detecti
    5 KB (745 words) - 17:21, 31 January 2018
  • Hyper Meccano: Acceleration of Hyperdimensional Computing
    [[Category:System Design]]
    3 KB (409 words) - 13:58, 9 November 2017
  • High Speed FPGA Trigger Logic for Particle Physics Experiments
    [[Category:System Design]] [[Category:System on Chips for IoTs]]
    4 KB (460 words) - 21:42, 30 January 2018
  • Wireless Communication Systems for the IoT
    ...iver, digital baseband processing, and an application processor. Such a RF System-on-Chip (RF-SoC) is mandatory to achieve minimal manufacturing costs.
    3 KB (344 words) - 01:45, 10 February 2021
  • Satellite Internet of Things
    ...nology to cellular connectivity by covering dead spots or as a stand-alone system. NB-IoT itself is seen as a possible technology for satellite IoT (sIoT) an ...upport satellite communication channels. A thorough simulative analysis of system performance will enable the identification of critical bottlenecks. These s
    3 KB (393 words) - 13:53, 13 November 2020
  • Neural Networks Framwork for Embedded Plattforms
    [[Category:System Design]] [[Category:System Design]]
    3 KB (317 words) - 14:40, 14 April 2021
  • BLISS - Battery-Less Identification System for Security
    ...bedded image processing. The ambitious goal is to build a self-sustainable system that allows simple image processing to be implemented on-board the device. ...dy the required components for building a miniature ultra-low power camera system and develop a demonstration platform based on our ULP image sensor chip (de
    4 KB (602 words) - 10:45, 31 January 2023
  • HERO: TLB Invalidation
    both dramatically simplifying the programmability of such a heterogeneous system. ...al of this project is to implement TLB invalidations for our heterogeneous system.
    6 KB (796 words) - 17:19, 18 November 2019
  • Interference Cancellation for the cellular Internet of Things
    ...is a great cellular IoT research opportunity and gives deep insights into system engineering.
    2 KB (269 words) - 13:15, 31 October 2019
  • Beat Cadence
    ...in including RF front-end, dedicated digital baseband hardware, and a CPU system. But, expected area and therefore cost as well as power consumption show ro
    1 KB (217 words) - 11:01, 18 March 2019
  • Deep Convolutional Autoencoder for iEEG Signals
    ...detection and location of such seizures. When aiming a low power implanted system the large amount of data has to be efficiently reduced. iEEG signals are sp
    5 KB (641 words) - 13:36, 9 September 2020
  • Heterogeneous SoCs
    ...exploit their theoretical potential is challenging due to the high overall system complexity. ...our chance to explore and work on (almost) any layer of a running computer system and contribute to energy-efficient next-generation computing platforms!
    3 KB (421 words) - 18:41, 28 October 2020
  • Predictable Execution
    ...be deployed on COTS hardware that limit the memory interference within the system, such that real-time guarantees can be provided, enabling the use of these
    2 KB (286 words) - 18:48, 10 November 2020
  • Energy Efficient Autonomous UAVs
    ...ize, and will thus constitute an increasingly larger fraction of the total system power consumption. * '''2020''' - V. Niculescu et Al., "An Energy-efficient Localization System for Imprecisely Positioned Sensor Nodes with Flying UAVs", ''2020 IEEE 18th
    14 KB (2,077 words) - 15:02, 13 June 2022
  • Aliasing-Free Wavetable Music Synthesizer
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (621 words) - 18:09, 9 October 2022
  • Modular Frequency-Modulation (FM) Music Synthesizer
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (549 words) - 12:35, 28 November 2022
  • Digital Medical Ultrasound Imaging
    At IIS, we are exploring the next generation of medical ultrasound system. Our Flagship projects are: ...rable solutions as well as alternatives to the traditional bulky and rigid system designs.
    6 KB (797 words) - 16:16, 23 February 2024
  • Hyperdimensional Computing
    ...://iis-projects.ee.ethz.ch/index.php/Biomedical_System_on_Chips Biomedical System on Chips] as well as [http://iis-projects.ee.ethz.ch/index.php/Deep_Learnin
    10 KB (1,341 words) - 10:46, 25 April 2018
  • Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
    * Motivation to build and test a real system and acquiring field data [[Category:System Design]]
    7 KB (1,003 words) - 17:30, 6 December 2021
  • CMOS power amplifier for field measurements in MRI systems
    [[Category:System Design]] [[Category:System Design]]
    3 KB (354 words) - 16:06, 6 May 2019
  • Real-Time Implementation of Quantum State Identification using an FPGA
    ...t the FPGA hardware using Verilog or VHDL. You will use Xilinx ISE, Xilinx System Generator, Chipscope, Modelsim, Matlab and Mathamatica as development tools [[Category:System Design]]
    5 KB (599 words) - 09:03, 21 December 2017
  • Inductive Charging Circuit for Implantable Devices
    [[Category:System Design]] [[Category:System Design]]
    3 KB (329 words) - 11:43, 20 August 2021
  • Low Power Geolocalization And Indoor Localization
    ...classification accuracy and energy efficiency and to further optimize the system. [[Category:System Design]]
    5 KB (697 words) - 13:36, 11 January 2018
  • Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
    3D sonar sensors. The proposed system architecture will be developed around an Ultra low power parallel processor * Design of the full system to achieve an autonomous sensor. (PCB design, Low power Techniques, etc.)
    4 KB (518 words) - 11:40, 2 February 2018
  • Wake Up Radio For Energy Efficient Communication System and IC Design
    ...he student he can be involved on the design of the IC, the layout, or at a system and application levler. The wake-up receiver should achieves power consumpt ...classification accuracy and energy efficiency and to further optimize the system.
    5 KB (686 words) - 11:54, 2 February 2018
  • Zero Power Touch Sensor and Reciever For Body Communication
    ...on the human body. The student will work to design a whole application and system exploiting the zero-power communication receiver/sensor. ...classification accuracy and energy efficiency and to further optimize the system.
    4 KB (585 words) - 11:58, 2 February 2018
  • Monocular Vision-based Object Following on Nano-size Robotic Blimp
    * Familiarity with embedded system programming in C.
    5 KB (623 words) - 16:14, 20 February 2018
  • Towards Autonomous Navigation for Nano-Blimps
    * Familiarity with embedded system programming in C.
    7 KB (1,008 words) - 16:20, 20 February 2018
  • Study and Development of Intelligent Capability for Small-Size UAVs
    ...tions, the student will apply the identified modifications to the existing system and develop the additional software tasks. Lastly, an evaluation of the pro * Familiarity with embedded system programming in C.
    6 KB (842 words) - 16:18, 20 February 2018
  • Towards Self-Sustainable Unmanned Aerial Vehicles
    The largest part of any aerial vehicle’s power budget is the mechanical system. A blimp, however, requires significantly less power for horizontal propuls * Familiarity with embedded system programming in C.
    6 KB (914 words) - 16:17, 20 February 2018
  • Biomedical Systems on Chip
    ...nce of several underlying life-long processes, e.g., respiration, vascular system dynamic, muscle contraction. ...ngs vision, the point-of-contact electronic that interfaces the biological system with the cloud-based digital world is very critical due to unique specifica
    2 KB (327 words) - 19:55, 22 February 2018
  • Real-Time ECG Contractions Classification
    [[Category:Biomedical System on Chips]] ...ld you choose to accept it, is to join our active research into biomedical system design. The approach is to used state-of-the-art machine learning algorithm
    4 KB (597 words) - 19:15, 9 March 2020
  • Evaluating An Ultra low Power Vision Node
    ...novel solutions to reducing the energy consumption of such devices on the system-level are required. One of the key ideas in event-driven computing is the r * Basic knowledge of the C language and embedded system programming
    3 KB (433 words) - 15:16, 4 August 2022
  • Predictable Execution on GPU Caches
    ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...memory system at one point in time. To avoid stalling the program when the system is not permitting memory accesses from the program in question, the memory
    5 KB (706 words) - 17:41, 19 June 2019
  • Freedom from Interference in Heterogeneous COTS SoCs
    ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the The goal of this project is to design and integrate a full system configuration of CPU and GPU applications that can be executed concurrently
    4 KB (499 words) - 17:40, 19 June 2019
  • BLISS
    #REDIRECT [[BLISS - Battery-Less Identification System for Security]]
    69 bytes (8 words) - 14:54, 25 April 2018
  • Pulse Oximetry Fachpraktikum
    [[Category:Biomedical System on Chips]]
    3 KB (358 words) - 15:59, 18 February 2019
  • Extend the RI5CY core with priviledge extensions
    ...rs that implements the RISC-V ISA. It has been designed for small embedded system platforms mostly used in IoT devices. Its ISA implements RISC-V's RV32IMFC ...build a testbench for the core to test the IP isolated by the rest of the system. (~3-4 weeks)
    4 KB (661 words) - 08:38, 20 January 2021
  • Wearables for Sports and Life Enhancement
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    3 KB (381 words) - 14:17, 28 January 2023
  • Brunn test
    ====[[Biomedical System on Chips|Biomedical System on Chips]]==== ===[[Biomedical System on Chips|Biomedical System on Chips]]===
    2 KB (311 words) - 12:02, 5 December 2018
  • Engineering For Kids
    ...studies in (primary+) schools we're developing an interesting edutainment system for kids together with the PR of D-ITET and [http://www.wysszurich.uzh.ch w The idea is to create a playful, central interaction system accompanied by distributable modules for the kids to solve and play with.
    3 KB (447 words) - 16:11, 18 September 2018
  • Improving Cold-Start in Batteryless And Energy Harvesting Systems
    ...c capacitance, a minimum amount of energy needs to be harvested before the system can do useful work. A specially designed cold-start circuit can significant ...ll investigate and design a new cold-start circuit that aims to reduce the system’s start-up time. Depending on the chosen architecture, the choice of MPPT
    5 KB (638 words) - 15:41, 10 November 2020
  • Ultra-low power sampling front-end for acquisition of physiological signals
    ...s thesis it will be possible to learn the whole the design cycle including system simulation and layout as a master student, for a semester thesis the work i : 20% System Investigations (Calculation, Matlab)
    2 KB (359 words) - 16:06, 6 May 2019
  • OTDOA Positioning for LTE Cat-M
    ...f needed dedicated hardware blocks can be deisgned and integrated into the system. If time allows the performance of the implementation will be verified with [[Category:System Design]]
    4 KB (566 words) - 15:50, 9 February 2021
  • Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
    : 40% System Simulation (Matlab/Simulink)
    2 KB (356 words) - 15:55, 6 May 2019
  • Optimal System Duty Cycling for a Mobile Health Platform
    ...hanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level d ...dictates battery size, the most critical factor in any volume-constrained system.
    4 KB (597 words) - 16:57, 12 July 2022
  • Ultra-low power transceiver for implantable devices
    ...e thesis it will be possible to learn the whole the design cycle including system simulation and layout as a master student, for a semester thesis the work i
    2 KB (347 words) - 11:43, 20 August 2021
  • Design and Implementation of a multi-mode multi-master I2C peripheral
    ...and not in the chips that we designed ourselves, rendering many low-level system management jobs challenging and cumbersome. In this project, you will exten *Some experience with hardware design (VHDL/(System-)Verilog), for example completion of VLSI I lecture
    2 KB (240 words) - 16:57, 12 July 2022
  • An Industrial-grade Bluetooth LE Mesh Network Solution
    * Identify critical network performance parameters to be integrated in the system design * Implement a BLE mesh reference system by compiling Nordic’s SIGMesh stack onto the Thingy52 IoT dev kits (or si
    5 KB (685 words) - 15:34, 10 November 2020
  • Enabling Standalone Operation for a Mobile Health Platform
    ...iomedical acquisition and processing platform is standalone operation: The system must be able to provide all required supply voltages and clock frequencies [[Category:Biomedical System on Chips]]
    2 KB (268 words) - 16:57, 12 July 2022
  • Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
    [[Category:System Design]]
    5 KB (622 words) - 15:36, 10 November 2020
  • Embedded Gesture Recognition Using Novel Mini Radar Sensors
    ...classification accuracy, and energy efficiency and to further optimize the system. [[Category:System Design]]
    5 KB (631 words) - 15:36, 10 November 2020
  • Physics is looking for PULP
    ...ring this project you will map a 32bit PULPino/PULPissimo micro-controller system to the Altera DE-10 Lite board, adapt the design flow so that prospective u [[Category:System Design]]
    4 KB (497 words) - 16:50, 21 June 2018
  • Design of Scalable Event-driven Neural-Recording Digital Interface
    ...ing” portion of the signal. This reduce the bandwidth from the recording system depending on the signal activity (more interesting events --> higher bandwi In the context of action potentials, a neural recording system can send to a digital processor only the spikes and do not send anything wh
    8 KB (1,269 words) - 18:40, 5 September 2019
  • LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
    ...a solution to be used in our high-performance GPU-based ultrasound imaging system. * Implementation of the RDMA subsystem for our ultrasound system
    2 KB (340 words) - 16:58, 16 September 2022
  • Human Intranet
    ...with the functions provided by the body itself. Human Intranet presents a system vision in which, for example, disease would be treated by chronically measu * '''System-level design and testing''' (Altium, C-programming)
    17 KB (2,419 words) - 20:09, 10 March 2024
  • Positioning for the cellular Internet of Things
    ...rrival (OTDOA) such as covered in [[Implementation of a NB-IoT Positioning System]] or [[OTDOA Positioning for LTE Cat-M]]
    1 KB (204 words) - 13:14, 31 October 2019
  • Low Latency Brain-Machine Interfaces
    ...r rhythms (SMR) and movement-related cortical potentials (MRCP). SMR-based system make use of event-related synchronisation/desynchronisation (ERD/ERS) behav
    4 KB (594 words) - 09:18, 16 September 2021
  • A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
    ..., non-invasive method to measure kidney performance via an external sensor system to avoid the use of urinary catheters for this subgroup of patients, thereb ...classification accuracy, and energy efficiency and to further optimize the system. The work includes the modeling and design of a suited impedance sensor, it
    6 KB (857 words) - 15:37, 10 November 2020
  • Indoor Smart Tracking of Hospital instrumentation
    ...ional demands on hospital staff. The goal of the project is set-up a whole system that includes readers and mobile tags. For example in the case of the RFID, [[Category:System Design]]
    6 KB (780 words) - 15:37, 10 November 2020
  • Ultrasound High Speed Microbubble Tracking
    ...imaging only and has only been demonstrated with large research ultrasound system. ...t Microbubbles (this may requires to modify the imaging method used by the system)
    3 KB (391 words) - 20:49, 12 November 2020
  • Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
    ...al ultrasound probe to capture the raw sensor data and transfer it to a PC system for fully software-defined processing, offering unprecedented flexibility a ...we at IIS have demonstrated that this novel architecture is feasible for a system with 64 channels ([[LightProbe]]), it yet has to be demonstrated that this
    2 KB (250 words) - 20:48, 12 November 2020
  • Wireless Sensing With Long Range Comminication (LoRa)
    ...esinged node will also include energy harvesting to allow a self-sustainig system. [[Category:System Design]]
    5 KB (744 words) - 15:37, 10 November 2020
  • Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
    [[Category:System Design]]
    4 KB (594 words) - 15:38, 10 November 2020
  • AMZ Driverless Competition Embedded Systems Projects
    '''Embedded stereo visual inertial system''' ...omputing system. In addition, some image processing should be done at this system to reduce the overhead of the network and to compute the first steps on the
    6 KB (895 words) - 16:27, 30 October 2020
  • Edge Computing for Long-Term Wearable Biomedical Systems
    ...eting two application scenarios: behind-the-ear EEG and ECG wristband. The system will also be used to explore applications scenarios for augmenting current [[Category:System Design]]
    6 KB (761 words) - 15:38, 10 November 2020
  • IBM Research
    ...l set of basic operations on high-dimensional vectors, we obtain hybrid AI system (HAS) that makes it possible to represent and manipulate data in ways famil *General interest in Deep Learning and memory/system design
    9 KB (1,330 words) - 15:20, 15 March 2024
  • Analog Compute-in-Memory Accelerator Interface and Integration
    ...iM accelerator and integrate the accelerator into a modern microcontroller system. 4. Verify functionality of the system
    3 KB (352 words) - 18:02, 16 December 2022
  • Elliptic Curve Accelerator for zkSNARKs
    [[Category:System Design]] [[Category:System on Chips for IoTs]]
    5 KB (614 words) - 15:02, 4 March 2019
  • Design and Evaluation of a Small Size Avalanche Beacon
    ...ch mode as well as the non-critical application should allow to reduce the system complexity significant and facilitates, therefore, a higher integration and ...erization of a discrete small size low power RF transmitter in an embedded system: prototype development, verification of the prototype's characteristics w.r
    5 KB (729 words) - 10:02, 22 February 2021
  • Outdoor Precision Object Tracking for Rockfall Experiments
    [[Category:System Design]]
    5 KB (714 words) - 08:37, 23 November 2022
  • Wearable Ultrasound for Artery monitoring
    ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with ...ign a dedicated casing to facilitate the usage of the probe and making the system a real product.
    3 KB (361 words) - 19:02, 6 December 2023
  • Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
    ...ion and the classifier are meant to be implemented on a low-power embedded system. Given the constrained conditions under which we operate, i.e. implantable : Embedded system programming
    5 KB (634 words) - 19:20, 9 March 2020
  • Battery indifferent wearable Ultrasound
    ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with [[Category:System Design]]
    3 KB (337 words) - 18:42, 6 December 2023
  • Design of combined Ultrasound and Electromyography systems
    ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with ....org/document/9630034] UStEMG: an Ultrasound Transparent Tattoo-based sEMG System for Unobtrusive Parallel Acquisitions of Muscle Electro-mechanics
    3 KB (437 words) - 19:03, 6 December 2023
  • Stand-Alone Edge Computing with GAP8
    Motivation to build and test a real system
    3 KB (363 words) - 14:38, 14 April 2021
  • Multisensory system for performance analysis in ski jumping (M/1-2S/B)
    ...roject focusses on the development of an unobtrusive multisensory embedded system to assist coaches to better quantify jumping trajectories of athletes. With ...perceptible to the athlete so as not to disturb his/her sensitive jumping system.
    6 KB (820 words) - 12:13, 23 July 2023
  • Energy Efficient Serial Link
    Our project is designed to provide a reliable and efficient communication system that is optimized for IoT applications. Our project incorporates advanced p
    2 KB (243 words) - 11:44, 14 February 2023
  • Energy Efficient AXI Interface to Serial Link Physical Layer
    ...d data compression. The project will require simulation and testing of the system to verify its performance, power consumption, and compatibility with differ * Experience with System Verilog or Verilog, VLSI 1
    2 KB (250 words) - 18:21, 20 February 2023
  • Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
    ...are, we can guarantee a high flexibility of the setup. This means that the system can be adapted in operation for a wide variety of transducer types and setu The main goal of this work is to develop a modular system for the characterization and tuning of ultrasonic transducers both in hard-
    5 KB (644 words) - 18:18, 21 July 2023
  • NAND Flash Open Research Platform
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    4 KB (551 words) - 11:06, 11 July 2019
  • A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
    ...A, configuration of the SDR, and the evaluation in Matlab. Eventually, the system has to be tested thoroughly. ...plore.ieee.org/document/8351613] A. Moin et al, An EMG Gesture Recognition System with Flexible High-Density Sensors and Brain-Inspired High-Dimensional Clas
    5 KB (731 words) - 16:42, 27 August 2019
  • Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    4 KB (517 words) - 17:09, 16 September 2021
  • NVDLA meets PULP
    [[File:nvdla_memory.png|right|NVDLA Memory System and High-Level Architecture]] ...hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data An
    6 KB (799 words) - 13:42, 10 November 2020
  • Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
    ...propose to build the next OPEN-SOURCE RISC-V programmable smart-peripheral system for the Ariane Core. ...ct the PULPissimo microcontroller to the Ariane coreplex and map the whole system to the FPGA. Note that Ariane has already been mapped to the FPGA and it is
    7 KB (1,030 words) - 19:05, 29 January 2021
  • SmartRing
    Now we would like to upgrade the system by adding advanced machine learning capabilities for sensor fusion and repl ...age and frequency scaling (ADVFS) within the chip. In the end, upgrade the system with your energy harvesting solution.
    4 KB (522 words) - 10:45, 31 January 2023
  • Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
    ...is thesis, you will design a novel heterogeneous interconnect for the PULP system to connect high-throughput hardware accelerators to ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended
    7 KB (961 words) - 21:21, 29 January 2019
  • Timing Channel Mitigations for RISC-V Cores
    ...act''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - ' ...hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data An
    6 KB (915 words) - 18:16, 20 May 2020
  • Developing a small portable neutron detector for detecting smuggled nuclear material
    [[Category:System Design]] [[Category:System on Chips for IoTs]]
    5 KB (623 words) - 10:32, 5 November 2019
  • Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
    ...ectrometer may be used in combination with different devices, the designed system should be easily adaptable to different use cases.
    4 KB (506 words) - 18:26, 5 November 2019
  • ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
    ...ct the way biomechanical measurements are performed today, as the proposed system should be easy and quick to use (e.g., time is key for testing patients in [[Category:System on Chips for IoTs]]
    6 KB (735 words) - 12:12, 23 July 2023
  • LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
    Now, we want to equip the system with a 192 element sensor to achieve better image quality (resolution, cont ...and electrical constraints to be properly be intergated with the existing system.
    2 KB (263 words) - 20:47, 12 November 2020
  • Floating-Point Divide & Square Root Unit for Transprecision
    ...ly. In contrast to approximate computing where the precision of the entire system is reduced - often incurring loss in result quality - transprecision comput * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx
    8 KB (1,135 words) - 17:09, 29 July 2020
  • LightProbe - CNN-Based-Image-Reconstruction
    * Simulation of the ultrasound imaging system to evaluate the idea (feasibility & performance) * Implement the idea on our system (only in case of a Master Thesis)
    2 KB (220 words) - 20:46, 12 November 2020
  • Channel Estimation for 5G Cellular IoT and Fast Fading Channels
    ...t fading channels is thus needed to improve the performance of the current system in such scenarios.
    3 KB (415 words) - 18:54, 29 October 2020
  • FPGA Testbed Implementation for Bluetooth Indoor Positioning
    ...iously developed digital baseband receiver block integrated in a processor system shall be used as a starting point. As a first step you will identify the in
    3 KB (431 words) - 21:47, 18 November 2019
  • Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
    ...he occurrence of ionization events due to cosmic radiation. The monitoring system has to acquire the frequency of the ionizing events and the amount of the c : • Design the monitoring system
    4 KB (493 words) - 16:31, 5 June 2019
  • Heroino: Design of the next CORE-V Microcontroller
    **system: ***src: Top-level and auxiliary files for the core-v-mcu system.
    9 KB (1,314 words) - 00:01, 7 February 2021
  • PREM Intervals and Loop Tiling
    ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...memory system at one point in time. To avoid stalling the program when the system is not permitting memory accesses from the program in question, the memory
    4 KB (531 words) - 18:00, 19 June 2019
  • Compiler Profiling and Optimizing
    ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...memory system at one point in time. To avoid stalling the program when the system is not permitting memory accesses from the program in question, the memory
    3 KB (466 words) - 18:20, 19 June 2019
  • Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
    ...E capacitive sensing: pass information across an air gap. Design analogous system to perform a measurement task. For reference: https://www.st.com/en/solutio 5: Consumable ID: Design a new data frame of credit card reader/writer style system. Current format is 12mm in length, 8mm length required.
    5 KB (645 words) - 15:41, 10 November 2020
  • PULP in space - Fault Tolerant PULP System for Critical Space Applications
    ...pikes due to cosmic rays being captured by sequential elements, taking the system into a faulty state.
    6 KB (980 words) - 14:46, 2 June 2021
  • Fault Tolerant OpenPULP System for Critical Spacial Applications
    #REDIRECT [[PULP in space - Fault Tolerant PULP System for Critical Space Applications]]
    88 bytes (13 words) - 13:10, 9 August 2019
  • Visualizing Functional Microbubbles using Ultrasound Imaging
    [[Category:System Design]]
    2 KB (305 words) - 15:28, 23 October 2023
  • Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
    * Motivation to build and test a real system [[Category:System Design]]
    4 KB (519 words) - 15:41, 10 November 2020
  • Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
    ...ortant component in sevral cyber-physical systems. Among other, the vision system of a self-driving takes advantage of DNNs to better recognize pedestrians, * Motivation to build and test a real system
    4 KB (509 words) - 15:41, 10 November 2020
  • Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
    ...rphic intelligence using their processor to build a whole working embedded system. The student will deal with both hardware and software building a prototype * Motivation to build and test a real system
    5 KB (692 words) - 15:45, 10 November 2020
  • High-throughput Embedded System For Neurotechnology in collaboration with INI
    ...ock diagram, which involves both the programming of a Low power FPGA and a System on Chip with ARM cortex-M4F and Bluetooth low energy 5.0. The project is qu * Motivation to build and test a real system
    4 KB (526 words) - 15:48, 10 November 2020
  • Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
    * Motivation to build and test a real system [[Category:System Design]]
    4 KB (500 words) - 15:48, 10 November 2020
  • Manycore System on FPGA (M/S/G)
    <!-- Manycore System on FPGA --> At ETH, we are developing our own many-core system called MemPool [1]. It boasts 256 lightweight 32-bit Snitch cores developed
    8 KB (1,319 words) - 10:41, 6 July 2021
  • Hardware Acceleration
    ...essors. This ''separation of compute acceleration and control'' limits the system's flexibility and real-world performance as communication and data exchange
    7 KB (917 words) - 17:04, 24 November 2023
  • Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
    : 80% System Development [[Category:System on Chips for IoTs]]
    5 KB (584 words) - 12:09, 29 October 2020
  • Event-Driven Convolutional Neural Network Modular Accelerator
    4. test and assess system level functionality, and provide post layout power/performance estimations
    4 KB (651 words) - 19:10, 29 January 2021
  • TCNs vs. LSTMs for Embedded Platforms
    ...performing one, the student will proceed with embedded implementation and system integration in order to demonstrate a real-life application using sensor ac
    2 KB (317 words) - 11:10, 21 July 2020
  • BirdGuard
    ...as a basis for prototyping the BirdGuard algorithms and the deterrence sub-system. Swiss research institutes are at the forefront of researching birds and ap The BirdGuard system aims to complement existing passive approaches by providing an easy-to-use
    5 KB (647 words) - 08:32, 23 February 2023
  • Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
    ...ly transmitting, easy to install and cost-effective for wind turbines. The system will integrate novel embedded signal processing solutions, including artifi ...classification accuracy, and energy efficiency and to further optimize the system. Energy Harvesting can be also employed to design the sensor node, and this
    5 KB (737 words) - 15:48, 10 November 2020
  • Spiking Neural Network for Autonomous Navigation
    4. Quantize and deploy the network on a PULP system equipped with modular SNN accelerator, and evaluate the accuracy loss cause
    4 KB (644 words) - 19:10, 29 January 2021
  • Semi-Custom Digital VLSI for Processing-in-Memory
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    7 KB (882 words) - 14:33, 28 July 2021
  • Hyper-Dimensional Computing Based Predictive Maintenance
    * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx
    5 KB (759 words) - 09:18, 16 September 2021
  • Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
    ...ulation, data pre-processing, wireless power and data transfer and overall system control. Data is generally processed inside the implant in the digital doma
    3 KB (381 words) - 11:22, 21 July 2020
  • Accurate deep learning inference using computational memory
    [[Category:System Design]]
    5 KB (628 words) - 12:51, 17 April 2020
  • ASIC Implementation of Jammer Mitigation
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (662 words) - 13:31, 10 May 2023
  • Real-Time Motor-Imagery Classification Using Neuromorphic Processor
    ...ented in a neuromorphic processor, and none of them are presenting a whole system from the data acquisition to the processing. ...of the present project is to investigate and develop a novel neuromorphic system for Brain–computer interfaces, trained for multi-class motor-imagery, th
    6 KB (815 words) - 20:02, 10 March 2024
  • Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
    ...isfy electrical constraints to be properly be intergated with the existing system.
    5 KB (620 words) - 07:56, 26 May 2020
  • Compression of iEEG Data
    ...detection and location of such seizures. When aiming a low power implanted system the large amount of data has to be efficiently reduced. iEEG signals are sp
    5 KB (636 words) - 20:01, 10 March 2024
  • Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
    : Embedded system programming
    5 KB (619 words) - 19:58, 10 March 2024
  • Improved State Estimation on PULP-based Nano-UAVs
    ...ehicles. There are several embodiments of the PULP paradigm, one of them a system-on-chip (SoC) called ''Mr.Wolf''[5]. This SoC features 9 cores, divided int
    8 KB (1,117 words) - 22:17, 26 January 2022
  • Deep Learning-based Global Local Planner for Autonomous Nano-drones
    [[File:GL_dpalossi.png|thumb|right|1000px|Overview of the cyber-physical system.]] ...tiple workloads thanks to a parallel ultra-low power octa-core (PULP) GAP8 System-on-Chip [6].
    4 KB (571 words) - 12:11, 27 January 2022
  • An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
    ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx
    7 KB (1,032 words) - 15:31, 16 November 2020
  • High Performance SoCs
    ...oncept.png|thumb|350px|Concept art for ''Manticore'', a Snitch-based 22 nm system with 4096 cores on multiple chiplets and with HBM2 memory.]] ...ing chips with industry-grade automated test equipment (ATE) and design of system-level demonstrator boards.
    11 KB (1,337 words) - 10:54, 25 January 2024
  • Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
    ...s is to have Halide programmed image processing kernels running on an HERO system implemented on an FPGA.
    5 KB (737 words) - 17:26, 2 November 2020
  • A Flexible Peripheral System for High-Performance Systems on Chip (M)
    <!-- (M): A Flexible Peripheral System for High-Performance Systems on Chip --> One of the most tedious and error-prone steps is assembling a peripheral system with the required and desired IO; this usually involves adapting existing p
    11 KB (1,675 words) - 15:40, 15 March 2021
  • A Snitch-based Compute Accelerator for HERO (M/1-2S)
    ...0px|alt=A HERO system with a Zynq MPSoC coupled to a Snitch cluster|A HERO system with a Zynq MPSoC coupled to a Snitch cluster]] ...onents are meant to be exchangeable. HERO features a shared virtual memory system between host and accelerator and provides a heterogeneous compiler toolchai
    11 KB (1,617 words) - 23:59, 6 February 2021
  • Peak-to-average power Reduction
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    4 KB (513 words) - 14:16, 24 November 2021
  • Software-Defined Paging in the Snitch Cluster (2-3S)
    * 25% System programming
    4 KB (563 words) - 20:08, 15 February 2021
  • DaCe on Snitch (M/1-3S)
    ...everaging the DaCe framework to generate code for ETH’s Snitch processor system.
    2 KB (333 words) - 20:05, 15 February 2021
  • VLSI Implementation of a 5G Ciphering Accelerator
    [[Category:System Design]]
    3 KB (404 words) - 10:05, 9 February 2021
  • PREM Runtime Scheduling Policies
    Modern heterogeneous System-on-Chips (SoCs) are cost-efficient and feature the processing power requir
    2 KB (313 words) - 11:47, 2 November 2020
  • Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
    ...n technique is to combine multiple instances of a core to a ''multi-core'' system. This technique introduces a new challenge: Each core keeps its own copy of * a coherent memory system must be able to invalidate or update specific cache lines, and to request s
    3 KB (395 words) - 16:32, 15 November 2022
  • Machine Learning on Ultrasound Images
    ...l work with Ultrasound Images acquired with a high-end Ultrasound research system, to build ML algorithms for the extraction of such physiological features. [[Category:System Design]]
    2 KB (258 words) - 15:28, 23 October 2023
  • Minimum Variance Beamforming for Wearable Ultrasound Probes
    [[Category:System Design]]
    3 KB (378 words) - 16:57, 16 September 2022
  • Time Gain Compensation for Ultrasound Imaging
    The [[LightProbe]] system is designed to acquire ultrasound data for many different applications (e.g ...of LightProbe, you will identify the approach to use to include TCG in the system, and, once implemented, you will perform ultrasound test measurements on ph
    2 KB (318 words) - 16:58, 16 September 2022
  • Smart Meters
    The students will work on a Smart Meter, an IoT system based on: The system will periodically wake up, take a picture, process the image extracting the
    3 KB (396 words) - 10:14, 23 August 2023
  • Event-Driven Vision on an embedded platform
    ...novel solutions to reducing the energy consumption of such devices on the system-level are required. One of the key ideas in event-driven computing is the r * Basic knowledge of the System Verilog or VHDL language and circuit design (VLSI 1)
    3 KB (449 words) - 08:41, 17 February 2021
  • IP-Based SoC Generation and Configuration (1-3S/B)
    ...IPs is the norm, but becomes more difficult and error-prone the larger the system becomes. ...simply a loose collection of scripts and templates shipped with the Snitch system [https://github.com/pulp-platform/snitch]. You will
    4 KB (617 words) - 10:19, 3 November 2023
  • Implementation of a Heterogeneous System for Image Processing on an FPGA (M)
    #REDIRECT [[Implementation of a Heterogeneous System for Image Processing on an FPGA (S)]]
    90 bytes (13 words) - 17:26, 2 November 2020
  • Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
    ...s private memory banks---this, however, impacts the programmability of the system. ...eved through a cache hierarchy, which impacts the energy efficiency of the system through its non-negligible power consumption.
    8 KB (1,196 words) - 10:41, 6 July 2021
  • Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
    ...ature extraction, and since it has been showed that the performance of the system can be largely influenced by this choice, the aim of this project is to do ...representation of the signal to the actual response of the human auditory system. The derivation techniques are described in detail in [[#ref-lyonmfcc|&#91;
    13 KB (1,815 words) - 13:31, 15 February 2024
  • Physical Implementation of MemPool, PULP's Manycore System
    #REDIRECT [[Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)]]
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  • Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
    : 80% System Development [[Category:System on Chips for IoTs]]
    8 KB (931 words) - 17:27, 23 November 2021
  • Matteo Perotti
    * Computer and System Architectures
    1 KB (120 words) - 15:52, 9 August 2023
  • MemPool on HERO (1S)
    ...ure 1 shows the block diagram of HERO. It features a shared virtual memory system between host and accelerator and provides a heterogeneous compiler toolchai ...ftware to interact with a PMCA, such as MemPool. In this step, the MemPool system will be integrated and connected to HERO’s accelerator interface.
    6 KB (902 words) - 19:07, 20 January 2021
  • An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
    * Synthesize your controller and the surrounding system; create area and timing reports. * Implement your system on an ASIC and tape it out.
    8 KB (1,214 words) - 15:18, 9 July 2021
  • Efficient TNN compression
    # Design and verify a ternary compression algorithm in System Verilog or VHDL * Basic knowledge of System Verilog or VHDL and digital circuit design (VLSI 1)
    3 KB (438 words) - 08:41, 17 February 2021
  • ISA extensions in the Snitch Processor for Signal Processing (M)
    .../>[[#ref-RISCV_P|8]]]. The set of instructions that should be added to the system is not fixed, but the student should implement and evaluate different image
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  • Cell-Free mmWave Massive MIMO Communication
    A cell-free system is a network formed by distributed access points (APs) over a large area co ...tudied in [3]. Last, to solve the lack of usage of all APs in this type of system, [4] presents an energy efficient AP sleep mode-technique that is able to d
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  • Practical Reconfigurable Intelligent Surfaces (RIS)
    [[File:Image_RIS.png|400px|thumb|RIS aided wireless system.]] In [1], a RIS is used in the downlink of a MIMO system to investigate the improvement provided by these devices in terms of energy
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  • Biomedical Circuits, Systems, and Applications
    ...ch topics are actively ongoing around the human body, from chip design, to system development, to algorithmic investigations in various application scenarios [[File:ustemg.jpg|thumb|left|120px| Ultrasound Transparent EMG System]]
    9 KB (1,292 words) - 19:16, 23 March 2024
  • Snitch meets iCE40 (1-2S/B)
    * How much power does a Snitch system consume, what is the minimum power required, and can we compete with a micr * Familiarize yourselves with the Snitch system
    2 KB (365 words) - 20:03, 15 February 2021
  • Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (653 words) - 11:08, 12 November 2020
  • Low-Resolution 5G Beamforming Codebook Design
    ...the signals transmitted by the individual antenna elements, providing the system with the capability to “beamform,” that is, to control the direction an : 70% System development
    6 KB (829 words) - 11:37, 12 November 2020
  • Deep Unfolding of Iterative Optimization Algorithms
    ...the project is to then implement Deep Unfolding on a resource-constrained system, like a Raspberry Pi. This project requires familiarity with calculus and p : 20% Software implementation in resource-constrained system
    6 KB (748 words) - 13:57, 12 November 2020
  • ASIC Development of 5G-NR LDPC Decoder
    [[Category:System Design]]
    3 KB (389 words) - 01:43, 10 February 2021
  • Autonomus Drones With Novel Sensors And Ultra Wide Band
    ...as complete autonomous drones. The students will follow the full flow from system design to firmware implementation and they can also deal with machine learn * A complete hardware and software prototype of drones and smart sensor system, which includes all the subsystems (sensor acquisition, preprocessing, and
    5 KB (646 words) - 11:39, 30 November 2020
  • Smart Patch For Heath Care And Rehabilitation
    ...a team, they will learn how to structure problems and identify solutions, system analysis, and simulation, as well as presentation and documentation techniq * Motivation to build and test a real system and acquiring field data
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  • Matheus Cavalcante
    * Computer and System Architecture
    890 bytes (104 words) - 18:33, 8 December 2020
  • Short Range Radars For Biomedical Application
    ...goal of the present project is to investigate and develop a novel embedded system for acquiring and processing short range data with machine learning. Accord ...ncrease the response time of the detection, aiming to achieve an always-on system.
    5 KB (692 words) - 12:46, 17 December 2021
  • Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
    ...onnecting 4 Baikonur ASICs through their serial links, creating a 104-core system with both application- and HPC-grade cores. ...onality. However, a lot of work still needs to be done to ''bring up'' the system so we can turn use it as an impressive evaluation and demonstration platfor
    11 KB (1,602 words) - 15:19, 9 July 2021
  • Compression of Ultrasound data on FPGA
    ...is equipped with a wireless link, which is the main power consumer of the system. [[Category:System Design]]
    2 KB (273 words) - 16:57, 16 September 2022
  • Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
    ...ulation, data pre-processing, wireless power and data transfer and overall system control. Data is generally processed inside the implant in the digital doma
    3 KB (388 words) - 09:25, 16 September 2021
  • Efficient Synchronization of Manycore Systems (M/1S)
    ...his coordination can limit the potential speedup offered by the multi-core system according to Amdahl’s law [[#ref-Hennessy2017|&#91;1&#93;]]. Efficient m ...uch an instruction requires the support of the interconnect and the memory system. We recently developed and published ATomic UNit (ATUN) [[#ref-Kurth2020|&
    12 KB (1,864 words) - 12:08, 29 August 2022
  • Low-Dropout Regulators for Magnetic Resonance Imaging
    ...the reference oscillator responsible for delivering the main clock of the system. The latter will be more challenging with adjustable input and output volta
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  • Transforming MemPool into a CGRA (M)
    ...ool’s flexibility by having a duality of modes. The result is a flexible system that achieves a very high throughput for systolic workloads. ...y. Therefore, you drastically reduce the power consumption and improve the system’s efficiency. Again, the impact of this network has to be analyzed in Mem
    13 KB (1,887 words) - 15:51, 17 November 2021
  • Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
    ...f this project is to take a step towards a fully-featured autonomous Linux system based on Ariane with extensive user interaction support. To this end, you w ...his project, you will learn to work with and extend an advanced processing system all the way from the RTL/hardware level to the Linux kernel and userspace l
    7 KB (1,122 words) - 15:21, 9 July 2021
  • A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
    ...CB for the iCE40 family to facilitate measurements and/or demonstrate your system in action. Can we compete with a microcontroller in terms of performance an
    8 KB (1,220 words) - 15:18, 9 July 2021
  • LLVM and DaCe for Snitch (1-2S)
    * Extending DaCe to generate efficient code for a Snitch system from SDFGs, ideally for the existing Snitch-HERO platform. ...isting C++ DaCe backend to emit LLVM-compilable code for a manycore Snitch system like Snitch-HERO. Validate your implementation on simple kernels or selecte
    11 KB (1,519 words) - 15:20, 9 July 2021
  • Implementing A Low-Power Sensor Node Network
    * Basic knowledge of the C language and embedded system programming
    2 KB (366 words) - 15:53, 11 October 2021
  • Efficient TNN Inference on PULP Systems
    ...pport for sub-byte arithmetic operations (e.g., 16x2b MAC) and construct a system around the improved core, which will be taped out. You get to build your ow
    5 KB (768 words) - 15:14, 4 August 2022
  • Wearables in Fashion
    [[Category:System Design]]
    3 KB (463 words) - 08:38, 23 November 2022
  • Online Learning of User Features (1S)
    ...e user’s characteristics can considerably improve the performance of the system. We want to explore how the user-specific features can be exploited in orde ...ility of those features belonging to a certain class. A schematic of a KWS system can be seen in Figure 1.
    11 KB (1,610 words) - 11:00, 14 November 2022
  • Securing Block Ciphers against SCA and SIFA
    ...A countermeasure on top of the existing design, and 3) drive the resulting system through an ASIC tapeout process. : 60% VHDL/System Verilog, ASIC Design
    6 KB (849 words) - 18:43, 23 November 2021
  • Huawei Research
    *General interest in Deep Learning and memory/system design ...p-digital-ic-design-engineer HW Design and Enhancement for ML Acceleration System] || AI Acceleration || digital VLSI design || [mailto:renzo.andri@huawei.c
    6 KB (799 words) - 11:11, 1 August 2022
  • Ibex: Tightly-Coupled Accelerators and ISA Extensions
    ...sor. The project can be done in the context of a single-core or multi-core system such as PULP where the accelerator is shared by multiple Ibex cores.
    6 KB (835 words) - 12:52, 27 April 2021
  • Ultrasound Low power WiFi with IMX7
    * Test the throughput of the system and corresponding power consumption. [[Category:System Design]]
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  • Automatic unplugging detection for Ultrasound probes
    ...Thus, wireless transmission of non-relevant information makes the overall system inefficient. ...result in power saving, and thus increased operation time of the wearable system.
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  • Ultrasound
    ...work on the development of hardware and software for a complete biomedical system.
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  • Novel Metastability Mitigation Technique
    Modern system-on-a-chip is usually an integration of heterogeneous building blocks. Such
    2 KB (203 words) - 18:03, 16 December 2022
  • Hardware/software codesign neural decoding algorithm for “neural dust”
    ...while reducing the damage caused by the implantation [1][2]. However, such system also poses stringent constraints on the power consumption and area. 2. Get familiar with the dataset and the system
    4 KB (519 words) - 16:16, 9 January 2023
  • Spiking Neural Network for Motor Function Decoding Based on Neural Dust
    2. Get familiar with the dataset, the system, and the deep learning framework
    5 KB (662 words) - 20:05, 10 March 2024
  • Ternary Neural Networks for Face Recognition
    ...ully applied to the problem to increase the energy efficiency of the final system. One such class of networks are ternary neural networks (TNNs), where all w
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  • Fast Simulation of Manycore Systems (1S)
    At ETH, we are developing our own many-core system called MemPool [[#ref-Cavalcante2020|&#91;1&#93;]], [[#ref-Riedel2021|&#91 ...y rely on cycle-accurate RTL simulation. However, simulation of such a big system is slow, even on the latest commercial simulators. This limits the complexi
    10 KB (1,434 words) - 17:20, 2 August 2021
  • Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
    At ETH, we are developing our own many-core system called MemPool. It boasts 256 lightweight 32-bit Snitch cores. They impleme This manycore system with vector support is to be analyzed in terms of the performance improveme
    11 KB (1,609 words) - 10:00, 30 June 2022
  • Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
    ...an hardware design at the circuit level of time-encoded SNNs to high-level system simulations in a high-performance computing framework. It also involves int
    3 KB (360 words) - 10:54, 31 August 2021
  • Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
    ...This means that their definition could be propagated throughout the memory system to further hide latency, minimize traffic, and improve memory management (p ...ergy, and timing impact of these extensions on a minimal end-to-end memory system (extended core, memory, and any adapters needed) running simple application
    4 KB (557 words) - 16:14, 6 November 2022
  • Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
    ...d within a single layer. In order to utilize these results in a real-world system, we need to map the resulting mixed-precision network to an appropriate rep
    3 KB (497 words) - 22:15, 23 November 2022
  • EEG artifact detection for epilepsy monitoring
    Epilepsy is a central nervous system disorder in which brain activity becomes abnormal, causing seizures or peri ...Mr. Wolf multicore processor on board. The project’s goal is to design a system capable of detecting various artifacts and then indicate to the user that a
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  • Novel Methods for Jammer Mitigation
    ...uous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt ...oped in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics a
    6 KB (687 words) - 13:32, 10 May 2023
  • EEG artifact detection with machine learning
    Epilepsy is a central nervous system disorder in which brain activity becomes abnormal, causing seizures or peri
    4 KB (561 words) - 15:25, 23 October 2023
  • Probing the limits of fake-quantised neural networks
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (659 words) - 14:08, 15 February 2024
  • Feature Extraction for Speech Recognition (1S)
    ...ature extraction, and since it has been showed that the performance of the system can be largely influenced by this choice, the aim of this project is to do ...representation of the signal to the actual response of the human auditory system. The derivation techniques are described in detail in [[#ref-lyonmfcc|&#91;
    12 KB (1,688 words) - 11:00, 14 November 2022
  • Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
    ...ware-constrained devices, expanding the capabilities of a keyword spotting system. ...pervised information. This is possible due to the prior knowledge that the system has over the nature of the data that it is presented with, and it is a spec
    12 KB (1,869 words) - 17:37, 1 September 2023
  • Modular Distributed Data Collection Platform
    ...e:motivation_sensor.png|200px|thumb|right|Example of remote controlled DAQ system]] ...to remote control the local data acquisition. Regarding energy supply, the system should be designed as a hybrid solution. It will incorporate a battery-powe
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  • VLSI Design of an Asynchronous LDPC Decoder
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    6 KB (725 words) - 17:36, 20 October 2021
  • Ultra low power wearable ultrasound probe
    ...ltrasound data acquisition from a reduced number of channels. The proposed system architecture is based on an MSP430 MCU, which is equipped with an Ultrasoun [[Category:System Design]]
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  • Mixed-Precision Neural Networks for Brain-Computer Interface Applications
    ...magined by the user by means of BCI devices. Once fully functional, such a system would be of immeasurable value in the design of, e.g., motorized prostheses
    8 KB (1,101 words) - 20:04, 10 March 2024
  • Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
    ...ttern information such as loop bounds and strides) ''throughout the memory system''. To this end, we are currently extending the AXI4 [3] memory protocol, us A simple demonstrator system building on your extended IPs could also be built.
    3 KB (431 words) - 16:13, 6 November 2022
  • XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
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  • Robert Balas
    ...mbedded systems going through the full stack of hardware design, operating system and hacking the compiler. I'm an avid free software contributor, GNU/Linux
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  • Integration Of A Smart Vision System
    ...ludes them from being used in a portable system. Furthermore, surveillance system typically do not come with any localized intelligence, so their recorded da In this project, a novel, distributed and energy-efficient surveillance system will be brought up and optimized by the student.
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  • Integrating Hardware Accelerators into Snitch (1S)
    ...] and the floating-point repetition (FREP) hardware loop, which allows the system to achieve FPU utilization above 90%. ...ave been historically integrated into the PULP cluster, but a Snitch-based system would greatly benefit by supporting these hardware modules.
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  • Flexfloat DL Training Framework
    ...out a slightly smaller version of Manticore, called Occamy, a two-chiplet system in the near future. Snitch-based architectures are built around the minimal
    4 KB (613 words) - 10:13, 2 November 2022
  • Counter-based Fast Power Estimation using FPGAs (M/1-3S)
    ...ct the activity of the individual functional units and therefore the whole system. They are usually employed to profile applications performance and resource ...xplore.ieee.org/abstract/document/845896 A survey of design techniques for system-level dynamic power management]</div>
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  • Ultrasound based hand gesture recognition
    ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with : 30% system development
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  • Non-blocking Algorithms in Real-Time Operating Systems
    ...on primitives used in FreeRTOS [4] [5], an open-source real-time operating system (RTOS) used by Amazon, and determine how they use critical sections. Turn t
    4 KB (508 words) - 18:59, 10 January 2022
  • Adding Linux Support to our DMA Engine (1-2S/B)
    * '''Research''': Investigate how Linux interacts with a system-level DMA and collect a set of minimal requirements for the hardware.
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  • Real-Time Embedded Systems
    ...ical instant''' at which these results are produced. In fact, a real-time system changes its state as a function of physical time. ...controlled object'' (the ''controlled cluster''), the ''real-time computer system'' (the ''computational cluster'') and the ''human operator'' (the ''operato
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  • A Unified Compute Kernel Library for Snitch (1-2S)
    ...Evaluate the performance of your kernels''' in RTL simulations of a Snitch system
    4 KB (554 words) - 09:49, 17 August 2022
  • Implementing DSP Instructions in Banshee (1S)
    ...ly. For all of these purposes, we heavily use ''Git'' as a version control system at IIS. If you have no previous experience with Git, we ''strongly'' advise
    10 KB (1,428 words) - 13:31, 27 October 2022
  • Streaming Integer Extensions for Snitch (M/1-2S)
    ...to fit our needs, and evaluate their performance benefits of the resulting system. A main goal of this thesis is to create a Snitch-based system which is suitable for the type of embedded/edge applications targeted by th
    6 KB (770 words) - 14:19, 15 September 2022
  • Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    7 KB (804 words) - 19:45, 21 November 2021
  • SCMI Support for Power Controller Subsystem
    ...ower domain, voltage, clock and sensor management through a shared mailbox system with the PCS. [1] [https://developer.arm.com/documentation/den0056/latest Arm System Control and Management Interface]
    3 KB (467 words) - 13:55, 12 October 2022
  • Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
    <!-- Peripheral Event Linking System For Real-Time Capable Energy-Efficient SoCs (M/1-2S) --> ...unities are limited due to the necessity to retain major parts of the main system memory due to the use of static random access memory (SRAM) for code execut
    8 KB (1,127 words) - 19:54, 1 March 2023
  • HW/SW Safety and Security
    [[File:Mcs.png|thumb|350px| A Mixed Criticality System (MCS).]] ...-time computer system is a computer system in which the correctness of the system behavior depends not only on the '''logical results''' of the computations,
    5 KB (614 words) - 09:49, 15 January 2024
  • Low Resolution Neural Networks
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    4 KB (520 words) - 14:52, 24 November 2021
  • Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
    ...ists of an analog front-​end, a data converter, a wireless communication system and a wireless power receiver. ...ze the noise efficiency of the LNA and reduce the power consumption of the system. At the same time, novel wireless power receiver structures should be explo
    3 KB (381 words) - 19:19, 25 November 2021
  • Watchdog Timer for PULP
    ...tware malfunction, the WDT will not be properly serviced, resulting in the system returning to its original state.
    2 KB (337 words) - 08:49, 21 June 2022
  • Self Aware Epilepsy Monitoring
    Epilepsy is a central nervous system disorder in which brain activity becomes abnormal, causing seizures or peri ...implementing a self-aware machine learning model to be used in a wearable system for real-time detection of epileptic seizures.
    2 KB (298 words) - 15:25, 23 October 2023
  • Wireless EEG Acquisition and Processing
    ...Mr. Wolf multicore processor on board. The project’s goal is to design a system capable of acquiring reliable EEG signals during motion, transmitting them
    3 KB (369 words) - 15:04, 20 July 2023
  • PULP’s CLIC extensions for fast interrupt handling
    ...ding environment, for example external master devices interacting with the system through I/O peripheral interfaces. This means that the underlying HW has to
    4 KB (515 words) - 15:06, 5 August 2022
  • Fast Accelerator Context Switch for PULP
    ...ization capabilities to the cluster of ControlPULP, allowing the operating system to schedule several accelerator tasks and let them run concurrently. This a * Evaluate the resulting system in RTL simulation and/or on the FPGA, for which a mature implementation of
    6 KB (835 words) - 16:27, 7 July 2023
  • Development of a fingertip blood pressure sensor
    [[Category:Biomedical System on Chips]]
    4 KB (535 words) - 16:56, 12 July 2022
  • Smart e-glasses for concealed recording of EEG signals
    : 25% System assembly design : 25% embedded system programming
    3 KB (410 words) - 19:02, 6 December 2023
  • Advanced EEG glasses
    : 25% System assembly design : 25% embedded system programming
    3 KB (420 words) - 19:01, 6 December 2023
  • Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
    ...with the obstacles. Furthermore, to further extend the capabilities of the system, you will have to implement a path planning solution that optimally drives
    4 KB (604 words) - 14:07, 10 March 2022
  • Triple-Core PULPissimo
    ...ability of signal spikes being captured by sequential elements, taking the system into a faulty state. While some fault tolerance schemes utilize Triple Modu
    2 KB (311 words) - 08:49, 21 June 2022
  • ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
    ...t. This new approach will be simulated in MATLAB for a mmWave massive MIMO system and the optimal number format parameters are chosen. Then, a matrix-vector The ideas of this project can be extended to other system blocks such as the beamspace FFT, so that these blocks generate their outpu
    5 KB (662 words) - 17:14, 26 September 2023
  • Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication
    ...li. The project also includes MATLAB simulations for a mmWave massive MIMO system with channels generated by QuadRiGa [8] or from a commercial raytracing cha
    5 KB (771 words) - 16:32, 8 February 2022
  • VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM
    ...y QuadRiGa [8] or from a commercial ray-tracing simulator, we will explore system-level aspects such as the possibility of reusing the equalization matrix ac
    6 KB (843 words) - 17:16, 26 September 2023
  • Passive Radar for UAV Detection using Machine Learning
    ...with the goal of verifying the effectiveness and practicability of such a system, which will answer the question of whether reliable UAV detection is indeed : 20% System-level simulation
    5 KB (564 words) - 16:12, 9 February 2022
  • Through Wall Radar Imaging using Machine Learning
    : 20% System-level simulation [[Category:System on Chips for IoTs]]
    5 KB (586 words) - 16:15, 9 February 2022
  • Improved Collision Avoidance for Nano-drones
    [[File:ToFDrone_dpalossi.png|thumb|right|500px|Overview of the cyber-physical system.]] ...latform is the Bitcraze Crazyflie 2.1 [4] extended by a powerful multicore System-on-Chip (SoC), the parallel ultra-low power (PULP) GAP8 [5] aboard the AI-d
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  • Bridging QuantLab with LPDNN
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    7 KB (831 words) - 19:36, 12 January 2023
  • Exploring NAS spaces with C-BRED
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    6 KB (839 words) - 14:08, 15 February 2024
  • Development of statistics and contention monitoring unit for PULP
    '''Multiprocessor System-on-Chip (MPSoCs)''' are getting more popular in the domain of '''Critical R ...g CPU overload with respect to single-core applications, improving overall system’s performance [2].
    6 KB (869 words) - 14:47, 7 July 2023
  • Ultrasound Doppler system development
    ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. The velocity of liquid flows (as for arteries and veins) can be measured b Preliminary results of custom syringe pump system:
    3 KB (363 words) - 17:18, 3 May 2024
  • Low-Power Time Synchronization for IoT Applications
    : 50% Asynchronous VLSI design with System Verilog
    1 KB (138 words) - 13:34, 25 May 2022
  • GRAND Hardware Implementation
    ...n efficient hardware architecture. The HDL implementation can be done with System Verilog. Then a synthesis must be carried out as well as the backend routin
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  • Low-Complexity MIMO Detection
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    4 KB (503 words) - 13:54, 30 May 2022
  • Forward error-correction ASIC using GRAND
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    4 KB (470 words) - 18:16, 27 May 2022
  • Low-power time synchronization for IoT applications
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    4 KB (492 words) - 10:55, 16 June 2022
  • Quantum Transport Modeling of Interband Cascade Lasers (ICL)
    ...is to simulate interband cascade lasers based on the InAs-GaInSb material system with an in-house quantum transport solver called OMEN and to determine thei
    3 KB (365 words) - 10:19, 31 May 2022
  • Weak-strong massive MIMO communication with low-resolution ADCs
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (662 words) - 13:33, 10 May 2023
  • Improving datarate and efficiency of ultra low power wearable ultrasound
    ...ept of the existing ULP probe, we aim to replace the BLE link with a Spark system. To this end, the student will start working with evaluation boards, replac
    3 KB (366 words) - 15:10, 23 October 2023
  • Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
    The power consumption of a system usually is the most difficult figure of merit to acquire, as it usually has
    2 KB (282 words) - 09:27, 3 November 2023
  • Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
    .... So far we have verified the unit's correctness using a simple file-based System-Verilog testbench. * Simulates a more realistic memory system (multiple memories, complex latency pattern, reordering, ...)
    2 KB (226 words) - 14:22, 27 February 2024
  • Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
    At ETH, we developed our own many-core system called MemPool. It boasts 256 lightweight 32-bit Snitch cores. They impleme ...d to integrate an FLL, a boot ROM, and a JTAG to access and initialize the system. While there are many IPs and know-how at IIS for that, this is also highly
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  • Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (586 words) - 15:34, 11 July 2022
  • Event-based navigation on autonomous nano-drones
    ...to run on a novel ultra-low-power processor, such as the PULP Kraken [3,4] System-on-Chip (SoC). At the same time, the candidate will also work on the hardwa
    4 KB (505 words) - 18:25, 26 July 2022
  • Towards Formal Verification of the iDMA Engine (1-3S/B)
    .... So far we have verified the unit's correctness using a simple file-based System-Verilog testbench.
    2 KB (272 words) - 10:21, 3 November 2023
  • Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
    ...osition unit that transposes matrices while they are copied throughout the system. The accelerator should work of full-precision integer and floating point f
    2 KB (214 words) - 09:39, 23 August 2023
  • Zephyr RTOS on PULP
    ...l). Among these, Zephyr OS [1] is a promising scalable real-time operating system with small memory footprint designed for resource-constrained systems follo ...required to be able to track and set the operating point of the controlled system in a workload-aware manner.
    3 KB (483 words) - 15:28, 19 February 2024
  • PULP Freertos with LLVM
    ...required to be able to track and set the operating point of the controlled system in a workload-aware manner. Currently, we support FreeRTOS [5] in ControlPULP as real-time operating system using our custom compiler toolchain based on GCC [3] which supports various
    3 KB (438 words) - 16:51, 5 August 2022
  • Running Rust on PULP
    [https://www.rust-lang.org/ Rust] is a new, system-level general-purpose programming language fully compatible with C, incorpo * Interest in low-level programming of a manycore system
    2 KB (311 words) - 14:14, 29 June 2023
  • Implementing Configurable Dual-Core Redundancy
    At ETH, we are developing our own many-core system called MemPool [[#ref-Cavalcante2020|&#91;2&#93;]], [[#ref-Riedel2021|&#91;
    4 KB (497 words) - 14:15, 29 June 2023
  • Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
    WP3: System Development and HW Extension (8 weeks, November-December) System and method for an optimized Winograd convolution accelerator
    4 KB (549 words) - 11:35, 3 November 2023
  • MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
    [[Category:Computer and System Architecture]] ...controller called x-heep, which shares most of the IPs with the ETH's PULP system.
    8 KB (1,304 words) - 14:44, 23 October 2023
  • A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
    * Strong interest system design and hardware/software interaction
    3 KB (416 words) - 10:49, 25 January 2024
  • Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
    * Experience with the System Verilog language, VLSI 1
    2 KB (308 words) - 14:30, 8 March 2023
  • Design of combined Ultrasound and PPG systems
    ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with [[Category:System Design]]
    3 KB (354 words) - 19:02, 6 December 2023
  • Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
    ...ed Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1M) --> ...ople.ee.ethz.ch/~janniss/projects/Maddness_system_integration.pdf Maddness System Intergration]
    6 KB (846 words) - 16:50, 3 November 2022
  • Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
    ...ed Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1M) -->
    6 KB (823 words) - 16:32, 3 November 2022
  • Alias-Free Oscillator Synchronization for Arbitrary Waveforms
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (577 words) - 09:48, 5 October 2022
  • Extended Verification for Ara
    * Empirically, by running more complex benchmarks and programs on the Ara system.
    5 KB (665 words) - 14:19, 18 October 2022
  • Virtual Memory Ara
    ...e runs only in bare-metal mode and is not designed to support an Operating System. This is a shame since the scalar RV64GC core CVA6 does support it! ...s for easy porting of many external programs and drastically increases the system's usability.
    5 KB (769 words) - 11:38, 3 November 2023
  • Audio Visual Speech Separation and Recognition (1S/1M)
    ...er(s) with the transcript of their respective speech. Lastly, the proposed system must abide by the TinyML[[#ref-reddi2020|&#91;5&#93;]] constraints consider
    11 KB (1,467 words) - 14:15, 1 March 2024
  • Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
    Occamy is a massively-parallel multiprocessor system-on-chip (MPSoC) designed for energy-efficient high-performance computing (H
    7 KB (944 words) - 10:47, 25 January 2024
  • Runtime partitioning of L1 memory in Mempool (M)
    ...L1 data-memory. Leveraging its hierarchical architecture, we can scale the system to TeraPool, a cluster of 1024 Snitch cores, having 4096 banks of shared me
    3 KB (490 words) - 10:38, 2 November 2023
  • Radiation Testing of a PULP ASIC
    ...ame room. As access to the room will be limited during the experiment, the system should be designed to allow us to sample as much data as possible during th * 30% System design
    3 KB (454 words) - 14:59, 25 October 2023
  • Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
    * to have a synthesizable fully configurable memory system. * to monitor key figures of merit online and in-system.
    2 KB (335 words) - 13:58, 27 October 2022
  • AXI-based Network on Chip (NoC) system
    <!-- AXI-based Network on Chip (NoC) system --> ...ould be to build a system with a mesh NoC and a couple of cores and do the system integration for a potential tapeout. For the verification, low-level softwa
    2 KB (252 words) - 14:43, 23 October 2023
  • All the flavours of FFT on MemPool (1-2S/B)
    ...L1 data-memory. Leveraging its hierarchical architecture, we can scale the system to TeraPool, a cluster of 1024 Snitch cores, having 4096 banks of shared me
    3 KB (460 words) - 18:54, 9 November 2022
  • Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
    ...chmark, optimize, and improve your testbenches simulating a large manycore system running real machine learning workloads (or booting Linux!). * 20% Benchmark and optimize the simulation speed of a large manycore system.
    2 KB (290 words) - 09:38, 3 November 2023
  • Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
    * 30% Verification and evaluation OOC and in-system
    2 KB (249 words) - 09:36, 3 November 2023
  • Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
    ...ce the model's memory footprint and open new opportunities to increase the system's energy efficiency.
    2 KB (307 words) - 18:20, 3 November 2023
  • Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
    ...ostructure and its influence on the (quantum) transport properties of this system
    2 KB (302 words) - 18:47, 10 November 2022
  • Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
    ...d Spatz on the TeraPool architecture as our hardware platform, a scaled-up system from MemPool [[#ref-Cavalcante2020|&#91;2&#93;]], which has 1024 Snitch cor ...r utilization, aiming to extract the maximum possible performance from the system.
    6 KB (775 words) - 11:57, 31 October 2023
  • Resource Partitioning of RPC DRAM
    ...ler to improve predicatability of memory accesses. For example, Arm Memory System Resource Partitioning and Monitoring (MPAM)[5] is a recent example of such <div> [5] “Arm Memory System Resource Partitioning and Monitoring (MPAM)” https://developer.arm.com/do
    3 KB (379 words) - 09:32, 15 January 2024
  • Resource Partitioning of Caches
    ...last-level cache (LLC) [4]. The strategy we are using is to make the whole system more predictable is resource partitioning. Specifically, partitioning the c
    3 KB (347 words) - 14:07, 4 March 2024
  • Implementation of a Coherent Application-Class Multicore System (1-2S)
    ...n technique is to combine multiple instances of a core to a ''multi-core'' system. This technique introduces a new challenge: Each core keeps its own copy of ...ane cores. Throughout this project, the feasibility and performance of the system shall be evaluated.
    2 KB (260 words) - 16:41, 15 November 2022
  • Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
    ...the voter detects discrepancy in the results, it alerts the system that a system failure happened and recovery or reset procedures must be initiated.
    5 KB (752 words) - 13:23, 24 October 2023
  • Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
    ...reconfigurable vector processor cluster to optimize area footprint of the system; * Benchmark the system on the previously identified application and perform additional optimizatio
    5 KB (651 words) - 20:42, 22 November 2022
  • Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
    * Integrate the IP into a full SoC system through an AXI-based DMA controller; * Interest in deepening system I/O communication topics
    5 KB (631 words) - 09:28, 3 November 2023
  • Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
    * Integrate the peripheral into a full SoC system; * Interest in deepening system I/O communication topics
    4 KB (554 words) - 09:28, 3 November 2023
  • Neural Recording Interface and Signal Processing
    ...es attracts more attentions. A better understanding of the brain and neuro system is needed. Since the number of electrophysiological signals generated by ne
    3 KB (466 words) - 10:26, 21 February 2024
  • Design of low mismatch DAC used for VAD
    Voice activity detection (VAD) is a hot topic in nowadays IoT system that can be used for keyword spotting, speech recognition and audio recordi
    1 KB (191 words) - 17:04, 24 January 2023
  • High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
    ...including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GH ...sumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with t
    3 KB (369 words) - 14:29, 25 January 2023
  • Noise Figure Measurement for Cryogenic System
    ...Qubits will be read-out at the same time. For discrete Qubits, the readout system usually works at the sub-1 GHz frequency range. However, for a compact foot
    2 KB (372 words) - 10:32, 14 February 2023
  • Super Resolution Radar/Imaging at mm-Wave frequencies
    ...and drive the theoretical approach of using phased array as a super radar system. Also, based on the candidate progress, the project will involve validation
    2 KB (326 words) - 11:44, 14 February 2023
  • High resolution, low power Sigma Delta ADC
    This project explores the CTSD ADC from system level up to layout to be able to reach ENOB >= 10 bits with small power and
    2 KB (223 words) - 11:29, 14 February 2023
  • Integrated Devices, Electronics, And Systems
    ...s of 5G/6G communications and sensing through high performance circuit and system designs. We are particularly interested in systems with wide bandwidth, hi
    1 KB (145 words) - 16:26, 27 September 2023
  • Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
    Epilepsy is a central nervous system disorder characterized by abnormal brain activity, causing seizures or peri ...ilst not forgetting the properties of previous users that might re-use the system; thus, our model must mitigate the "catastrophic forgetting" phenomenon.
    8 KB (1,271 words) - 15:04, 20 July 2023
  • Audio Visual Speech Separation (1S/1M)
    ...er(s) with the transcript of their respective speech. Lastly, the proposed system must abide by the TinyML[[#ref-reddi2020|&#91;5&#93;]] constraints consider
    9 KB (1,283 words) - 17:44, 1 September 2023
  • A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
    ...ticast support directly into the interconnect of a shared-memory many-core system called Occamy [4]. In Occamy, 216+1 cores and their tightly-coupled data me [4] [https://pulp-platform.org/occamy/ Occamy many-core chiplet system] <br />
    8 KB (1,177 words) - 11:45, 13 March 2024
  • Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
    ...ed.png|450px|thumb|right|The envisioned high-performance multimodal vision system]] ...s of new possibilities for AI and tinyML. We are creating a completely new system, with an autonomous base station and distributed smart sensor nodes to run
    4 KB (572 words) - 11:07, 5 December 2023
  • Design of a Low Power Smart Sensing Multi-modal Vision Platform
    ...s of new possibilities for AI and tinyML. We are creating a completely new system, with an autonomous base station and distributed smart sensor nodes to run ...ng Projects]] [[Category:EmbeddedAI]] [[Category:SmartSensors]] [[Category:System Design]] [[Category:2023]] [[Category:Semester Thesis]] [[Category:Master T
    4 KB (553 words) - 11:02, 5 December 2023
  • Object Detection and Tracking on the Edge
    ...s of new possibilities for AI and tinyML. We are creating a completely new system, with an autonomous base station and distributed smart sensor nodes to run ...ng Projects]] [[Category:EmbeddedAI]] [[Category:SmartSensors]] [[Category:System Design]] [[Category:2023]] [[Category:Semester Thesis]] [[Category:Master T
    4 KB (523 words) - 10:55, 5 December 2023
  • Artificial Reverberation for Embedded Systems
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (578 words) - 12:39, 14 June 2023
  • On-Board Software for PULP on a Satellite
    * 10% System design
    3 KB (383 words) - 14:29, 18 February 2024
  • A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
    ...t needs to be accessed and monitored calls for a high-speed FPGA/GPU based system with a compact, and incubator-compatible hardware design. [[Image:Hangxing FPGA.png|800px| System Overview]]
    6 KB (720 words) - 16:27, 27 September 2023
  • Real-time Linux on RISC-V
    ...e that is non-preemptible'' which translates directly into a more reactive system. The core algorithms and data structures that are changed are the timer, in
    3 KB (460 words) - 15:29, 19 February 2024
  • Wireless In Action Data Streaming in Ski Jumping (1 B/S)
    ...ta. To improve modern feedback methods in ski jumping, we aim to develop a system that collects athlete performance data with a body-worn sensor node and tra ...with real ski jumpers) shall demonstrate the performance of the developed system. According to the level of the student and the chosen thesis type (BT/ST) t
    6 KB (688 words) - 12:15, 23 July 2023
  • Cycle-Accurate Event-Based Simulation of Snitch Core
    ...ly. For all of these purposes, we heavily use ''Git'' as a version control system at IIS. If you have no previous experience with Git, we ''strongly'' advise [[Category:System on Chips for IoTs]]
    14 KB (2,018 words) - 22:54, 23 November 2023
  • Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
    ...l motor control during action is difficult. Therefore, we aim to develop a system that translates sensor data into simple, motor-transferable information onl [[Category:System on Chips for IoTs]]
    6 KB (735 words) - 12:15, 23 July 2023
  • Towards Flexible and Printable Wearables
    * 34% System design and implementation ...ng Projects]] [[Category:EmbeddedAI]] [[Category:SmartSensors]] [[Category:System Design]] [[Category:2023]] [[Category:Semester Thesis]] [[Category:Bachelor
    5 KB (574 words) - 13:06, 20 July 2023
  • Testbed Design for Self-sustainable IoT Sensors
    ...ng Projects]] [[Category:EmbeddedAI]] [[Category:SmartSensors]] [[Category:System Design]] [[Category:2023]] [[Category:Semester Thesis]] [[Category:Bachelor
    3 KB (356 words) - 13:03, 20 July 2023
  • On - Device Continual Learning for Seizure Detection on GAP9
    Epilepsy, a central nervous system disorder, is characterized by abnormal brain activity resulting in seizures ...user without forgetting the properties of prior users who might reuse the system. This necessitates mitigating the "catastrophic forgetting" phenomenon in o
    9 KB (1,326 words) - 11:16, 12 October 2023
  • Extending our FPU with Internal High-Precision Accumulation (M)
    ...s the model's memory footprint and opens new opportunities to increase the system's energy efficiency. For these reasons, many commercial platforms already p
    2 KB (341 words) - 15:54, 15 February 2024

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