Category:Completed
From iis-projects
These projects have already been completed. You can take a look at the results of the project and learn more.
Contents
Analog
2015
No pages meet these criteria.
2014
No pages meet these criteria.
2013
- Wireless Biomedical Signal Acquisition Device
- Flexible Front-End Circuit for Biomedical Data Acquisition
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
2012
- Data Mapping for Unreliable Memories
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- High Throughput Turbo Decoder Design
- Turbo Decoder Design for High Code Rates
- Channel Decoding for TD-HSPA
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- Successive Interference Cancellation for 3G Downlink
- Channel Estimation for TD-HSPA
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- MatPHY: An Open-Source Physical Layer Development Framework
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- High Performance Cellular Receivers in Very Advanced CMOS
- Multi-Band Receiver Design for LTE Mobile Communication
- High-Resolution, Calibrated Folding ADCs
Digital
2015
- Hardware Accelerated Derivative Pricing
- Glitches Reduce Listening Time of Your iPod
- FFT-based Convolutional Network Accelerator
- Real-Time Optical Flow Using Neural Networks
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Vector Processor for In-Memory Computing
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Hardware/software co-programming on the Parallella platform
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Real-Time Stereo to Multiview Conversion
2014
- EvalEDGE: A 2G Cellular Transceiver FMC
- Real-Time Stereo to Multiview Conversion
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
2012
- A Multiview Synthesis Core in 65 nm CMOS
- Real-time View Synthesis using Image Domain Warping
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
Nano Electronics
2015
No pages meet these criteria.
2014
No pages meet these criteria.
2013
No pages meet these criteria.
2012
No pages meet these criteria.
Nano TCAD
2015
No pages meet these criteria.
2014
No pages meet these criteria.
2013
No pages meet these criteria.
2012
No pages meet these criteria.
Pages in category "Completed"
The following 68 pages are in this category, out of 282 total.
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- A computational memory unit using phase-change memory devices
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- A Recurrent Neural Network Speech Recognition Chip
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- A Trustworthy Three-Factor Authentication System
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for HPC monitoring
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Active-Set QP Solver on FPGA
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced 5G Repetition Combining
- Aliasing-Free Wavetable Music Synthesizer
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Analog Compute-in-Memory Accelerator Interface and Integration
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASIC Implementation of Jammer Mitigation
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autonomous Sensing For Trains In The IoT Era
B
- Bandwidth Efficient NEureka
- Baseband Meets CPU
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Bluetooth Low Energy receiver in 65nm CMOS
- Bridging QuantLab with LPDNN
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
C
- Cell-Free mmWave Massive MIMO Communication
- Change-based Evaluation of Convolutional Neural Networks
- Channel Decoding for TD-HSPA
- Channel Estimation for TD-HSPA
- Charging System for Implantable Electronics
- CLIC for the CVA6
- CMOS power amplifier for field measurements in MRI systems
- Compressed Sensing Reconstruction on FPGA
- Compression of Ultrasound data on FPGA
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a HDMI Video Interface for PULP
D
- Data Mapping for Unreliable Memories
- DC-DC Buck converter in 65nm CMOS
- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning for Brain-Computer Interface
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and Implementation of ultra low power vision system
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip