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• Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
  ...itional, high-resolution cameras. The student will use a cutting-edge high-performance embedded GPU to acquire data from these devices and run sensor-fusion based ...egory:Master Thesis]] [[Category:Bachelor Thesis]] [[Category:Event-Driven Computing]] [[Category:Hot]]
  2 KB (349 words) - 15:53, 11 October 2021
• Graph neural networks for epileptic seizure detection
  ...ning graphs with convolutional networks (GCNs), achieving state-of-the-art performance in public datasets [13].[14] proposed a temporal GCN to tackle the task of 1 - Development in a high-level programming language (python) of graph neural networks and/or convolu
  10 KB (1,306 words) - 19:58, 10 March 2024
• Huawei Research
  ===About the Huawei Future Computing Laboratory=== ...research laboratory focused on fundamental research in the area of future computing systems (new hardware, new software, new algorithms).
  6 KB (799 words) - 11:11, 1 August 2022
• Spiking Neural Network for Motor Function Decoding Based on Neural Dust
  ...t al., “Real-time brain-machine interface in non-human primates achieves high-velocity prosthetic finger movements using a shallow feedforward neural net
  5 KB (662 words) - 20:05, 10 March 2024
• Fast Simulation of Manycore Systems (1S)
  [[Category:High Performance SoCs]] In a quest for high-performance computing systems, few architectural models retain the flexibility of manycore system
  10 KB (1,434 words) - 17:20, 2 August 2021
• Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
  ...f time-encoded SNNs to high-level system simulations in a high-performance computing framework. It also involves interactions with several researchers across IB ...or level and/or digital design with VHDL). Prior knowledge of neuromorphic computing concepts is a bonus but not necessary.
  3 KB (360 words) - 10:54, 31 August 2021
• Universal Stream Semantic Registers for Snitch (1S)
  [[Category:High Performance SoCs]] ...e handling such streams in hardware. This frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also ''de
  3 KB (425 words) - 17:32, 17 November 2021
• Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
  [[Category:High Performance SoCs]] ...e handling such streams in hardware. This frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also ''de
  4 KB (557 words) - 16:14, 6 November 2022
• Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  ...cision network to an appropriate representation and apply to it a suitable computing paradigm. ...gher precision. Our goal is therefore to keep this overhead of the sparse, high-precision part of the layer as small as possible and reach an optimal trade
  3 KB (497 words) - 22:15, 23 November 2022
• Mixed-Precision Neural Networks for Brain-Computer Interface Applications
  ...s. However, the deployed networks have so far all been run at a relatively high numerical precision of 8 bits. ...er a simulation or the physical Kraken chip - see references) and evaluate performance compared to the 8-bit baseline
  8 KB (1,101 words) - 20:04, 10 March 2024
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  [[Category:High Performance SoCs]] ...hardware, which brings many benefits: it frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also deco
  3 KB (431 words) - 16:13, 6 November 2022
• XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
  ...ss communication, in which massive amounts of data need to be processed at high rates. [[Category:Event-Driven Computing]]
  7 KB (933 words) - 19:29, 21 November 2021
• Integration Of A Smart Vision System
  ...activity in their field of view, they send an alarm to a centralized high-performance vision platform, which is able to pan, tilt and zoom its field of view to t ...egory:Master Thesis]] [[Category:Bachelor Thesis]] [[Category:Event-Driven Computing]] [[Category:Hot]]
  3 KB (433 words) - 15:36, 4 August 2022
• Integrating Hardware Accelerators into Snitch (1S)
  ...with a large double-precision floating-point unit (FPU) optimized for high-performance. Additionally, Snitch features two custom instruction-set-architecture (ISA
  4 KB (567 words) - 13:57, 7 September 2022
• Counter-based Fast Power Estimation using FPGAs (M/1-3S)
  [[Category:High Performance SoCs]] On the other hand, modern computing systems feature a number of ''performance counters'', i.e. hardware registers tracking carefully selected countable e
  5 KB (688 words) - 13:51, 27 October 2022
• Non-blocking Algorithms in Real-Time Operating Systems
  ...hardware and provide features such as efficient interrupt nesting to allow high priority interrupts to get the highest attention. On the software-level you Measure the performance impact, interrupt latency and jitter.
  4 KB (508 words) - 18:59, 10 January 2022
• Implementing DSP Instructions in Banshee (1S)
  [[Category:High Performance SoCs]] In a quest for high-performance computing systems, few architectural models retain the flexibility of manycore system
  10 KB (1,428 words) - 13:31, 27 October 2022
• SCMI Support for Power Controller Subsystem
  Today’s High Performance Computing (HPC) systems are complex architectures requiring on-chip dedicated HW reso ...explore.ieee.org/document/8065010 Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster]
  3 KB (467 words) - 13:55, 12 October 2022
• Serverless Benchmarks on RISC-V (M)
  [[Category:High Performance SoCs]] ...ior of these microservices/functions has been shown to have very different performance characteristics from traditional monolithic applications. For example, a sh
  6 KB (905 words) - 21:41, 6 December 2021
• Enhancing our DMA Engine with Fault Tolerance
  At IIS we are developing a modular and extensible high-performance direct memory access (DMA) engine. This DMA is integrated into a variety of ...le to runtime faults (SEUs), especially when deployed in environments with high levels of radiation, such as space. To combat this, a variety of redundancy
  2 KB (348 words) - 13:16, 24 October 2023
• Fast Accelerator Context Switch for PULP
  ...extensions targeting energy-efficient digital signal processing [2]. This computing cluster serves as an accelerator. ...stem (PCS) dynamically adjusting the operating point of a High Performance Computing (HPC) processor to meet energy, power, and thermal constraints.
  6 KB (835 words) - 16:27, 7 July 2023
• Exploring NAS spaces with C-BRED
  ...s are usually designed to be large to increase the likelihood of including high-quality networks, i.e., better than sibling candidates. A possible alternative is restricting the search to sub-spaces containing high-quality networks.
  6 KB (839 words) - 14:08, 15 February 2024
• Low-Complexity MIMO Detection
  [[File:Low_complexity_mimo_bs6-crop.png|500px|thumb|High performance low-complexity iterative MIMO receiver.]] ...to implement a low complexity MIMO detection algorithm and to optimize its performance with state-of-the-art machine learning methods. Therefore, a novel 5G-compl
  4 KB (503 words) - 13:54, 30 May 2022
• Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
  [[Category:High Performance SoCs]] ...s is an important operation used in countless applications from scientific computing to machine learning workloads.
  2 KB (214 words) - 09:39, 23 August 2023
• Optimizing the Pipeline in our Floating Point Architectures (1S)
  [[Category:High Performance SoCs]] ...fundamental for a large set of applications spanning from high-performance computing to neural network training. FP architectures usually show a large critical
  3 KB (380 words) - 14:27, 15 May 2023
• Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
  [[Category:High Performance SoCs]] ...s relative to each grid point [1]. They are widespread in high-performance computing (HPC) and underly various problems in physical simulation, economics, and i
  3 KB (431 words) - 22:29, 19 January 2023
• MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
  [[Category:High Performance Computing]] ...from sensor-monitoring all the way to robotics. Despite typically lower in performance, they are usually preferred over custom circuits and FPGAs thanks to their
  8 KB (1,304 words) - 14:44, 23 October 2023
• Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
  [[Category:High Performance SoCs]] ...-up-table (LUT) and an addition. That can significantly reduce the overall computing and energy needs.
  6 KB (846 words) - 16:50, 3 November 2022
• Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
  [[Category:High Performance SoCs]] ...-up-table (LUT) and an addition. That can significantly reduce the overall computing and energy needs.
  6 KB (823 words) - 16:32, 3 November 2022
• Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
  [[Category:High Performance SoCs]] ...ssor system-on-chip (MPSoC) designed for energy-efficient high-performance computing (HPC) applications. It is a concrete implementation of the concept Manticor
  7 KB (944 words) - 10:47, 25 January 2024
• Runtime partitioning of L1 memory in Mempool (M)
  [[Category:High Performance SoCs]] ...f 1024 Snitch cores, having 4096 banks of shared memory. The huge parallel computing power of TeraPool suits perfectly the purpose of accelerating embarrassingl
  3 KB (490 words) - 10:38, 2 November 2023
• AXI-based Network on Chip (NoC) system
  [[Category:High Performance SoCs]] ...on a single chip is rapidly growing, there is a rising need for scalable, high-bandwidth, and low-latency on-chip communication fabrics. This need is ofte
  2 KB (252 words) - 14:43, 23 October 2023
• All the flavours of FFT on MemPool (1-2S/B)
  [[Category:High Performance SoCs]] ...f 1024 Snitch cores, having 4096 banks of shared memory. The huge parallel computing power and the small latency cost of the shared memory accesses in TeraPool
  3 KB (460 words) - 18:54, 9 November 2022
• Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
  <!-- Creating Towards a High-performance Open-source Verification Suite for AXI-based Systems (1-3S/B) --> [[Category:High Performance SoCs]]
  2 KB (290 words) - 09:38, 3 November 2023
• Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
  [[Category:High Performance SoCs]] ...the RISC-V vector extension specification is introduced for efficiency and performance improvement. Spatz lean Processing Element (PE) acts as an accelerator to a
  6 KB (775 words) - 11:57, 31 October 2023
• Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
  [[Category:High Performance SoCs]] ...d supercomputing to industrial automation and avionics, including embedded computing products that nowadays feature at least one Ethernet interface. Ethernet st
  5 KB (631 words) - 09:28, 3 November 2023
• Noise Figure Measurement for Cryogenic System
  ...tire qubits readout system. It needs to provide ultra-low noise figure and high gain to ensure readout signal fidelity. Additionally, broadband operation i However, it is not trivial to set up cryogenic environment for high frequency (GHz) measurement since the device under test (DUT) will be isola
  2 KB (372 words) - 10:32, 14 February 2023
• Integrated Devices, Electronics, And Systems
  ...m designs. We are particularly interested in systems with wide bandwidth, high energy-​efficiency, low latency, and security. ...tegrated circuits and systems to address new applications, such as quantum computing, quantum sensing, and electronics-​photonics integration.
  1 KB (145 words) - 16:26, 27 September 2023
• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
  [[Category:High Performance SoCs]] To realize the performance potential of many-core
  8 KB (1,177 words) - 11:45, 13 March 2024
• Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
  [[Category:High Performance SoCs]] ...fundamental for a large set of applications spanning from high-performance computing to neural network training. A flexible highly-parametrized open-source floa
  2 KB (307 words) - 15:40, 15 February 2024
• Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
  <!-- High-performance Multimodal Computer-Vision Systems --> ...ibuted-multi-modal-vision-systed.png|450px|thumb|right|The envisioned high-performance multimodal vision system]]
  4 KB (572 words) - 11:07, 5 December 2023
• Federico Villani
  At IIS, Federico is working ultrasound systems and building a high performance ultrasound research platform. * High-Performance computing
  834 bytes (98 words) - 18:30, 8 November 2023
• Wireless In Action Data Streaming in Ski Jumping (1 B/S)
  ...k methods in ski jumping, we aim to develop a system that collects athlete performance data with a body-worn sensor node and transmits the information to the coac ...way. Field measurements (also with real ski jumpers) shall demonstrate the performance of the developed system. According to the level of the student and the chos
  6 KB (688 words) - 12:15, 23 July 2023
• Cycle-Accurate Event-Based Simulation of Snitch Core
  ...become a crucial asset for exploring SoC architectures. In this scenario, high-level simulators play an essential role in breaking the speed and design ef * Easy calibration of platform parameters for accurate performance estimation
  14 KB (2,018 words) - 22:54, 23 November 2023
• A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
  [[Category:High Performance SoCs]] ...many complex applications and take up a large fraction of high-performance computing (HPC) cycles today. They fall in the category of embarassingly parallel com
  7 KB (960 words) - 14:25, 2 May 2024
• Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
  [[Category:High Performance SoCs]] ...programming model [2] based on PULP [3] for energy-efficient flexible high-performance in-network packet processing. So far we have used the traditional PULP clus
  3 KB (374 words) - 10:24, 3 November 2023
• Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
  [[Category:High Performance SoCs]] ...core of many crucial workloads for modern computing, including scientific computing and deep learning. Finding optimal ways to schedule and parallelize GEMM is
  6 KB (848 words) - 14:25, 2 May 2024
• Network-off-Chip (M)
  As the demand for High-Performance Computing (HPC) systems continues to increase, traditional on-chip communication netw ...virtual channels that can be sent off-chip while achieving low latency and high throughput and energy efficiency.
  4 KB (586 words) - 14:27, 24 October 2023
• 3D Matrix Multiplication Unit for ITA (1S)
  ...dware acceleration of transformer models poses new challenges due to their high arithmetic intensities, large memory requirements, and complex dataflow dep ...rallelism of attention mechanism and 8-bit integer quantization to improve performance and energy efficiency. To maximize ITA’s energy efficiency, we focus on m
  3 KB (485 words) - 10:52, 12 December 2023
• Efficient collective communications in FlooNoC (1M)
  [[Category:High Performance SoCs]] To realize the performance potential of many-core
  6 KB (897 words) - 19:52, 22 February 2024

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