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Showing below up to 50 results in range #201 to #250.
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- DaCe on Snitch
- Data Augmentation Techniques in Biosignal Classification
- Data Mapping for Unreliable Memories
- David J. Mack
- Deconvolution Accelerator for On-Chip Semi-Supervised Learning
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Deep Learning Projects
- Deep Learning for Brain-Computer Interface
- Deep Unfolding of Iterative Optimization Algorithms
- Deep neural networks for seizure detection
- Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- Design Review
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design and Implementation of a multi-mode multi-master I2C peripheral
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of ultra low power vision system
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design and implementation of the front-end for a portable ionizing radiation detector
- Design of Charge-Pump PLL in 22nm for 5G communication applications
- Design of MEMs Sensor Interface
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- Design of Scalable Event-driven Neural-Recording Digital Interface
- Design of State Retentive Flip-Flops
- Design of Streaming Data Platform for High-Speed ADC Data
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a D-Band Variable Gain Amplifier for 6G Communication
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
- Design of a Fused Multiply Add Floating Point Unit
- Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)
- Design of a VLIW processor architecture based on RISC-V
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of an LTE Module for the Internet of Things
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
