Difference between revisions of "Category:FPGA"
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* Develop your architecture using Hardware Description Languages (HDL) such as Verilog or VHDL | * Develop your architecture using Hardware Description Languages (HDL) such as Verilog or VHDL | ||
* Run your system on the development board and collect the results. | * Run your system on the development board and collect the results. | ||
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| + | ==Available Projects== | ||
| + | <DynamicPageList> | ||
| + | suppresserrors = true | ||
| + | category = Available | ||
| + | category = FPGA | ||
| + | </DynamicPageList> | ||
| + | ==Projects in Progress== | ||
| + | <DynamicPageList> | ||
| + | suppresserrors = true | ||
| + | category = In progress | ||
| + | category = FPGA | ||
| + | suppresserrors=true | ||
| + | </DynamicPageList> | ||
| + | ==Completed Projects== | ||
| + | <DynamicPageList> | ||
| + | suppresserrors = true | ||
| + | category = Completed | ||
| + | category = FPGA | ||
| + | suppresserrors=true | ||
| + | </DynamicPageList> | ||
Revision as of 19:10, 10 February 2015
In an FPGA (Field Programmable Gate Array) Project you will be implementing a digital project using a development board that houses a programmable FPGA and a series of peripherals. Such projects allow you to quickly realize prototypes and/or testbeds used to simulate the behavior of large systems. In such a project you will
- Learn how to program the FPGA board
- Understand the different available peripherals on your system board
- Develop your architecture using Hardware Description Languages (HDL) such as Verilog or VHDL
- Run your system on the development board and collect the results.
Available Projects
- Physics is looking for PULP
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- Real-Time Implementation of Quantum State Identification using an FPGA
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Compressed Sensing vs JPEG
Projects in Progress
- ASIC Development of 5G-NR LDPC Decoder
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
Completed Projects
- Precise Ultra-low-power Timer
- Efficient Synchronization of Manycore Systems (M/1S)
- Advanced 5G Repetition Combining
- Next Generation Synchronization Signals
- Transforming MemPool into a CGRA (M)
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Compression of Ultrasound data on FPGA
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- LLVM and DaCe for Snitch (1-2S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Manycore System on FPGA (M/S/G)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Ibex: FPGA Optimizations
- Timing Channel Mitigations for RISC-V Cores
- HERO: TLB Invalidation
- Indoor Positioning with Bluetooth
- Deep Learning for Brain-Computer Interface
- Turbo Equalization for Cellular IoT
- Shared Correlation Accelerator for an RF SoC
- IoT Turbo Decoder
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Efficient NB-IoT Uplink Design
- BigPULP: Multicluster Synchronization Extensions
- Smart Virtual Memory Sharing
- Hardware Accelerated Derivative Pricing
- Internet of Things Network Synchronizer
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- High-speed Scene Labeling on FPGA
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Digital Transmitter for Mobile Communications
- FPGA-Based Digital Frontend for 3G Receivers
- Spatio-Temporal Video Filtering
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- FFT-based Convolutional Network Accelerator
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Vector Processor for In-Memory Computing
Pages in category "FPGA"
The following 100 pages are in this category, out of 100 total.
A
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Active-Set QP Solver on FPGA
- Advanced 5G Repetition Combining
- An FPGA-Based Evaluation Platform for Mobile Communications
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- ASIC Development of 5G-NR LDPC Decoder
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
B
C
- Cell Measurements for the 5G Internet of Things
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Compressed Sensing for Wireless Biosignal Monitoring
- Compressed Sensing vs JPEG
- Compression of Ultrasound data on FPGA
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
D
E
F
H
- Harald Kröll
- Hardware Accelerated Derivative Pricing
- Hardware Accelerator for Model Predictive Controller
- HERO: TLB Invalidation
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High-speed Scene Labeling on FPGA
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Human Intranet
I
- Ibex: FPGA Optimizations
- Image and Video Processing
- Implementation of a NB-IoT Positioning System
- Improved Reacquisition for the 5G Cellular IoT
- Indoor Positioning with Bluetooth
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Internet of Things Network Synchronizer
- IoT Turbo Decoder
L
- LAPACK/BLAS for FPGA
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - CNN-Based-Image-Reconstruction
- LightProbe - Design of a High-Speed Optical Link
- LightProbe - Frontend Firmware and Control Side Channel
- LightProbe - Thermal-Power aware on-head Beamforming
- LLVM and DaCe for Snitch (1-2S)
- LTE IoT Network Synchronization
M
P
- Physics is looking for PULP
- Precise Ultra-low-power Timer
- PULPonFPGA: Hardware L2 Cache
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
R
S
- Sandro Belfanti
- Shared Correlation Accelerator for an RF SoC
- Smart Virtual Memory Sharing
- Spatio-Temporal Video Filtering
- Stefan Lippuner
- Sub-Noise Floor Channel Tracking
- User:Susman
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- System Analysis and VLSI Design of NB-IoT Baseband Processing
