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Showing below up to 100 results in range #51 to #150.

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  1. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration‏‎ (20 revisions)
  2. Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA‏‎ (20 revisions)
  3. Accelerator for Boosted Binary Features‏‎ (20 revisions)
  4. Accelerator for Spatio-Temporal Video Filtering‏‎ (20 revisions)
  5. FFT-based Convolutional Network Accelerator‏‎ (19 revisions)
  6. Trace Debugger for custom RISC-V Core‏‎ (19 revisions)
  7. Wireless Communication Systems for the IoT‏‎ (19 revisions)
  8. PULP’s CLIC extensions for fast interrupt handling‏‎ (19 revisions)
  9. 4th Generation Synchronization‏‎ (19 revisions)
  10. Improving Scene Labeling with Hyperspectral Data‏‎ (18 revisions)
  11. Flexfloat DL Training Framework‏‎ (18 revisions)
  12. Low-Power Environmental Sensing‏‎ (18 revisions)
  13. David J. Mack‏‎ (18 revisions)
  14. ASIC Implementation of High-Throughput Next Generation Turbo Decoders‏‎ (18 revisions)
  15. Mapping Networks on Reconfigurable Binary Engine Accelerator‏‎ (18 revisions)
  16. VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE‏‎ (18 revisions)
  17. Baseband Meets CPU‏‎ (17 revisions)
  18. Energy Efficient AXI Interface to Serial Link Physical Layer‏‎ (17 revisions)
  19. Fast Accelerator Context Switch for PULP‏‎ (17 revisions)
  20. Energy Efficient Circuits and IoT Systems Group‏‎ (17 revisions)
  21. Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs‏‎ (17 revisions)
  22. Compressed Sensing vs JPEG‏‎ (17 revisions)
  23. A Snitch-based Compute Accelerator for HERO‏‎ (17 revisions)
  24. BLISS - Battery-Less Identification System for Security‏‎ (17 revisions)
  25. Streaming Integer Extensions for Snitch (M)‏‎ (17 revisions - redirect page)
  26. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core‏‎ (17 revisions)
  27. Heterogeneous SoCs‏‎ (16 revisions)
  28. Rethinking our Convolutional Network Accelerator Architecture‏‎ (16 revisions)
  29. Wireless In Action Data Streaming in Ski Jumping (1 B/S)‏‎ (16 revisions)
  30. LightProbe‏‎ (16 revisions)
  31. 3D Turbo Decoder ASIC Realization‏‎ (16 revisions)
  32. Optimal System Duty Cycling for a Mobile Health Platform‏‎ (16 revisions)
  33. Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications‏‎ (16 revisions)
  34. Completed‏‎ (15 revisions)
  35. Active-Set QP Solver on FPGA‏‎ (15 revisions)
  36. Vector Processor for In-Memory Computing‏‎ (15 revisions)
  37. Digital Transmitter for Mobile Communications‏‎ (15 revisions)
  38. Elliptic Curve Accelerator for zkSNARKs‏‎ (15 revisions)
  39. Big Data Analytics Benchmarks for Ara‏‎ (15 revisions)
  40. Advanced 5G Repetition Combining‏‎ (15 revisions)
  41. Digital Beamforming for Ultrasound Imaging‏‎ (15 revisions)
  42. DMA Streaming Co-processor‏‎ (15 revisions)
  43. PULP-Shield for Autonomous UAV‏‎ (15 revisions)
  44. Design of an LTE Module for the Internet of Things‏‎ (15 revisions)
  45. Ultra low power wearable ultrasound probe‏‎ (14 revisions)
  46. PULP in space - Fault Tolerant PULP System for Critical Space Applications‏‎ (14 revisions)
  47. Application Specific Frequency Synthesizers (Analog/Digital PLLs)‏‎ (14 revisions)
  48. ASIC Design of a Gaussian Message Passing Processor‏‎ (14 revisions)
  49. Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)‏‎ (14 revisions)
  50. Beamspace processing for 5G mmWave massive MIMO on GPU‏‎ (14 revisions)
  51. HW/SW Safety and Security‏‎ (14 revisions)
  52. Heroino: Design of the next CORE-V Microcontroller‏‎ (14 revisions)
  53. Finite Element Simulations of Transistors for Quantum Computing‏‎ (14 revisions)
  54. Physical Implementation of Ara, PULP's Vector Machine (1-2S)‏‎ (14 revisions)
  55. High-speed Scene Labeling on FPGA‏‎ (14 revisions)
  56. Towards global Brain-Computer Interfaces‏‎ (13 revisions)
  57. Efficient collective communications in FlooNoC (1M)‏‎ (13 revisions)
  58. Deep Learning for Brain-Computer Interface‏‎ (13 revisions)
  59. Turbo Equalization for Cellular IoT‏‎ (13 revisions)
  60. Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)‏‎ (13 revisions)
  61. On-Board Software for PULP on a Satellite‏‎ (13 revisions)
  62. Neural Recording Interface and Signal Processing‏‎ (13 revisions)
  63. CLIC for the CVA6‏‎ (13 revisions)
  64. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT‏‎ (13 revisions)
  65. Level Crossing ADC For a Many Channels Neural Recording Interface‏‎ (13 revisions)
  66. Integrated silicon photonic structures‏‎ (13 revisions)
  67. GUI-developement for an action-cam-based eye tracking device‏‎ (13 revisions)
  68. LAPACK/BLAS for FPGA‏‎ (13 revisions)
  69. Shared Correlation Accelerator for an RF SoC‏‎ (13 revisions)
  70. StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC‏‎ (13 revisions)
  71. On-chip clock synthesizer design and porting‏‎ (13 revisions)
  72. Cycle-Accurate Event-Based Simulation of Snitch Core‏‎ (13 revisions)
  73. Gomeza old project1‏‎ (13 revisions)
  74. Acceleration and Transprecision‏‎ (13 revisions)
  75. A Wireless Sensor Network for a Smart LED Lighting control‏‎ (13 revisions)
  76. Online Learning of User Features (1S)‏‎ (13 revisions)
  77. MatPHY: An Open-Source Physical Layer Development Framework‏‎ (13 revisions)
  78. ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G‏‎ (13 revisions)
  79. ASIC implementation of an interpolation-based wideband massive MIMO detector‏‎ (12 revisions)
  80. Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems‏‎ (12 revisions)
  81. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials‏‎ (12 revisions)
  82. Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems‏‎ (12 revisions)
  83. Stand-Alone Edge Computing with GAP8‏‎ (12 revisions)
  84. Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)‏‎ (12 revisions)
  85. Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex‏‎ (12 revisions)
  86. A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)‏‎ (12 revisions)
  87. PULPonFPGA: Hardware L2 Cache‏‎ (12 revisions)
  88. Deep neural networks for seizure detection‏‎ (12 revisions)
  89. Hardware Accelerators for Lossless Quantized Deep Neural Networks‏‎ (12 revisions)
  90. Sensor Fusion for Rockfall Sensor Node‏‎ (12 revisions)
  91. Ultrasound Doppler system development‏‎ (12 revisions)
  92. Peak-to-average power Reduction‏‎ (12 revisions)
  93. Digital Audio High Level Synthesis for FPGAs‏‎ (12 revisions - redirect page)
  94. Spatio-Temporal Video Filtering‏‎ (12 revisions)
  95. Investigation of Quantization Strategies for Retentive Networks (1S)‏‎ (12 revisions)
  96. BigPULP: Multicluster Synchronization Extensions‏‎ (12 revisions)
  97. Accelerating Matrix Multiplication on a 216-core MPSoC (1M)‏‎ (12 revisions)
  98. Event-Driven Computing‏‎ (12 revisions)
  99. Bridging QuantLab with LPDNN‏‎ (12 revisions)
  100. Event-Driven Convolutional Neural Network Modular Accelerator‏‎ (12 revisions)

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