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• Ultra-low power processor design
  ...hitecture. We will use a state of the art 28nm SOI process to evaluate the performance of the processor. ====Energy Efficient Computing using Multicore Systems====
  10 KB (1,669 words) - 19:01, 30 January 2014
• Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
  ...P TD-HSPA wireless communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect ...the future requires a paradigm shift from the assumption of 100% reliable computing to fault-tolerant
  2 KB (343 words) - 13:56, 9 February 2015
• Digital
  rect 0 0 1300 910 [[High Performance SoCs]] * '''[[High Performance SoCs]]'''
  7 KB (811 words) - 15:21, 23 February 2024
• Acceleration and Transprecision
  ...ccelerators are not limited to high performance sector alone. In low power computing, they allow complex tasks such as computer vision or cryptography to be per
  2 KB (275 words) - 17:05, 24 November 2023
• Ultra-Efficient Visual Classification on Movidius Myriad2
  ...f 12 SHAVE processors, that leverage VLIW and SIMD operations to achieve a high level of energy efficiency. The SHAVE processors share a 2MB tightly couple # Measurement of performance and energy efficiency of the proposed solution
  4 KB (593 words) - 14:57, 30 November 2016
• Covariant Feature Detector on Parallel Ultra Low Power Architecture
  The development of a CV library featuring high level capabilities is key tackling real word problems such as wearable devi ...to operate on a large range of operating voltages, achieving in this way a high level of energy efficiency over a wide range of application workloads.
  4 KB (628 words) - 16:16, 20 February 2018
• FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  ...s able to perform accurate tomographic reconstruction of SoS/AA, providing high-contrast tumor images. In the next months, this technology will be evaluate ...creening procedure in medical trials, we now aim at incorporating portable computing platforms as an add-on to conventional ultrasound systems. This platforms w
  3 KB (411 words) - 14:07, 30 August 2017
• A Wireless Sensor Network for HPC monitoring
  ...ed by wireless links. We want to apply this scenario to a High Performance Computing (HPC) infrastructure for environmental monitoring, aiming at an improving o ...cation (simulations), measuring power-consumption, and assessing detection performance in lab. conditions
  5 KB (617 words) - 16:22, 27 February 2018
• Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. However, even if energy-efficiency is of pr ...en-source ARM-Linux loss-less implementations when available) for the best performance on our application-scenario.
  3 KB (351 words) - 16:19, 27 February 2018
• Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. However, even if energy-efficiency is of pr
  3 KB (394 words) - 16:19, 27 February 2018
• Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. However, even if energy-efficiency is of pr ...d at the node power-supply. Such routing-board will integrate a high-speed high-resolution ADC, which will be controlled by the built-in Programmable Real-
  3 KB (440 words) - 16:15, 1 September 2017
• Open Power-On Chip Controller Study and Integration
  ...re a set of interested partners shares HW and SW IPs to create competitive computing node systems. The power8 CPUs features an interesting power management design where the computing cores are coupled with a dedicated PPC 405 hard real-time core, which imple
  3 KB (462 words) - 15:57, 9 September 2016
• Linux Driver for fine-grain and low overhead access to on-chip performance counters
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. Optimizing for energy efficiency requires m ...ce with external monitors and not with the internal per-core architectural performance counters.
  3 KB (417 words) - 15:55, 9 September 2016
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...at the same time can benefit from the availability of a level of computing performance orders of magnitude better than that of ultra-low power microcontrollers. * [Cassidy13] A. S. Cassidy et al., “Cognitive computing building block: A versatile and efficient digital neuron model for neurosyn
  9 KB (1,427 words) - 18:36, 5 September 2019
• Deep Learning Projects
  ...rties make DNNs an ideal fit for modern SIMD architectures and distributed computing systems. ...each data sample. Hence, to reduce the pressure of DNNs on the underlying computing infrastructure, research in computational deep learning has focussed on two
  18 KB (2,473 words) - 19:29, 19 February 2024
• BigPULP: Multicluster Synchronization Extensions
  ...figurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Flex, i.e., a highly versatile, program ...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...figurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Flex, i.e., a highly versatile, program ...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t
  6 KB (801 words) - 15:05, 23 August 2018
• Neural Networks Framwork for Embedded Plattforms
  ...ly trained reduced-precision networks reach similar performance than their high-precision equivalents. In previous projects, we have successfully developed ...-based special-purpose instructions on the PULP platform to accelerate the computing task.
  3 KB (317 words) - 14:40, 14 April 2021
• HERO: TLB Invalidation
  ...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t ...ous Embedded SoCs", ''ESWEEK special issue of ACM Transactions on Embedded Computing Systems'' [https://dl.acm.org/citation.cfm?id=3126560 link]
  6 KB (796 words) - 17:19, 18 November 2019
• Heterogeneous SoCs
  ...terogeneous integration has allowed (not only) Apple to get high computing performance under tight power constraints.]] ...Heterogeneous systems on chip''' are currently one of the main drivers for performance-per-energy advancements in various application domains.
  3 KB (421 words) - 18:41, 28 October 2020
• Energy Efficient Autonomous UAVs
  ...al class of devices used for such sophisticated algorithms are multi-cores high-end CPUs and embedded heterogeneous systems featuring powerful CPUs coupled Nowadays is well known how UAVs with high-level autonomous navigation capabilities are a hot topic both in industry a
  14 KB (2,077 words) - 15:02, 13 June 2022
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...e only at the end of 20th century, but it requires the development of high performance electronic devices. The research on the development of these electronic dev ...in significant experience with signal processing in the context of quantum computing experiments and FPGA hardware implementations
  5 KB (599 words) - 09:03, 21 December 2017
• Design of a 25 Gbps SerDes for optical chip-to-chip communication
  ...d memory has doubled only every 30 months, becoming the bottleneck of high performance computers. ...n the optical domain can bypass those issues, allowing power efficient and high transmission rates.
  3 KB (382 words) - 11:44, 20 August 2021
• Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
  ..., the data streams that reflect the underlying neuron activity can present high spatial correlation among neighboring channels. This poses new challenges r * Evaluate Power/Performance/Area of the proposed implementation.
  5 KB (741 words) - 10:05, 18 November 2019
• Wireless Sensing With Long Range Comminication (LoRa)
  ...ce since low power microprocessors are weak in terms of computation power. High computation microprocessor are power hungry though. For these reasons, mult ...cation (simulations), measuring power-consumption, and assessing detection performance in lab. conditions
  5 KB (744 words) - 15:37, 10 November 2020
• AMZ Driverless Competition Embedded Systems Projects
  ...competition we started our second season willing to improve robustness and performance even further. We hope to be faster than a human driver in the coming years. ...cameras and an IMU allowing running visual inertial algorithms in the main computing system. In addition, some image processing should be done at this system to
  6 KB (895 words) - 16:27, 30 October 2020
• IBM Research
  ...n architecture, huge amounts of data need to be shuttled back and forth at high speeds, a task at which this architecture is inefficient. ...omputing paradigms from in-memory computing to brain-inspired neuromorphic computing. Our research spans from devices and architectures to algorithms and applic
  9 KB (1,330 words) - 15:20, 15 March 2024
• Finite Element Simulations of Transistors for Quantum Computing
  computing. The existing C++ code at IIS that solves this quantum transport problem is The idea of quantum computing is to associate a bit to a two-state quantum phenomenon (a “qu-bit”), s
  3 KB (432 words) - 14:14, 23 June 2021
• NVDLA meets PULP
  [[File:nvdla_memory.png|right|NVDLA Memory System and High-Level Architecture]] in terms of performance, area, and power consumption. This includes getting familiar with NVDLA, un
  6 KB (799 words) - 13:42, 10 November 2020
• Heroino: Design of the next CORE-V Microcontroller
  ***Shared, banked, memory for high-performance memory access by both the instruction and the data ports of CV32. ...s]] [[Category:Master Thesis]] [[Category:Hot]][[Category:High Performance Computing]][[Category:FPGA & Digital ASIC Design]][[Category:Embedded systems]][[Cate
  9 KB (1,314 words) - 00:01, 7 February 2021
• Manycore System on FPGA (M/S/G)
  [[Category:High Performance SoCs]] In a quest for high-performance computing systems, few architectural models retain the flexibility of many-core syste
  8 KB (1,319 words) - 10:41, 6 July 2021
• Hardware Acceleration
  ...erators are not limited to the high-performance sector alone. In low power computing, they allow complex tasks such as computer vision or cryptography to be per ==General-Purpose Computing==
  7 KB (917 words) - 17:04, 24 November 2023
• Finite element modeling of electrochemical random access memory
  ...of finite element modeling of electrochemical devices for analog computing. The work will be carried out in the Science & Technology Department at ...RAM operation and the influence of materialspropertiesand geometry on performance metrics requires a detailed multiphysics model
  4 KB (515 words) - 17:06, 16 September 2021
• Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  ..., which are 3D components that can be approximated as 2D slices, where the high dimension can be High Performance Computing is advantageous but not necessary.
  2 KB (327 words) - 17:06, 16 September 2021
• Event-Driven Convolutional Neural Network Modular Accelerator
  ...ed approaches seem to go into the direction of a higher Sensor Activity to Computing Energy proportionality, which could bring significant advantages to many ed ...igurable in the type of neuron model to use, and in the number of physical computing engines instantiated. The accelerator operations are orchestrated by an RIS
  4 KB (651 words) - 19:10, 29 January 2021
• Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
  [[Category:Herschmi]][[Category:Event-Driven Computing]] ...your goal would be to improve algorithms, and implementations based on HD computing
  2 KB (308 words) - 20:12, 9 February 2020
• Spiking Neural Network for Autonomous Navigation
  ...pproach, and seems to go into the direction of a higher Sensor Activity to Computing Energy proportionality, which could bring significant advantages to many ed 1. Study the SNN computing paradigm, and select a population of SNN candidate for the target task
  4 KB (644 words) - 19:10, 29 January 2021
• Semi-Custom Digital VLSI for Processing-in-Memory
  ...eless communication, where massive amounts of data need to be processed at high rates. [[Category:Event-Driven Computing]]
  7 KB (882 words) - 14:33, 28 July 2021
• Hyper-Dimensional Computing Based Predictive Maintenance
  Hyperdimensional computing (HDC) is an energy-efficient alternative to ...design the classification schemes using the primitives of hyperdimensional computing. In a second step, the algorithm should be tuned to be portable to an ultra
  5 KB (759 words) - 09:18, 16 September 2021
• Accurate deep learning inference using computational memory
  ...ty limits in terms of performance and power are being reached, alternative computing paradigms are searched for in which computation and storage are collocated. ...nts on phase-change memory chips comprising more than 1 million devices to high-level algorithmic development in a deep learning framework such as TensorFl
  5 KB (628 words) - 12:51, 17 April 2020
• Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
  ...ion of implantable multielectrode-arrays (MEAs) to record brain signals at high spatio-temporal resolution. Data processing is needed to decode useful info ...omputing with numbers. HDC has proven to be promising for energy-efficient computing applied to biosignal classification [2].
  5 KB (619 words) - 19:58, 10 March 2024
• High Performance SoCs
  ==High-Performance Systems-on-Chip== ...n ever-increasing amount of '''parallel floating-point performance''' from computing systems. Increasingly, such applications must scale across a wide range of
  11 KB (1,337 words) - 10:54, 25 January 2024
• Energy Efficient SoCs
  ...SoC architectures that combine the versatility of parallel general-purpose computing with the energy efficiency of application-specific hardware accelerators.
  3 KB (339 words) - 15:59, 1 November 2023
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
  In a quest for high-performance computing systems, few architectural models retain the flexibility of many-core syste ...at 500MHz, and the L1 memory can be accessed by any of the cores through a high-throughput interconnection network with a round-trip latency of at most fiv
  8 KB (1,196 words) - 10:41, 6 July 2021
• Practical Reconfigurable Intelligent Surfaces (RIS)
  ...research for fifth-generation (5G) wireless systems and beyond, providing high data rates for all users was one of the key requirements. From now on, the ...e desired signal power and mitigate interference, improving the system’s performance, without the need of extra APs [4].
  8 KB (1,011 words) - 12:25, 16 November 2023
• Hypervisor Extension for Ariane (M)
  [[Category:High Performance SoCs]] ...ing systems (OSes) – a common technique used in secure systems and cloud computing to allow running untrusted OSes or multiple OSes in parallel.
  3 KB (391 words) - 08:49, 21 June 2022
• Matheus Cavalcante
  * High-Performance Computing
  890 bytes (104 words) - 18:33, 8 December 2020
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  [[Category:High Performance SoCs]] Much of our recent work on high-performance computing systems at IIS uses the ''Snitch'' cluster [[#ref-snitch|[3]]]. Thi
  11 KB (1,602 words) - 15:19, 9 July 2021
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  [[Category:High Performance SoCs]] ...lerator interface, allowing it to be paired with a powerful FPU to achieve high FPU utilizations and compute-over-control ratio.
  8 KB (1,220 words) - 15:18, 9 July 2021
• LLVM and DaCe for Snitch (1-2S)
  [[Category:High Performance SoCs]] ...system [[#ref-zaruba2020snitch|[1]]] targets energy-efficient high-performance systems. It is built around the minimal RISC-V Snitch core, only 15 kGE in
  11 KB (1,519 words) - 15:20, 9 July 2021
• Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
  ...itional, high-resolution cameras. The student will use a cutting-edge high-performance embedded GPU to acquire data from these devices and run sensor-fusion based ...egory:Master Thesis]] [[Category:Bachelor Thesis]] [[Category:Event-Driven Computing]] [[Category:Hot]]
  2 KB (349 words) - 15:53, 11 October 2021
• Graph neural networks for epileptic seizure detection
  ...ning graphs with convolutional networks (GCNs), achieving state-of-the-art performance in public datasets [13].[14] proposed a temporal GCN to tackle the task of 1 - Development in a high-level programming language (python) of graph neural networks and/or convolu
  10 KB (1,306 words) - 19:58, 10 March 2024
• Huawei Research
  ===About the Huawei Future Computing Laboratory=== ...research laboratory focused on fundamental research in the area of future computing systems (new hardware, new software, new algorithms).
  6 KB (799 words) - 11:11, 1 August 2022
• Spiking Neural Network for Motor Function Decoding Based on Neural Dust
  ...t al., “Real-time brain-machine interface in non-human primates achieves high-velocity prosthetic finger movements using a shallow feedforward neural net
  5 KB (662 words) - 20:05, 10 March 2024
• Fast Simulation of Manycore Systems (1S)
  [[Category:High Performance SoCs]] In a quest for high-performance computing systems, few architectural models retain the flexibility of manycore system
  10 KB (1,434 words) - 17:20, 2 August 2021
• Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
  ...f time-encoded SNNs to high-level system simulations in a high-performance computing framework. It also involves interactions with several researchers across IB ...or level and/or digital design with VHDL). Prior knowledge of neuromorphic computing concepts is a bonus but not necessary.
  3 KB (360 words) - 10:54, 31 August 2021
• Universal Stream Semantic Registers for Snitch (1S)
  [[Category:High Performance SoCs]] ...e handling such streams in hardware. This frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also ''de
  3 KB (425 words) - 17:32, 17 November 2021
• Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
  [[Category:High Performance SoCs]] ...e handling such streams in hardware. This frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also ''de
  4 KB (557 words) - 16:14, 6 November 2022
• Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  ...cision network to an appropriate representation and apply to it a suitable computing paradigm. ...gher precision. Our goal is therefore to keep this overhead of the sparse, high-precision part of the layer as small as possible and reach an optimal trade
  3 KB (497 words) - 22:15, 23 November 2022
• Mixed-Precision Neural Networks for Brain-Computer Interface Applications
  ...s. However, the deployed networks have so far all been run at a relatively high numerical precision of 8 bits. ...er a simulation or the physical Kraken chip - see references) and evaluate performance compared to the 8-bit baseline
  8 KB (1,101 words) - 20:04, 10 March 2024
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  [[Category:High Performance SoCs]] ...hardware, which brings many benefits: it frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also deco
  3 KB (431 words) - 16:13, 6 November 2022
• XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
  ...ss communication, in which massive amounts of data need to be processed at high rates. [[Category:Event-Driven Computing]]
  7 KB (933 words) - 19:29, 21 November 2021
• Integration Of A Smart Vision System
  ...activity in their field of view, they send an alarm to a centralized high-performance vision platform, which is able to pan, tilt and zoom its field of view to t ...egory:Master Thesis]] [[Category:Bachelor Thesis]] [[Category:Event-Driven Computing]] [[Category:Hot]]
  3 KB (433 words) - 15:36, 4 August 2022
• Integrating Hardware Accelerators into Snitch (1S)
  ...with a large double-precision floating-point unit (FPU) optimized for high-performance. Additionally, Snitch features two custom instruction-set-architecture (ISA
  4 KB (567 words) - 13:57, 7 September 2022
• Counter-based Fast Power Estimation using FPGAs (M/1-3S)
  [[Category:High Performance SoCs]] On the other hand, modern computing systems feature a number of ''performance counters'', i.e. hardware registers tracking carefully selected countable e
  5 KB (688 words) - 13:51, 27 October 2022
• Non-blocking Algorithms in Real-Time Operating Systems
  ...hardware and provide features such as efficient interrupt nesting to allow high priority interrupts to get the highest attention. On the software-level you Measure the performance impact, interrupt latency and jitter.
  4 KB (508 words) - 18:59, 10 January 2022
• Implementing DSP Instructions in Banshee (1S)
  [[Category:High Performance SoCs]] In a quest for high-performance computing systems, few architectural models retain the flexibility of manycore system
  10 KB (1,428 words) - 13:31, 27 October 2022
• SCMI Support for Power Controller Subsystem
  Today’s High Performance Computing (HPC) systems are complex architectures requiring on-chip dedicated HW reso ...explore.ieee.org/document/8065010 Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster]
  3 KB (467 words) - 13:55, 12 October 2022
• Serverless Benchmarks on RISC-V (M)
  [[Category:High Performance SoCs]] ...ior of these microservices/functions has been shown to have very different performance characteristics from traditional monolithic applications. For example, a sh
  6 KB (905 words) - 21:41, 6 December 2021
• Enhancing our DMA Engine with Fault Tolerance
  At IIS we are developing a modular and extensible high-performance direct memory access (DMA) engine. This DMA is integrated into a variety of ...le to runtime faults (SEUs), especially when deployed in environments with high levels of radiation, such as space. To combat this, a variety of redundancy
  2 KB (348 words) - 13:16, 24 October 2023
• Fast Accelerator Context Switch for PULP
  ...extensions targeting energy-efficient digital signal processing [2]. This computing cluster serves as an accelerator. ...stem (PCS) dynamically adjusting the operating point of a High Performance Computing (HPC) processor to meet energy, power, and thermal constraints.
  6 KB (835 words) - 16:27, 7 July 2023
• Exploring NAS spaces with C-BRED
  ...s are usually designed to be large to increase the likelihood of including high-quality networks, i.e., better than sibling candidates. A possible alternative is restricting the search to sub-spaces containing high-quality networks.
  6 KB (839 words) - 14:08, 15 February 2024
• Low-Complexity MIMO Detection
  [[File:Low_complexity_mimo_bs6-crop.png|500px|thumb|High performance low-complexity iterative MIMO receiver.]] ...to implement a low complexity MIMO detection algorithm and to optimize its performance with state-of-the-art machine learning methods. Therefore, a novel 5G-compl
  4 KB (503 words) - 13:54, 30 May 2022
• Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
  [[Category:High Performance SoCs]] ...s is an important operation used in countless applications from scientific computing to machine learning workloads.
  2 KB (214 words) - 09:39, 23 August 2023
• Optimizing the Pipeline in our Floating Point Architectures (1S)
  [[Category:High Performance SoCs]] ...fundamental for a large set of applications spanning from high-performance computing to neural network training. FP architectures usually show a large critical
  3 KB (380 words) - 14:27, 15 May 2023
• Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
  [[Category:High Performance SoCs]] ...s relative to each grid point [1]. They are widespread in high-performance computing (HPC) and underly various problems in physical simulation, economics, and i
  3 KB (431 words) - 22:29, 19 January 2023
• MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
  [[Category:High Performance Computing]] ...from sensor-monitoring all the way to robotics. Despite typically lower in performance, they are usually preferred over custom circuits and FPGAs thanks to their
  8 KB (1,304 words) - 14:44, 23 October 2023
• Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
  [[Category:High Performance SoCs]] ...-up-table (LUT) and an addition. That can significantly reduce the overall computing and energy needs.
  6 KB (846 words) - 16:50, 3 November 2022
• Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
  [[Category:High Performance SoCs]] ...-up-table (LUT) and an addition. That can significantly reduce the overall computing and energy needs.
  6 KB (823 words) - 16:32, 3 November 2022
• Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
  [[Category:High Performance SoCs]] ...ssor system-on-chip (MPSoC) designed for energy-efficient high-performance computing (HPC) applications. It is a concrete implementation of the concept Manticor
  7 KB (944 words) - 10:47, 25 January 2024
• Runtime partitioning of L1 memory in Mempool (M)
  [[Category:High Performance SoCs]] ...f 1024 Snitch cores, having 4096 banks of shared memory. The huge parallel computing power of TeraPool suits perfectly the purpose of accelerating embarrassingl
  3 KB (490 words) - 10:38, 2 November 2023
• AXI-based Network on Chip (NoC) system
  [[Category:High Performance SoCs]] ...on a single chip is rapidly growing, there is a rising need for scalable, high-bandwidth, and low-latency on-chip communication fabrics. This need is ofte
  2 KB (252 words) - 14:43, 23 October 2023
• All the flavours of FFT on MemPool (1-2S/B)
  [[Category:High Performance SoCs]] ...f 1024 Snitch cores, having 4096 banks of shared memory. The huge parallel computing power and the small latency cost of the shared memory accesses in TeraPool
  3 KB (460 words) - 18:54, 9 November 2022
• Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
  <!-- Creating Towards a High-performance Open-source Verification Suite for AXI-based Systems (1-3S/B) --> [[Category:High Performance SoCs]]
  2 KB (290 words) - 09:38, 3 November 2023
• Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
  [[Category:High Performance SoCs]] ...the RISC-V vector extension specification is introduced for efficiency and performance improvement. Spatz lean Processing Element (PE) acts as an accelerator to a
  6 KB (775 words) - 11:57, 31 October 2023
• Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
  [[Category:High Performance SoCs]] ...d supercomputing to industrial automation and avionics, including embedded computing products that nowadays feature at least one Ethernet interface. Ethernet st
  5 KB (631 words) - 09:28, 3 November 2023
• Noise Figure Measurement for Cryogenic System
  ...tire qubits readout system. It needs to provide ultra-low noise figure and high gain to ensure readout signal fidelity. Additionally, broadband operation i However, it is not trivial to set up cryogenic environment for high frequency (GHz) measurement since the device under test (DUT) will be isola
  2 KB (372 words) - 10:32, 14 February 2023
• Integrated Devices, Electronics, And Systems
  ...m designs. We are particularly interested in systems with wide bandwidth, high energy-​efficiency, low latency, and security. ...tegrated circuits and systems to address new applications, such as quantum computing, quantum sensing, and electronics-​photonics integration.
  1 KB (145 words) - 16:26, 27 September 2023
• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
  [[Category:High Performance SoCs]] To realize the performance potential of many-core
  8 KB (1,177 words) - 11:45, 13 March 2024
• Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
  [[Category:High Performance SoCs]] ...fundamental for a large set of applications spanning from high-performance computing to neural network training. A flexible highly-parametrized open-source floa
  2 KB (307 words) - 15:40, 15 February 2024
• Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
  <!-- High-performance Multimodal Computer-Vision Systems --> ...ibuted-multi-modal-vision-systed.png|450px|thumb|right|The envisioned high-performance multimodal vision system]]
  4 KB (572 words) - 11:07, 5 December 2023
• Federico Villani
  At IIS, Federico is working ultrasound systems and building a high performance ultrasound research platform. * High-Performance computing
  834 bytes (98 words) - 18:30, 8 November 2023
• Wireless In Action Data Streaming in Ski Jumping (1 B/S)
  ...k methods in ski jumping, we aim to develop a system that collects athlete performance data with a body-worn sensor node and transmits the information to the coac ...way. Field measurements (also with real ski jumpers) shall demonstrate the performance of the developed system. According to the level of the student and the chos
  6 KB (688 words) - 12:15, 23 July 2023
• Cycle-Accurate Event-Based Simulation of Snitch Core
  ...become a crucial asset for exploring SoC architectures. In this scenario, high-level simulators play an essential role in breaking the speed and design ef * Easy calibration of platform parameters for accurate performance estimation
  14 KB (2,018 words) - 22:54, 23 November 2023
• A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
  [[Category:High Performance SoCs]] ...many complex applications and take up a large fraction of high-performance computing (HPC) cycles today. They fall in the category of embarassingly parallel com
  7 KB (960 words) - 14:25, 2 May 2024
• Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
  [[Category:High Performance SoCs]] ...programming model [2] based on PULP [3] for energy-efficient flexible high-performance in-network packet processing. So far we have used the traditional PULP clus
  3 KB (374 words) - 10:24, 3 November 2023
• Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
  [[Category:High Performance SoCs]] ...core of many crucial workloads for modern computing, including scientific computing and deep learning. Finding optimal ways to schedule and parallelize GEMM is
  6 KB (848 words) - 14:25, 2 May 2024
• Network-off-Chip (M)
  As the demand for High-Performance Computing (HPC) systems continues to increase, traditional on-chip communication netw ...virtual channels that can be sent off-chip while achieving low latency and high throughput and energy efficiency.
  4 KB (586 words) - 14:27, 24 October 2023
• 3D Matrix Multiplication Unit for ITA (1S)
  ...dware acceleration of transformer models poses new challenges due to their high arithmetic intensities, large memory requirements, and complex dataflow dep ...rallelism of attention mechanism and 8-bit integer quantization to improve performance and energy efficiency. To maximize ITA’s energy efficiency, we focus on m
  3 KB (485 words) - 10:52, 12 December 2023
• Efficient collective communications in FlooNoC (1M)
  [[Category:High Performance SoCs]] To realize the performance potential of many-core
  6 KB (897 words) - 19:52, 22 February 2024
• Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
  [[Category:High Performance SoCs]] ...e evolved from Embedded MCUs a few years ago, to high performance CPUs and computing cards today.
  3 KB (459 words) - 13:24, 12 April 2024