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- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1 Semester/Bachelor students6 KB (741 words) - 18:14, 21 July 2023
- <!-- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) -->1 KB (188 words) - 09:39, 3 November 2023
- : Looking for 1-2 Semester/Master students6 KB (820 words) - 12:13, 23 July 2023
- : Looking for 1 Semester/Bachelor students5 KB (644 words) - 18:18, 21 July 2023
- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1-2 Semester/Master students6 KB (735 words) - 12:12, 23 July 2023
- #Redirect [[A Snitch-based Compute Accelerator for HERO (M/1-2S)]]66 bytes (10 words) - 21:47, 10 November 2020
- <!-- (M/1-2S): A Snitch-based Compute Accelerator for HERO --> ...pen-source Parallel Ultra-Low Power (PULP) platform [<nowiki/>[[#ref-pulp|1]]] , which provides a multicore cluster based on the open RISC-V instructio11 KB (1,617 words) - 23:59, 6 February 2021
- #Redirect [[LLVM and DaCe for Snitch (1-2S)]] ...ttps://scholar.google.com/scholar?oi=bibs&cluster=8341123140790442037&btnI=1&hl=de Snitch]2 KB (333 words) - 20:05, 15 February 2021
- #Redirect [[LLVM and DaCe for Snitch (1-2S)]] ...ttps://scholar.google.com/scholar?oi=bibs&cluster=8341123140790442037&btnI=1&hl=de Snitch]3 KB (386 words) - 20:06, 15 February 2021
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- 1. Install MemPool and test it on different configurations ...RTL language (SystemVerilog or Verilog or VHDL). Having followed the VLSI 1 course is recommended.8 KB (1,196 words) - 10:41, 6 July 2021
- <!-- (1-2S): An RPC DRAM Implementation for Energy-Efficient ASICs --> .... These ''reduced pin count DDR'' (RPC DDR) [[[#ref-rpc_dram_website|1]]] memories only require a simple on-chip PHY and can operate with regular8 KB (1,214 words) - 15:18, 9 July 2021
- #Redirect [[A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)]]2 KB (365 words) - 20:03, 15 February 2021
- ...Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) --> ...Ariane cores, and die-to-die serial link. [[#ref-zaruba2020manticore|[1]]]]]11 KB (1,602 words) - 15:19, 9 July 2021
- Ara is working well, with a prototype achieving an operating frequency of 1 GHz in a modern technology. 1. Familiarize with the RISC-V Vector Extension and the Ara source code. (~26 KB (916 words) - 15:25, 9 July 2021
- <!-- (1-2S/B): A Snitch-Based SoC on iCE40 FPGAs --> With the iCE40 FPGA family, Lattice Semiconductor [[[#ref-fpga|1]]] provides FPGAs with the world’s smallest form factor, optimized for u8 KB (1,220 words) - 15:18, 9 July 2021
- <!-- LLVM and DaCe for Snitch (1-2S) --> The Snitch ecosystem [[#ref-zaruba2020snitch|[1]]] targets energy-efficient high-performance systems. It is built aroun11 KB (1,519 words) - 15:20, 9 July 2021
- <!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> ...ts following predefined address patterns. Recent architectural extensions [1-5] propose handling such streams in hardware. This frees processors from ex4 KB (557 words) - 16:14, 6 November 2022
- <!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> ...s following a predefined address pattern. Recent architectural extensions [1,2] propose handling such streams in hardware, which brings many benefits: i3 KB (431 words) - 16:13, 6 November 2022
- <!-- Counter-based Fast Power Estimation using FPGAs (M/1-3S) --> ...ly approximated by randomly selecting a handful of signals to be observed [1].5 KB (688 words) - 13:51, 27 October 2022
- #REDIRECT [[Adding Linux Support to our DMA Engine (1-2S/B)]]61 bytes (11 words) - 17:27, 19 November 2021
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2 KB (244 words) - 12:12, 21 June 2022
- The Snitch ecosystem [1] targets energy-efficient high-performance systems. It is built around the [1] https://ieeexplore.ieee.org/document/92165524 KB (554 words) - 09:49, 17 August 2022
- <!-- Streaming Integer Extensions for Snitch (M/1-2S) --> The Snitch ecosystem [1] targets energy-efficient high-performance systems. It is built around the6 KB (770 words) - 14:19, 15 September 2022
- <!-- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) --> ...r processors are complex and require an immensely large circuit area. Ara [1], our in-house vector Processor (RISC-V Vector Extension Version 0.10) e.g.3 KB (384 words) - 12:13, 21 June 2022
- <!-- Creating Extension and Evaluation of TinyDMA (1-2S/B/2-3G) --> Currently, TinyDMA is based on the AMBA AXI4[1] on-chip communication standard. Next to AXI4, simpler protocols are used t2 KB (312 words) - 09:35, 3 November 2023
- ...ng Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) -->2 KB (282 words) - 09:27, 3 November 2023
- ...ng a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) -->2 KB (226 words) - 14:22, 27 February 2024
- <!-- Creating Towards Formal Verification of the iDMA Engine (1-3S/B) -->2 KB (272 words) - 10:21, 3 November 2023
- <!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) -->2 KB (214 words) - 09:39, 23 August 2023
- <!-- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) --> ...arrays in fixed, possibly irregular patterns relative to each grid point [1]. They are widespread in high-performance computing (HPC) and underly vario3 KB (431 words) - 22:29, 19 January 2023
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- ...eating Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) -->3 KB (392 words) - 09:38, 3 November 2023
- .../asic.ethz.ch/2022/Neo.html Neo], feature a Linux-capable '''CVA6''' core [1] and a '''Serial Link''' off-chip interface. While the chips contain a few * [1] https://github.com/openhwgroup/cva63 KB (416 words) - 10:49, 25 January 2024
- ...the concept Manticore architecture that went on display at HotChips 2020 [1]. It couples a 64-bit RISC-V application-class out-of-order CVA6 core [2,3] [1] [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9296802 Manticor7 KB (944 words) - 10:47, 25 January 2024
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- ...pendent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) -->2 KB (335 words) - 13:58, 27 October 2022
- <!-- All the flavours of FFT on MemPool (1-2S/B) --> MemPool [[#ref-Cavalcante2020|[1]]] is a IIS-born many-core system, having 256 Snitch cores and 1024 ban3 KB (460 words) - 18:54, 9 November 2022
- ...ing A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --> ...effort. A simple solution to this problem was introduced in 1996 with USB 1.0.2 KB (220 words) - 09:27, 3 November 2023
- ...s a High-performance Open-source Verification Suite for AXI-based Systems (1-3S/B) -->2 KB (290 words) - 09:38, 3 November 2023
- ...ndent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) -->2 KB (223 words) - 17:18, 18 December 2023
- ...ng a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) -->2 KB (250 words) - 09:31, 29 August 2023
- <!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) -->2 KB (249 words) - 09:36, 3 November 2023
- <!-- Creating Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) --> TileLink (https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf) is a chip-scale interconnect standard providing multiple maste1 KB (181 words) - 09:36, 3 November 2023
- <!-- Creating Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) -->2 KB (297 words) - 09:36, 3 November 2023
- ...Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) --> ...heavily present in communications kernels. The Spatz [[#ref-Spatz2022|[1]]], a small and energy-efficient vector unit based on the RISC-V vector6 KB (775 words) - 11:57, 31 October 2023
- ...ely used both in academia and industry. Ariane features a write-back level 1 data cache, which temporally stores a copy of recently accessed memory cont * [1] https://github.com/openhwgroup/cva62 KB (260 words) - 16:41, 15 November 2022
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- <!-- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) --> [[File:occamy_block_diagram.png|thumb|Figure 1: A block diagram of the Occamy chip architecture]]8 KB (1,177 words) - 11:45, 13 March 2024
- : Looking for 1-2 Semester/Master students6 KB (688 words) - 12:15, 23 July 2023
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- : Looking for 1-2 Bachelor or Semester students / 1 Master student6 KB (735 words) - 12:15, 23 July 2023
- : Looking for 1 Bachelor or Semester student5 KB (631 words) - 12:43, 23 July 2023
- : Looking for 1 Bachelor or Semester student5 KB (631 words) - 10:07, 24 July 2023
- <!-- Softmax for Transformers (M/1-2S) --> Transformers [1], initially popularized in Natural Language Processing (NLP), have found ap4 KB (573 words) - 14:46, 23 October 2023
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- <!-- Creating A Boundry Scan Generator (1-3S/B/2-3G) -->1 KB (203 words) - 09:55, 3 November 2023
- ...t, the goal is to modify a simple embedded RISC-V processor, such as Ibex [1]. The Ibex core supports both the riscv32i and the riscv32e base instructio * [1] https://github.com/lowRISC/ibex2 KB (259 words) - 11:55, 18 December 2023
- <!-- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) --> ...al family of lightweight yet high-performance data movement engines (iDMA)[1].1 KB (192 words) - 14:24, 27 February 2024
- <!-- Backend explorations for Network-on-Chips (1-2S/M) --> ...research group we implemented our own Network-on-Chip called ''FlooNoC'' [1][2], which was designed with awareness of those physical implementation eff3 KB (511 words) - 16:23, 31 October 2023
- <!-- Streaming Layer Normalization in ITA (M/1-2S) --> Transformers [1], initially popularized in Natural Language Processing (NLP), have found ap4 KB (511 words) - 12:38, 21 December 2023
- <!-- NeuroSoC RISC-V Component (M/1-2S) --> The NeuroSoC project [1] will design and demonstrate an advanced Multiprocessor System-on-Chip base3 KB (482 words) - 17:26, 10 January 2024
- ...hysical Design: Reinforcement Learning for Macro Placement and Mix-Placer (1-2S/M) --> * [1] https://dl.acm.org/doi/pdf/10.1145/3569052.35789264 KB (530 words) - 10:50, 3 November 2023
- ...tor-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M) --> ...heavily present in communications kernels. The Spatz [[#ref-Spatz2022|[1]]], a small and energy-efficient vector unit based on the RISC-V vector6 KB (844 words) - 11:41, 31 October 2023
- ...SC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) -->3 KB (342 words) - 13:02, 12 February 2024
- ...also add other enhancements. I3C specification developed by MIPI Alliance [1] , is an intelligent multi-featured interface that improves upon the key at ...e Specification for I3C® (Improved Inter Integrated Circuit), version 1.1.1, MIPI Alliance, Inc., 11 June 2021.5 KB (775 words) - 17:17, 18 December 2023
- ...ing an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) --> ...are developing a scalable and flexible family of DMA engines, called iDMA [1]. iDMA is the cluster-level DMA in both the Snitch and PULP clusters. When2 KB (314 words) - 10:27, 3 November 2023
- ...sical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)]]106 bytes (14 words) - 10:50, 3 November 2023
- ...ed Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) --> [1] “A High-performance, Energy-efficient Modular DMA Engine Architecture”2 KB (332 words) - 11:18, 3 November 2023
- <!-- Implementation of an Accelerator for Retentive Networks (M/1-2S) --> ...ars, a new class of deep learning algorithm, the Transformer architecture [1], has emerged.5 KB (735 words) - 14:31, 18 February 2024
- <!-- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) -->1 KB (165 words) - 17:19, 13 November 2023
- <!-- Writing a Hero runtime for EPAC (1-3S/B) --> #pragma omp target device(1)4 KB (501 words) - 15:27, 15 February 2024
- ...HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) -->3 KB (461 words) - 12:19, 12 February 2024
- ...HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) --> MemPool[1] is an example of the massively parallel SoCs built at IIS. It integrates 23 KB (482 words) - 15:57, 13 February 2024
- Within the WP3 of the UrbanTwin Project [1], we have designed and produced a compact, low-power, highly efficient comp [1] [https://urbantwin.ch/ Urban Twin Project]4 KB (568 words) - 13:26, 10 May 2024
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Page text matches
- * Consider about 1 slide per minute on average for your slides.1 KB (187 words) - 18:53, 22 March 2020
- : Looking for 1-2 Semester/Master students3 KB (409 words) - 10:52, 27 March 2014
- : Looking for 1-2 Semester/Master students4 KB (397 words) - 15:44, 14 February 2023
- ...ion methods including magnetic, electrostatic, and electrochemical effects[1,2,3], thus they can be better controlled for many applications. To better u2 KB (328 words) - 10:21, 14 February 2023
- ...or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). ...eks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''4 KB (444 words) - 12:43, 23 July 2023
- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1 Semester/Bachelor students6 KB (741 words) - 18:14, 21 July 2023
- ...bi equalizer. A high-level block diagram of the algorithm is shown in Fig. 1. In the ing is explained in more details in [1]. The preprocessing step is concluded with deciding over5 KB (684 words) - 10:43, 6 November 2017
- * Start with a 1-2 sentence summary of your project. (this can be repeated every week the sa IPC = 1).7 KB (1,133 words) - 07:08, 7 October 2023
- ...correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transcei : Looking for 1-2 Semester/Master students3 KB (382 words) - 20:00, 26 September 2017
- <!--: Looking for 1-2 Semester/Master students3 KB (392 words) - 12:33, 15 April 2016
- : Looking for 1-2 Semester/Master students3 KB (385 words) - 11:13, 14 April 2016
- : Looking for 1-2 Semester/Master students3 KB (508 words) - 11:12, 14 April 2016
- : Looking for 1-2 Semester/Master students2 KB (300 words) - 14:11, 13 March 2014
- : Looking for 1-2 Semester/Master students3 KB (492 words) - 12:34, 7 November 2017
- : Looking for 1-2 Semester/Master students3 KB (407 words) - 10:57, 5 November 2019
- : Looking for 1 Master student3 KB (429 words) - 09:42, 12 October 2017
- the OsmocomBB project [1] has implemented a relatively [1] OsmocomBB. http://bb.osmocom.org/trac/, April 2015.3 KB (421 words) - 10:40, 6 November 2017
- ...aseband Processing (DBB) from the [[RazorEDGE]] project on an ML605 board [1] and RF processing on the [[evalEDGE]] FMC module is available. A separate [1] [http://www.xilinx.com/ml605 Virtex-6 FPGA ML605 Evaluation Kit], June 2012 KB (273 words) - 11:30, 24 February 2017
- ...the 3GPP standard organization include enhancements to 2G and 4G networks [1] refereed to as EC-GSM-IoT and NB-IoT to enhance coverage by up to 20 dB an2 KB (277 words) - 17:59, 29 March 2017
- : Looking for 1-2 Semester/Master students2 KB (329 words) - 17:44, 21 December 2017
- : Looking for 1-2 Semester/Master students2 KB (319 words) - 17:43, 21 December 2017
- : Looking for 1-2 Semester/Master students3 KB (355 words) - 12:07, 17 January 2014
- : Looking for 1-2 Master students3 KB (472 words) - 12:12, 17 January 2014
- : Looking for 1-2 Master students3 KB (389 words) - 12:28, 17 January 2014
- ...operly engineered so that high storage capacities are obtained. Based on a 1-D battery simulator that we have recently implemented, the goal of this pro : Looking for 1 Semester/Master students3 KB (362 words) - 15:43, 4 September 2019
- : Looking for 1 Master student3 KB (456 words) - 15:43, 4 September 2019
- Standard 1-D simulation models, as popularized in the mid 90's, are computationally ve : Looking for 1 Semester/Master students3 KB (431 words) - 15:41, 4 September 2019
- ...Es and is capable of computing an AES encryption and decryption in 742 and 1,025 clock cycles, respectively. Hashing of a 512-bit message according to G3 KB (434 words) - 12:01, 26 March 2015
- : Looking for 1-2 Semester/Master students3 KB (357 words) - 18:53, 6 December 2014
- ...f-merit (FoM) is 2.8 pJ/conversion while peak INL and DNL are 2.34 LSB and 1.56 LSB, respectively.2 KB (328 words) - 18:02, 29 January 2014
- ...interest. This offset voltage can exceed the signal amplitude (100 μV ...1 mV) by three orders of magnitude and is varying over time since it is affec2 KB (311 words) - 10:53, 10 March 2015
- ...s became accessible and affordable as companies, e.g. Sound Semiconductor [1] or Coolaudio [2], manufacture specialized analog integrated circuits (ICs) ...ctive synthesizer using off-the-shelf components from Sound Semiconductor [1]. The synthesizer should include one or multiple oscillators, a voltage-con5 KB (597 words) - 12:56, 4 December 2021
- : KTI 11376.1 ...[http://dx.doi.org/10.1007/s11265-014-0949-1 DOI: 10.1007/s11265-014-0949-1]3 KB (397 words) - 14:12, 27 May 2015
- ...l hundred or thousand bits, and varying code rates ranging from 0.33 up to 1. Transmission modes with very high code rates have been proved crucial for2 KB (316 words) - 10:45, 9 February 2015
- ...nce on Communication, Control, and Computing'', Monticello, Illinois, USA, 1-5 Oct 20123 KB (352 words) - 13:56, 9 February 2015
- : Looking for 1-2 Semester / Master Thesis Students2 KB (342 words) - 16:46, 11 February 2015
- : Looking for 1/2 Semester/Master students4 KB (613 words) - 19:54, 9 February 2015
- complexity IoT devices in release 12 [1]. The low complexity is achieved by single receive antenna and 1.4 MHz bandwidth2 KB (222 words) - 10:40, 6 November 2017
- : Looking for 1-2 Interested Students2 KB (344 words) - 10:30, 5 November 2019
- : Looking for 1-2 Interested Students3 KB (366 words) - 12:40, 1 June 2017
- : Looking for 1-2 Interested Students3 KB (373 words) - 11:51, 19 August 2017
- : Looking for 1-2 Semester/Master students2 KB (225 words) - 14:58, 8 March 2014
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- : Looking for 1-2 Semester students2 KB (307 words) - 20:06, 17 February 2015
- : Looking for 1-2 Semester/Master students2 KB (251 words) - 20:06, 17 February 2015
- ...ed by the IBM TrueNorth architecture [Merolla14], an homogeneous fabric of 1 million digital spiking neurons that can be used for visual classification ...2013 International Joint Conference on Neural Networks (IJCNN), 2013, pp. 1–10.5 KB (784 words) - 14:50, 30 November 2016
- : Looking for 1-2 Semester/Master students2 KB (278 words) - 16:57, 12 July 2022
- : Looking for 1 Semester/Master student3 KB (331 words) - 15:40, 4 September 2019
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- : Looking for 1 Semester/Master student3 KB (357 words) - 15:38, 4 September 2019
- : Looking for 1 Semester student3 KB (363 words) - 15:37, 4 September 2019
- : Looking for 1 Semester/Master student3 KB (449 words) - 15:37, 4 September 2019
- : Looking for 1 Master student4 KB (488 words) - 17:12, 16 September 2021
- : Looking for 1 Master student3 KB (448 words) - 17:11, 16 September 2021
- : Looking for 1 Master student2 KB (284 words) - 17:10, 16 September 2021
- : Looking for 1 Master/ industrial internship student4 KB (608 words) - 13:58, 23 June 2021
- : Looking for 1-2 Semester students4 KB (518 words) - 16:07, 6 May 2019
- : Looking for 1-2 Semester/Master students2 KB (188 words) - 10:58, 27 March 2014
- : Looking for 1-2 Semester/Master students2 KB (348 words) - 20:01, 26 September 2017
- ...Passing algorithms in an efficient way has been developed at IIS recently [1]. :[1] [http://arxiv.org/abs/1404.3162 A Signal Processor for Gaussian Message Pa2 KB (236 words) - 09:46, 12 October 2017
- ...further development from GAP based on PULPopen. Total of 10x 32bit cores, 1 fabric controller + 9 in the cluster. ...//asic.ethz.ch/2017/Mr.Wolf.html Mr. Wolf] new generation PULP system with 1 fabric controller (micro-riscy) and a cluster with eight RI5CY (RISC-V core10 KB (1,563 words) - 10:09, 19 August 2022
- : Looking for 1-2 Master/Semester student3 KB (449 words) - 12:12, 4 November 2019
- ...e information of these repetitions, even though they contain changed data [1]. : Looking for 1-2 Semester/Master students3 KB (345 words) - 10:52, 5 April 2022
- : Looking for 1-2 Semester/Master students4 KB (667 words) - 15:23, 23 December 2016
- ...ature. This leads to significant higher FLOPS and smother thermal profile [1]. : Looking for 1-2 Semester/Master students3 KB (456 words) - 08:35, 20 January 2021
- LTE synchronization consists of 4 parts [1-5]: ...s Communications and Networking Conference'', 2009. WCNC 2009. IEEE, pages 1–6, April 2009.2 KB (350 words) - 17:56, 14 April 2016
- ...ended normal operation modes: NORX32-4-1, NORX32-6-1, NORX64-4-1, NORX64-6-13 KB (423 words) - 11:13, 13 June 2014
- ...used to build a processor architecture to efficiently run such algorithms [1]. A specific processor of this type is usually attached as a fixed-function [1] [http://arxiv.org/abs/1404.3162 A Signal Processor for Gaussian Message Pa1 KB (210 words) - 08:34, 20 January 2021
- : Looking for 1-2 Semester students3 KB (413 words) - 16:05, 21 July 2016
- Sigma point belief propagation [1] lets one describe these algorithms in a common way. While in a recent mast [1] [http://automatica.dei.unipd.it/tl_files/utenti/lucaschenato/Classes/PSC102 KB (265 words) - 08:34, 20 January 2021
- : Looking for 1 or 2 Master/Semester thesis students3 KB (378 words) - 19:56, 9 February 2015
- : Looking for 1 Master or 2 semester project students : if interested in FPGA development, VLSI 1 is required3 KB (408 words) - 13:17, 5 February 2016
- ...The latest packet switched GSM enhancement called Evolved EDGE even allows 1 Mobile Station (MS) to use 2 frequency carriers in the downlink. This furth2 KB (250 words) - 17:45, 14 April 2016
- ...increase and low-power features is likely to be introduced in March 2016 [1]. ...plexity and low throughput Internet of Things (CIoT)'', 3GPP TR 45.820 v13.1.0, 2015.3 KB (384 words) - 16:41, 17 July 2016
- ...hine (M2M) communications and the Internet of things (IoT) was introduced [1]. [1] http://www.nextgcom.co.uk/wordpress/wp-content/uploads/2014/09/ARM-NextG-L3 KB (335 words) - 14:20, 4 November 2019
- : Looking for 1 semester student2 KB (344 words) - 15:34, 4 September 2019
- : VLSI 1 and enrolment in VLSI 2 is required * Literature survey, building a basic understanding of the problem at hand (1 week)9 KB (1,289 words) - 19:45, 24 March 2015
- : Looking for 1-2 Master students3 KB (466 words) - 19:37, 3 March 2016
- : Looking for 1-2 Master students : Student 1, Student 23 KB (480 words) - 19:08, 28 January 2017
- : Looking for 1-2 Master students3 KB (438 words) - 18:06, 3 February 2015
- : Looking for 1-2 Semester/Master students2 KB (247 words) - 17:38, 21 December 2017
- ...needs to be transmitted to the following baseband ASIC can reach orders of 1 Gb/s. To avoid any disturbances to the vulnerable receiver and to mimize th : Looking for 1-2 Semester/Master students1 KB (197 words) - 17:37, 21 December 2017
- : Student 1, Student 23 KB (431 words) - 18:04, 28 January 2017
- ...d a battery. The node should also be able to have a lifetime that at least 1 days processing data and generate a pulse when particular events are detect4 KB (589 words) - 10:14, 3 August 2018
- : Looking for 1 Semester/Master student : Student 1, Student 23 KB (376 words) - 18:04, 28 January 2017
- ...or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). ...eks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''7 KB (816 words) - 11:57, 8 May 2024
- ...types, while still preserving functional and timing accuracy. [1][2] 1. '''Research:''' Getting familiar with the implementation of GVSoC and how4 KB (520 words) - 15:15, 4 December 2023
- in what's called the the Internet of things (IoT) [1,2]. To realize this vision, cellular standards ...0) for Machine to Machine (M2M) communications and the IoT was introduced [1]. Since Cat-0 devices target the low-complexity M2M market, 75 percent4 KB (561 words) - 10:43, 6 November 2017
- System-in-a-Package (SiP) modems such as [1] are evalEDGE v.1.0 board. The ZedBoard can be used for controlling or7 KB (1,105 words) - 20:02, 26 September 2017
- : Looking for 1 Master or (2 or 1) semester project students (work load will be adjusted)5 KB (707 words) - 11:22, 5 February 2016
- A huge variety of integrated audio modules such as [1] exist on the marked. In cellular devices an audio chip can be placed betwe [1] [http://www.analog.com/en/audiovideo-products/audio-signal-processors/adau2 KB (286 words) - 18:15, 17 December 2015
- At IIS, we use an evaluation platform based on the Xilinx Zynq-7000 SoC [1] with PULPonFPGA [2] implemented in the programmable logic to study the int5 KB (716 words) - 13:43, 29 November 2019
- <!--: Looking for 1-2 Semester students2 KB (300 words) - 11:23, 14 April 2016
- * VLSI 1 * Fixed-point model, implementation loss, test environment (1-2 weeks)8 KB (1,145 words) - 11:30, 5 February 2016
- * VLSI 18 KB (1,197 words) - 18:18, 29 August 2016
- <!--: Looking for 1-2 Semester/Master students3 KB (420 words) - 11:22, 14 April 2016
- .../3G/4G voice communication shall be implemented on an ASIC. Previous work [1] can be used as reference. An ASIC solution as opposed to a CPU/DSP solutio1 KB (229 words) - 18:01, 29 March 2017
- : Looking for 1-2 Interested Students3 KB (373 words) - 19:40, 14 April 2016
- ...ure (PTAT) current to result in a temperature independent voltage of about 1.2V. Such a voltage is not compliant with modern CMOS processes that have su ...ild a summing network for the generation of the constant band-gap voltage [1]. Switched capacitor networks have the advantage that they can be made to h4 KB (471 words) - 11:13, 3 May 2018
- ...sed jointly with a ZedBoard and an ML605 for receiver characterization in [1]. The evalEDGE board itself has been published in [2]. The current evalEDGE [1] H. Kröll, S. Zwicky, B. Weber, C. Roth, D. Tschopp, C. Benkeser, A. Burg,2 KB (289 words) - 17:10, 17 December 2015
- ...hine (M2M) communications and the Internet of things (IoT) was introduced [1]. In order to develop signal-processing algorithms for the fast evolving LT [1] Redefining LTE for IoT. http://www.nextgcom.co.uk/wordpress/wp-content/upl2 KB (347 words) - 17:58, 14 April 2016
- : Looking for 1 Master student or 2 semester-project students2 KB (343 words) - 10:24, 14 September 2016
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- ...n, we propose an alternative, two-stage system architecture consisting of: 1. "wake-up sensing" (WUS) circuit, and 2. main microprocessor (MCU or DSP).7 KB (895 words) - 17:02, 28 July 2017
- : Looking for 1-2 Semester/Master students2 KB (277 words) - 11:10, 3 May 2018
- : Looking for 1-2 semster project students or 1-4 students for a group project. * Some experience programming (Computer Science 1+2 or equivalent)8 KB (1,176 words) - 16:26, 30 October 2020
- ...ity streams have been introduced with the Evolved EDGE 2G cellular system [1], the recent EC-GSM-IoT standard achieves up to 20 dB coverage extension by [1] 3GPP. Release 7. http://www.3gpp.org/release-7, 2007.3 KB (418 words) - 10:39, 6 November 2017
- ...RF and DBB portions of stoneEDGE communicate using the standardized DigRF 1.12 interface [2]. However, the DigRF standard is by definition the interfac [1] Advanced Circuit Pursuit, ACP AG. http://www.newacp.ch/, September 2015.2 KB (299 words) - 17:58, 14 April 2016
- [[File:lteRxChain.png|thumb|Figure 1: LTE Rx-chain.]]2 KB (245 words) - 10:39, 6 November 2017
- ...neural networks (such as GoogLeNet [http://arxiv.org/pdf/1409.4842v1.pdf (1)]) as a backend. Most efforts to embed these models in low-power devices ha <!--: Looking for 1-2 Master students-->4 KB (593 words) - 14:57, 30 November 2016
- ...orking on an efficient FPGA implementation of an online active-set method [1]. The project is a continuation of a [http://iis-projects.ee.ethz.ch/index. [1] Ferreau, Hans Joachim. "An online active set strategy for fast solution of4 KB (542 words) - 12:39, 1 June 2017
- ...nvNets), nowadays even outperfoming humans on object classification tasks [1,2]. : Looking for (1 or 2) Master or (1 to 3) semester project students (work load will be adjusted)3 KB (397 words) - 18:17, 29 August 2016
- : Looking for 1 Master or (1 or 2) semester project students (work load will be adjusted) : Looking for (1 or 2) Master or (1 to 3) semester project students (work load will be adjusted)2 KB (285 words) - 18:16, 29 August 2016
- ...ed for 4G transceiver development. The evaLTE board has been published in [1]. The predecessor of the evaLTE board named [[evalEDGE]] offered 2G support [1] B. Weber, H. Kröll, S. Altorfer, and Q. Huang, "Cellular Baseband Develop2 KB (240 words) - 17:07, 17 December 2015
- ...coverage increase and low-power features is getting finalized during 2016 [1,2]. Current research at the institute includes a first prototype of an EC-G ...the base station has to be estimated and corrected such that it is below 0.1 ppm at the receive signal level (or receive signal level to interference le4 KB (582 words) - 20:00, 26 September 2017
- ...ill port a set of existing vision algorithms, based on the VlFeat library [1], on the PULP platform, dealing with parallel programming challenging, low- : Looking for 1 or 2 interested Semester Project Students4 KB (628 words) - 16:16, 20 February 2018
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- as observed in some previous work [1]. This project abstracts from the specific localization3 KB (426 words) - 11:41, 21 July 2017
- ...tions (1*32b+1*16b) which can then be processed in parallel. (e.g. 1 ALU + 1 LSU instruction)3 KB (377 words) - 10:25, 5 November 2019
- ...memory support for many-core accelerators in heterogeneous embedded SoCs [1,2]. Recently, we have switched to a new evaluation platform based on the Ju : Looking for 1-2 Interested Master Students (Semester Project)5 KB (711 words) - 10:27, 5 November 2019
- : Looking for 1 Master/Semester student4 KB (555 words) - 16:36, 23 May 2018
- ...m/2015/09/recurrent-neural-networks-tutorial-part-1-introduction-to-rnns/ (1)] WildML, Recurrent Neural Networks Tutorial.4 KB (522 words) - 13:38, 10 November 2020
- : Looking for 1-2 Master students : Student 1, Student 23 KB (403 words) - 20:45, 9 August 2016
- ...memory support for many-core accelerators in heterogeneous embedded SoCs [1,2]. Our solution is based on the Remapping Address Block (RAB): A hardware <!-- : Looking for 1 Interested Master Student (Semester Project) --->5 KB (712 words) - 17:57, 7 November 2017
- ...ficiently managed by a kernel-level driver module running on the host CPU [1,2] and a dedicated helper thread running on the accelerator [3]. The first : Suitable for 1 interested Master student (Semester Project)6 KB (866 words) - 13:43, 29 November 2019
- : Looking for 1 semester student3 KB (365 words) - 17:10, 16 September 2021
- ...n step where residual frequency error is reduced to a configurable amount (1 kHz is our value of choice) is implemented. Then a fine frequency estimatio ...part of a modem SoC. The entire DFE occupies a core area of 0.62 mm2 in a 1.2-V 0.13-μm CMOS technology with clock rate 76.8 MHz. Finally, to verify a2 KB (340 words) - 10:39, 6 November 2017
- ...line by beating the 2nd best player in the world Lee Sedol in the game Go [1]. A game which were considered to be too complex to be solved with classic The goal of this thesis is to port the recent published methods [1][2][3] (mainly applied on games: e.g. Go and set of Atari Games) to a new c6 KB (828 words) - 16:26, 20 February 2018
- : Looking for 1-2 Master students : Student 1, Student 23 KB (485 words) - 17:46, 10 August 2016
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- <!-- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) -->1 KB (188 words) - 09:39, 3 November 2023
- : Looking for (1 or 2) Master or (1 or 2) semester project students (work load will be adjusted) : Looking for (1 or 2) Master or (1 to 3) semester project students (work load will be adjusted)3 KB (362 words) - 16:25, 30 October 2020
- : 1-2 Master thesis or 2-3 semester project students * VLSI 1 or equivalent10 KB (1,357 words) - 16:25, 30 October 2020
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- ...is to build such an ultra low power oscillator for a frequency range up to 1 MHz based on latest research results and to achieve a comparable efficiency : Looking for 1-2 Semester students2 KB (368 words) - 18:58, 19 December 2016
- ...is project is to compensate the process variation in the PULP v3 SoCs by (1) characterize and correlate the PVT sensors response to ambient and process : Looking for 1 Master Students (Semester Project)3 KB (348 words) - 15:31, 13 September 2016
- : Looking for 1-2 Semester students3 KB (362 words) - 17:35, 21 December 2017
- Frequency tuning capabilities spanning the range from a few kHz up to 1 GHz and more in combination with high frequency resolution is required in S : Looking for 1 Master student or 1 semester-project student3 KB (389 words) - 11:20, 14 September 2016
- ...with 20 dB coverage increase and low-power features got finalized in 2016 [1]. Current research at the institute led to a prototype of an EC-GSM-IoT mod [1] 3GPP. Release 13. http://www.3gpp.org/release-13, 2016.2 KB (286 words) - 10:37, 6 November 2017
- : Looking for 1-2 Semester students3 KB (428 words) - 11:45, 20 August 2021
- ...tion of the DPLL could be lower than 500fs while consuming power less than 1 mW. : Looking for 1-2 Semester students3 KB (453 words) - 11:45, 20 August 2021
- [[File:Fpga_testbed.png|thumb|Figure 1: FPGA testbed]] reduce the communication bandwidth from 20 MHz (LTE Cat-1) to 1.4 MHz for Cat-M1 and6 KB (900 words) - 16:58, 7 May 2018
- ...Integrated Circuits Conference (CICC), 2015 IEEE, San Jose, CA, 2015, pp. 1-8.4 KB (514 words) - 15:51, 20 August 2021
- 1. design a low-power interface in standard cell technology that could be use ...2013 International Joint Conference on Neural Networks (IJCNN), 2013, pp. 1–10.9 KB (1,427 words) - 18:36, 5 September 2019
- 1. acquire familiarity with the chosen deep learning framework (Keras or Torc6 KB (909 words) - 19:50, 30 May 2017
- ...20 dB coverage increase and low-power features got finalized during 2016 [1]. Current research at the institute produced a first prototype of an EC-GSM [1] 3GPP. Release 13. http://www.3gpp.org/release-13, 2016.2 KB (295 words) - 11:27, 6 November 2017
- ...number of zero-valued operands (parameters and/or activations) in order to 1) take advantage of sparsity (for storing the model) and to 2) minimize the But when the precision is extremely reduced (i.e., 1-bit or 2-bits operands), these solutions can no longer be applied, and quan18 KB (2,473 words) - 19:29, 19 February 2024
- ...4G based NB-IoT and a 2G based Extended Coverage GSM for IoT (EC-GSM-IoT) [1]. The latter promises up to 20 dB coverage increase compared to legacy solu2 KB (289 words) - 18:00, 29 March 2017
- 1. create a spiking phoneme dataset using a set of real speakers (both male a6 KB (920 words) - 16:33, 3 October 2019
- ...wed by the IBM TrueNorth architecture [Merolla14], a homogeneous fabric of 1 million digital spiking neurons that can be used for visual classification7 KB (1,000 words) - 12:22, 13 January 2017
- 1. Evaluate existing small CNN models in literature, such as SqueezeNet and T5 KB (794 words) - 13:19, 13 January 2017
- ...respectively. (By using 8 timeslots, which is the maximum, a throughput of 1.9 Mbit is achievable with 2 antennas). Current research at the institute le2 KB (378 words) - 18:00, 29 March 2017
- In this context the Parallel Ultra Low-Power Platform [1] developed here at IIS, is the key computational unit to bring state-of-the * 1. HW design: starting from the drone's schematics, design and develop the PU6 KB (875 words) - 11:06, 23 February 2018
- ...racy was shown to be reduced by about 10% or less. (75% instead of 85% Top-1 accuracy in the sound recognition CNN.) : Looking for 1-2 semester student6 KB (823 words) - 08:36, 20 January 2021
- : Looking for 1 Master student3 KB (392 words) - 14:17, 5 April 2022
- : Looking for 1-2 Semester students2 KB (315 words) - 13:00, 22 February 2017
- : Looking for 1-2 Semester/Master students2 KB (249 words) - 15:36, 15 September 2021
- ...r 2-3 students for a semester project (or 1 semester student FPGA only) or 1 student for a master thesis.6 KB (842 words) - 08:37, 20 January 2021
- : Looking for 1-2 Master students4 KB (546 words) - 11:33, 17 April 2020
- ...rch groups are focusing on reducing networks bit precision to 8, 4 or even 1 bit, as targeted by [Andri2017]. As consequence, the design of hardware ar ...fixed-point MAC able to operate with multiple bit precision (16, 8 ,4 ,2, 1 bits, signed and unsigned) with multiple destination registers for the accu7 KB (1,001 words) - 10:43, 26 June 2017
- : Looking for 1-2 Semester/Master students3 KB (401 words) - 19:08, 29 January 2021
- ...and their implementation (for example see the RISC-V Debug Specification [1]). [1] https://github.com/riscv/riscv-debug-spec5 KB (729 words) - 11:27, 11 December 2018
- : Looking for 1-2 Semester/Master students3 KB (366 words) - 15:39, 10 November 2020
- ...e of the reasons why we are considering an external HDMI transmitter chip [1] for managing the actual HDMI implementation. In a minimal pin-count config [1] http://www.analog.com/en/products/audio-video/analoghdmidvi-interfaces/hdm4 KB (603 words) - 09:37, 10 July 2018
- ...f various single-cluster PULP configurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Fle ...PU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 to 64 cores.6 KB (805 words) - 12:17, 22 January 2018
- ...f various single-cluster PULP configurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Fle ...PU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 to 64 cores.6 KB (801 words) - 15:05, 23 August 2018
- : Looking for 1-2 Semester/Master students3 KB (409 words) - 13:58, 9 November 2017
- : Looking for 1-2 Semester/Master students [1] 3GPP. Release 13. http://www.3gpp.org/release-13, 2016.3 KB (440 words) - 16:32, 18 May 2018
- : Looking for 1-2 Semester/Master students [1] 3GPP. Release 13. http://www.3gpp.org/release-13, 2016.3 KB (427 words) - 09:37, 14 September 2018
- : Looking for 1-2 Semester/Master students4 KB (460 words) - 21:42, 30 January 2018
- : Looking for 1 Semester/Master student3 KB (393 words) - 13:53, 13 November 2020
- : Looking for 1 Master or 1 semester project students3 KB (317 words) - 14:40, 14 April 2021
- ...ass the EC-GSM-IoT requirements for all coverage classes (CCs) by at least 1 dB.1 KB (174 words) - 19:52, 21 March 2018
- The tracks can be chosen individually (1 or 2). A detailed task description will be worked out right before the proj4 KB (602 words) - 10:45, 31 January 2023
- With the PULP platform [1], the IIS actively develops a manycore platform for ultra-low power operati : VLSI 16 KB (796 words) - 17:19, 18 November 2019
- ...ments for the so called cellular Internet of Things (IoT) defined by 3GPP [1] include EC-GSM-IoT, NB-IoT, and eMTC. In particular the 2G based EC-GSM-Io ...eet the challenging interference suppression requirements defined by 3GPP [1]. The most promising algorithmic candidate will be implemented in hardware,2 KB (269 words) - 13:15, 31 October 2019
- : Looking for 1 Semester student3 KB (421 words) - 09:38, 14 September 2018
- ...g more attention and showed to be a viable option to compress EEG signals [1,2].5 KB (641 words) - 13:36, 9 September 2020
- ...on the Parallel Ultra-Low-Power [2] architecture paradigm, which features 1+8 general-purpose RISC-Vcores: one, named Fabric Controller (FC), acts as t [[File:cf_aideck.jpg|thumb|right|200px| The ''CrazyFlie 2.1'']]14 KB (2,077 words) - 15:02, 13 June 2022
- : Looking for 1-2 Semester/Bachelor/Master students : VLSI 15 KB (621 words) - 18:09, 9 October 2022
- : Looking for 1-2 Semester/Bachelor/Master students : VLSI 15 KB (549 words) - 12:35, 28 November 2022
- ...or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). ...eks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''6 KB (797 words) - 16:16, 23 February 2024
- ...roving the quality of life for patients with epilepsy that afflicts nearly 1% of the world's population.10 KB (1,341 words) - 10:46, 25 April 2018
- rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]] rect 953 1 1802 740 [[Positioning with Wireless Signals]]7 KB (814 words) - 16:53, 8 January 2024
- ...g algorithms, different stress types were identified with 88% accuracy, in 1-minute time windows. These predictions are used to help firefighters train7 KB (1,003 words) - 17:30, 6 December 2021
- : Looking for 1-2 Master students3 KB (354 words) - 16:06, 6 May 2019
- ...og signal outputs of Circuit Quantum Electrodynamics (CQED) at 12-bits and 1 GSPS resolution. You will use an Arbitrary Waveform Generator (AWG) to prov : Looking for 1-2 Semester/Master students5 KB (599 words) - 09:03, 21 December 2017
- : Looking for 1 Master or semester student3 KB (382 words) - 11:44, 20 August 2021
- : Looking for 1-2 Semester or Master students3 KB (329 words) - 11:43, 20 August 2021
- ...lp improving the localization precision as observed in some previous work [1]. This project abstracts from the specific localization technique and focus5 KB (697 words) - 13:36, 11 January 2018
- ...s, that there will be 15 billion smart devices with Internet connectivity [1]. Potential applications include smart metering, tracking in logistics, env : Looking for 1-2 Semester/Master students4 KB (481 words) - 16:33, 18 May 2018
- * [1] Crazyflie2.0 http://www.bitcraze.io/crazyflie-2/4 KB (605 words) - 16:35, 20 February 2018
- * [1] Crazyflie2.0 http://www.bitcraze.io/crazyflie-2/5 KB (623 words) - 16:14, 20 February 2018
- [1] Bitcraze Crazyflie2.0 http://www.bitcraze.io/crazyflie-2/7 KB (1,008 words) - 16:20, 20 February 2018
- ...lgorithms on tiny size aerial vehicles such as the Bitcraze CarzyFlie 2.0 [1]. This project focuses on the feasibility study and the development of high [1] Bitcraze Crazyflie2.0 http://www.bitcraze.io/crazyflie-2/6 KB (842 words) - 16:18, 20 February 2018
- ...possible to self-sustainability. Using a commercially available platform [1], the student will make all [1] Bitcraze Crazyflie2.0 http://www.bitcraze.io/crazyflie-2/6 KB (914 words) - 16:17, 20 February 2018
- ...t by which are known to anticipated important disease if not timely cured [1]. Given the constrained conditions under which we operate, i.e, wearable de : [1] B.A.Koplanand et al, “Ventricular Tachycardia and Sudden Cardiac Death,4 KB (597 words) - 19:15, 9 March 2020
- ...th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, 2017, pp. 1-6.4 KB (649 words) - 17:27, 22 January 2019
- : Looking for 1 Interested Master Student (Semester/Master Project)5 KB (706 words) - 17:41, 19 June 2019
- : Looking for 1 Interested Master Student (Semester Project)4 KB (499 words) - 17:40, 19 June 2019
- 1. Take confidence with the current core architecture, understading the pipel4 KB (661 words) - 08:38, 20 January 2021
- : Looking for 1-2 Semester/Master students3 KB (381 words) - 14:17, 28 January 2023
- : Looking for 1-2 Semester Thesis/Group Work students3 KB (447 words) - 16:11, 18 September 2018
- ...x|thumb|LTE Cat-M1 Power Consumption over time in discontinuous reception [1].]] : Looking for 1-2 Bachelor/Semester/Master students (variable scope of project)3 KB (346 words) - 14:04, 11 January 2021
- : Looking for 1-2 Semester or master students2 KB (359 words) - 16:06, 6 May 2019
- : Looking for 1-2 Master/Semester/Bachelor student(s)4 KB (566 words) - 15:50, 9 February 2021
- : Looking for 1-2 Semester or master students2 KB (356 words) - 15:55, 6 May 2019
- We are looking for 1-2 motivated Semester Thesis students <br>4 KB (597 words) - 16:57, 12 July 2022
- : Looking for 1-2 Semester or master students2 KB (347 words) - 11:43, 20 August 2021
- We are looking for 1-2 motivated Semester Thesis students <br>2 KB (240 words) - 16:57, 12 July 2022
- 1. Scalability: A mesh network is scalable if it can cope with networks of di5 KB (685 words) - 15:34, 10 November 2020
- We are looking for 1-2 motivated Semester Thesis/Group Work students <br>2 KB (268 words) - 16:57, 12 July 2022
- ...ning set. Thus, a key goal of the internship is to implement and evaluate (1) A-weighting sound pressure level algorithm(s) and (2) explore audio classi5 KB (622 words) - 15:36, 10 November 2020
- : Looking for 1-2 Semester/Master students4 KB (497 words) - 16:50, 21 June 2018
- ...ed to one of the neurons sensed by the electrode - one electrode can sense 1 – 4 neurons in the neighbourhood -). This process is called "spike sortin ...16 SPI channels that communicate with multiple-channels ADCs (for example [1]) for neuron-inspired applications and to tape it out in umcL65 nm technolo8 KB (1,269 words) - 18:40, 5 September 2019
- ...inspired from the very size of the biological brain’s circuits: assuming 1 bit per synapse, the brain is made up of more than 24 billion of such ultra17 KB (2,419 words) - 20:09, 10 March 2024
- ...cation needs knowledge about its position. In particular for cellular IoT [1] there are 3 options to attain position information: [1] 3GPP. Release 13. http://www.3gpp.org/release-13, 2016.1 KB (204 words) - 13:14, 31 October 2019
- * [1] J Microw Power. 1983 Sep;18(3):305-9.: https://www.ncbi.nlm.nih.gov/pubmed ...al impedance tomography." Journal of Medical and Biological Engineering 36.1 (2016): 71-79.6 KB (857 words) - 15:37, 10 November 2020
- * [1] Isella L, Romano M, Barrat A, Cattuto C, Colizza V, et al. (2011) Close En6 KB (780 words) - 15:37, 10 November 2020
- * [1] Aoudia, F. A., Gautier, M., Magno, M., Le Gentil, M., Berder, O., & Benini Figure Source: ref [1]5 KB (744 words) - 15:37, 10 November 2020
- ...d a battery. The node should also be able to have a lifetime that at least 1 days processing data and generate a pulse when particular events are detect4 KB (594 words) - 15:38, 10 November 2020
- ...vel hardware experiments on phase-change memory chips comprising more than 1 million devices to high-level algorithmic development in a deep learning fr9 KB (1,330 words) - 15:20, 15 March 2024
- ...exploit a thin ferroelectric layer between gate and channel to store data [1]. These devices can be exploited as the basic cell of analog compute-in-mem 1. Work in close contact with industry partners for the development of a FeFE3 KB (352 words) - 18:02, 16 December 2022
- ...oral windows for Riemannian features results in 75.47±12.8% accuracy with 1.6x faster testing than CSP.2 KB (231 words) - 17:53, 7 August 2018
- ...fication tasks on only a small portion of Xilinx(R) UltraScale(TM) FPGAs: (1) We propose simple logical operations to rematerialize the hypervectors on3 KB (434 words) - 10:11, 8 August 2018
- : Looking for 1-2 Semester/Master students5 KB (614 words) - 15:02, 4 March 2019
- * [1] ETSI EN 300 718-1 V1.2.1 (2001-05) https://www.etsi.org/deliver/etsi_en/300700_300799/30071801/01.02 ...ernational Workshop on Measurement and Networking (M&N), Naples, 2017, pp. 1-6.5 KB (729 words) - 10:02, 22 February 2021
- ...have to be calibrated and evaluated with real-world in-field measurements.[1] For that reason, the WSL Institute for Snow and Avalanche Research SLF in * [1] A. Caviezel et al., "Design and Evaluation of a Low-Power Sensor Device fo5 KB (714 words) - 08:37, 23 November 2022
- ...been standardized to fullfill the 5G requirements for this kind of device [1]: LTE Cat-M1 (eMTC) and NB-IoT. They both offer reduced cost and power cons : Looking for 1-2 Semester/Master students3 KB (447 words) - 11:55, 29 October 2019
- : Looking for 1-2 Semester or master students3 KB (350 words) - 14:52, 25 September 2019
- ...iological information can be derived also from single-element transducers [1]. ...al problems. As a main target, we consider the monitoring of artery walls [1]. The project will include the design of experiments, microcontroller imple3 KB (361 words) - 19:02, 6 December 2023
- ...trollers, operating with a single US channel and consuming less than 20mW [1]. In this project, you will work on the extension of a novel wearable US probe [1] to extend its lifetime thanks to energy harvesting solutions. The main tas3 KB (337 words) - 18:42, 6 December 2023
- ...trollers, operating with a single US channel and consuming less than 20mW [1]. ...nd in a synchronized way US and EMG data. The ultra-low-power US probe of [1] and the BioWolf platform for ExG signals [3] will be considered as startin3 KB (437 words) - 19:03, 6 December 2023
- The goal of this project is to 1) port and integrate a the PREM infrastructure previously developed for the1 KB (162 words) - 18:20, 20 November 2018
- ...or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). ...eks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''4 KB (539 words) - 12:43, 23 July 2023
- : Looking for 1-2 Semester/Master students6 KB (820 words) - 12:13, 23 July 2023
- ...CT [[Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)]]90 bytes (12 words) - 08:50, 7 February 2023
- * Experience with System Verilog or Verilog, VLSI 12 KB (250 words) - 18:21, 20 February 2023
- : Looking for 1 Semester/Bachelor students5 KB (644 words) - 18:18, 21 July 2023
- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1-2 Semester/Master students4 KB (551 words) - 11:06, 11 July 2019
- ...ilities in classifying Electromygraphy (EMG) data for gesture recognition [1]. : Looking for 2 students for a semester project or 1 student for a master thesis.5 KB (731 words) - 16:42, 27 August 2019
- : Looking for 1 Master/semester student3 KB (432 words) - 14:14, 23 June 2021
- : Looking for 1 Master student4 KB (517 words) - 17:09, 16 September 2021
- ...indeed a face it will run, using advanced libraries liek TensorFlow lite [1], the whole face recognition task. [1] https://www.tensorflow.org/lite/7 KB (1,030 words) - 19:05, 29 January 2021
- : Looking for 1-2 Semester/Master students6 KB (735 words) - 12:12, 23 July 2023
- * VLSI 1 / Microcontroller experience (only in case of a Master Theis)2 KB (220 words) - 20:46, 12 November 2020
- : • Looking for 1-2 interested students in Electrical Engineering or Experimental Physics (s5 KB (615 words) - 12:23, 9 May 2019
- : Looking for 1-2 Semester/Master students [1] Sierra Wireless. R1-131043: PBCH Correlation Decoder.3 KB (415 words) - 18:54, 29 October 2020
- ...mbeddings to the model. You can start from an existing CNN implementation [1], and extend it with additional embeddings. : Looking for 2 students for a semester project or 1 student for a master thesis.4 KB (585 words) - 11:12, 21 July 2020
- : Looking for 1-2 Semester/Master students [1] Sierra Wireless. R1-131043: PBCH Correlation Decoder.3 KB (431 words) - 21:47, 18 November 2019
- : • Looking for 1-2 interested students in Electrical Engineering or Experimental Physics (s5 KB (665 words) - 10:30, 5 June 2019
- : Looking for 1 Interested Master Student (Master/Semester Project)4 KB (531 words) - 18:00, 19 June 2019
- : Looking for 1 Interested Master Student (Semester Project), possibly also given as a smal3 KB (466 words) - 18:20, 19 June 2019
- : Looking for 1 Interested Master Student (Master/Semester Project)2 KB (300 words) - 18:27, 19 June 2019
- ...rrelation properties of the new (left) and old (right) waveforms. Source: [1].]] ...been proposed to reduce the complexity to a 1D sweep using a clever trick [1].3 KB (358 words) - 10:51, 5 April 2022
- 1: Smart shock sensor. Piezo setting counter: Placing a small piezo capacitor ...re the real time data while the tool is running. In the range of 100Hz and 1 to 8 IO ports with differing signal types. Possible communication protocols5 KB (645 words) - 15:41, 10 November 2020
- 1. Familiarizing with the architecture of the OpenPULP cluster and the Ibex p 3. FPGA evaluation of the implementation (~1-2 person months).6 KB (980 words) - 14:46, 2 June 2021
- ...e amount of data to acquire and the costarring of power consumption (below 1-200mW) a low power FPGA is planned to be used to acquire and "compress/proc4 KB (526 words) - 15:48, 10 November 2020
- At ETH, we are developing our own many-core system called MemPool [1]. It boasts 256 lightweight 32-bit Snitch cores developed at ETH [2]. They <span class="csl-left-margin">[1] </span><span class="csl-right-inline">M. Cavalcante, S. Riedel, A. Pul8 KB (1,319 words) - 10:41, 6 July 2021
- ...ng ternary weights, which means all network weights are quantized to {-1,0,1}, we can design the fundamental compute units in hardware without using an7 KB (917 words) - 17:04, 24 November 2023
- : Looking for 1 semester student2 KB (350 words) - 17:07, 16 September 2021
- : Looking for 1-2 M.S. students5 KB (584 words) - 12:09, 29 October 2020
- ...access memory (ECRAM) isa novel type of non-volatile memory (NVM) [1,2] to provide acceleration for training of deep neural networks (D ....Li-Ion Synaptic Transistor for Low Power Analog Computing. Adv. Mater.29, 1–8 (2017).4 KB (515 words) - 17:06, 16 September 2021
- ...goal of the project is to develop and optimize phase change memory (PCM) [1,2] for non-von Neumann computing. The work will involve experimental chara : [1] M. Le Gallo and A. Sebastian, “An overview of phase-change memory device5 KB (640 words) - 14:13, 23 June 2021
- : Looking for 1 Master student3 KB (372 words) - 17:06, 16 September 2021
- : Looking for 1 Master/semester student2 KB (327 words) - 17:06, 16 September 2021
- : Looking for 1 Master student. Prior to the Master thesis, you are welcome to carry a seme2 KB (320 words) - 12:21, 23 June 2021
- 1. learn how the existing neural engine works ...hic Manycore Processor with On-Chip Learning," in IEEE Micro, vol. 38, no. 1, pp. 82-99, January/February 2018.4 KB (651 words) - 19:10, 29 January 2021
- ...find a global model using hyperdimensional superposition of model weights [1]. A preliminary study [2] showed that we can find a global model for 9 subj : Looking for 1-2 students for a semester project or group project.5 KB (672 words) - 09:20, 16 September 2021
- 1. Familiarizing with the RISC-V Vector Extension and the Ara source code. (~ ...For more details refer to [http://eda.ee.ethz.ch/index.php/Design_review (1)].4 KB (627 words) - 14:42, 29 October 2020
- Hyperdimensional (HD) computing [1] is a brain-inspired computing paradigm based on representing information w2 KB (260 words) - 15:51, 29 October 2019
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstrationHyperdimensional (HD) computing [1] is a brain-inspired computing paradigm based on representing information w2 KB (308 words) - 20:12, 9 February 2020
- ...wed by log-energy feature extraction, with Riemannian covariance matrices [1] achieving the highest classification accuracy of 75.47% on the BCI competi * [https://ieeexplore.ieee.org/document/8494247/] Pullini et al., Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Proce3 KB (372 words) - 11:09, 21 July 2020
- ...ided into 2 tracks, each one offering a Master’s thesis (or similar) for 1-5 KB (647 words) - 08:32, 23 February 2023
- 1. Study the SNN computing paradigm, and select a population of SNN candidate [1] Event-based Vision: A Survey4 KB (644 words) - 19:10, 29 January 2021
- ...posed PPAC (Parallel Processor in Associative Content-Addressable Memory) [1], a PIM architecture that is able to accelerate several operations that hav [1] O. Castañeda, M. Bobbett, A. Gallyas-Sanhueza, and C. Studer, "PPAC: A Ve7 KB (882 words) - 14:33, 28 July 2021
- ...signed at ETH Zürich and University of Bologna under the name Zero-riscy [1], and has been taped out multiple times in a mix of academic and industry p <!-- : Looking for 1 Interested Master Student (Semester Project) -->5 KB (666 words) - 09:45, 28 August 2020
- ...signed at ETH Zürich and University of Bologna under the name Zero-riscy [1], and has been taped out multiple times in a mix of academic and industry p ...in terms of cycles per instruction compared to bigger cores such as RI5CY [1]. On one hand the performance of Ibex is lower due to the simpler pipeline4 KB (639 words) - 09:45, 28 August 2020
- Epilepsy is a severe and prevalent chronic neurological disorder affecting 1–2% of the world’s population. One-third of epilepsy patients continue t ...s to train the models in a self-supervised way using contrastive learning [1], which was able to learn different sleep states. This will not only improv5 KB (650 words) - 20:01, 10 March 2024
- ...ing approaches are arising for efficient processing such as InceptionTime [1], MultiScale-CNN [2], and Temporal Convolutional Networks (TCN) [3]. 1 - Development in a high-level programming language (python) of different de6 KB (780 words) - 20:02, 10 March 2024
- ...recently designed an accelerator called Reconfigurable Binary Engine (RBE)[1]. The RBE architecture exploits two computational concepts, explained below6 KB (814 words) - 09:55, 8 March 2023
- ...riety of application areas such as machine learning and signal processing [1]. Most importantly, it is very appealing for making energy-efficient deep l ...vel hardware experiments on phase-change memory chips comprising more than 1 million devices to high-level algorithmic development in a deep learning fr5 KB (628 words) - 12:51, 17 April 2020
- ...tly a hot research topic in wireless communication. Many different linear [1], [2] and non-linear (e.g., deep learning based [3]) jammer mitigation algo [1] Q. Yan, H. Zeng, T. Jiang, M. Li, W. Lou, and Y. T. Hou "Jamming resilient5 KB (662 words) - 13:31, 10 May 2023
- ...g on the electrode's surface), high-frequencies of operation are required [1-3]. Within this framework, we consider the biochip described in [1-3]. The chip is mounted on a PCB adaptor (see picture), that provides all t5 KB (620 words) - 07:56, 26 May 2020
- ...in contact with a virus, and corresponding CBCM charge/discharge switches [1].]] ...g on the electrode's surface), high-frequencies of operation are required [1-3].3 KB (394 words) - 13:27, 26 May 2020
- * Analyse the data and apply a standard classifier [1,2] : Looking for 1-2 students for a semester project or group project.5 KB (669 words) - 15:27, 23 October 2023
- ...crete Wavelet Transform (DWT) or Non-Negative Matrix Factorization (NNMF) [1]. Due to its recent success, however, convolutional neural networks (CNNs)5 KB (636 words) - 20:01, 10 March 2024
- ...consuming. In this thesis, the student explores data augmentation methods [1][2] to improve the learning in biosignal classification tasks. Applications4 KB (585 words) - 19:59, 10 March 2024
- ...processors for brain-machine interfacing and neuroprosthetic applications [1].5 KB (619 words) - 19:58, 10 March 2024
- 2.0 nano-drone[1][2][3]. * Familiarize with Crazyflie (CF) firmware (1 weeks)8 KB (1,117 words) - 22:17, 26 January 2022
- ...ng systems is represented by the combination of global and local planning [1]. On the one hand, global planning sees “the whole picture” (for exampl ...e deployment of all sensors and computational modules aboard a Crazyflie 2.1 nano-drone [4], equipped with a powerful AI-deck [5] companion board that e4 KB (571 words) - 12:11, 27 January 2022
- ====Phase 1==== 1. Get familiar with the already existing LPR UWB as described on the IEEE St8 KB (1,139 words) - 19:10, 29 January 2021
- ...deployment. A viable option are memory augmented neural networks (MANNs) [1] which augment CNNs with an external binary memory. This opens up a large v5 KB (662 words) - 21:31, 9 January 2022
- ...lly, SNNs have shown to extract robust features from event-driven cameras [1], whereas HDC have proven to be capable to update their simple to cope with : Looking for 1-2 students for a semester project.5 KB (707 words) - 09:23, 16 September 2021
- ...or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). ...eks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''11 KB (1,337 words) - 10:54, 25 January 2024
- #Redirect [[A Snitch-based Compute Accelerator for HERO (M/1-2S)]]66 bytes (10 words) - 21:47, 10 November 2020
- 1. Familiarizing with the Halide language and the architecture of HERO (~2 pe ...ide environment on an FPGA with a set of custom image processing kernels (~1 person week)5 KB (737 words) - 17:26, 2 November 2020
- ...its APB- and DMA-based peripheral subsystem. [<nowiki/>[[#ref-pulpissimo|1]]] ]] ...ch. Get familiar with the existing PULPissimo [<nowiki/>[[#ref-pulpissimo|1]]] peripheral system and its peripherals to analyze their behavior, config11 KB (1,675 words) - 15:40, 15 March 2021
- <!-- (M/1-2S): A Snitch-based Compute Accelerator for HERO --> ...pen-source Parallel Ultra-Low Power (PULP) platform [<nowiki/>[[#ref-pulp|1]]] , which provides a multicore cluster based on the open RISC-V instructio11 KB (1,617 words) - 23:59, 6 February 2021
- : Looking for 1-2 Semester/Master students4 KB (513 words) - 14:16, 24 November 2021
- [[File:FBNet.png|400px|thumb|right|Differentiable Neural Arcitechture Search [1]]] ...Many different flavors of NAS exist, such as being differentiable or DNAS [1], NAS methods that utilize evolutionary algorithms, and NAS methods that us6 KB (784 words) - 21:34, 9 January 2022
- [[File:FBNet.png|400px|thumb|right|Differentiable Neural Arcitechture Search [1]]] ...Many different flavors of NAS exist, such as being differentiable or DNAS [1], NAS methods that utilize evolutionary algorithms, and NAS methods that us5 KB (760 words) - 01:39, 10 January 2022
- ...|thumb|350px|Block diagram of the ''Snitch'' cluster; the DMA core is CC N+1.]]4 KB (563 words) - 20:08, 15 February 2021
- #Redirect [[LLVM and DaCe for Snitch (1-2S)]] ...ttps://scholar.google.com/scholar?oi=bibs&cluster=8341123140790442037&btnI=1&hl=de Snitch]2 KB (333 words) - 20:05, 15 February 2021
- #Redirect [[LLVM and DaCe for Snitch (1-2S)]] ...ttps://scholar.google.com/scholar?oi=bibs&cluster=8341123140790442037&btnI=1&hl=de Snitch]3 KB (386 words) - 20:06, 15 February 2021
- ...the PULP project and capable of booting Linux. The current Ariane backend [1] is built around a scoreboard (essentially a small ROB) which took over mor ...l goal is to have a reasonably advanced superscalar core running at around 1.5GHz operating frequency in a modern 12nm process with IPCs expected from t3 KB (474 words) - 15:50, 17 November 2021
- ...ely used both in academia and industry. Ariane features a write-back level 1 data cache, which temporally stores a copy of recently accessed memory cont * [1] https://github.com/openhwgroup/cva63 KB (395 words) - 16:32, 15 November 2022
- ...knowledge of the System Verilog or VHDL language and circuit design (VLSI 1)3 KB (449 words) - 08:41, 17 February 2021
- 1. Install MemPool and test it on different configurations ...RTL language (SystemVerilog or Verilog or VHDL). Having followed the VLSI 1 course is recommended.8 KB (1,196 words) - 10:41, 6 July 2021
- : Type: Bachelor's Thesis or Semester Project for 1-2 student(s)2 KB (261 words) - 12:24, 12 January 2023
- .... A deep learning pipeline for KWS integrating MFCC is presented in Figure 1. ...gram [[#ref-kim2021|[4]]]. Moreover, surveys [[#ref-alim2018|[1]]] [[#ref-sharma2020|[7]]] [[#ref-choi2021|[3]]] [[#ref13 KB (1,815 words) - 13:31, 15 February 2024
- #REDIRECT [[Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)]]82 bytes (11 words) - 17:40, 2 November 2020
- ...IMO (DM-MIMO) systems are channel charting [3], fingerprinting techniques [1], and triangulation/trilateration [4]. ...ied to user positioning, but require extensive training with labeled data [1]. Triangulation and trilateration as described in [4], estimate the user’8 KB (931 words) - 17:27, 23 November 2021
- ...FPGA fabric, with a hard ARM Cortex-A multicore host processor [1]. Figure 1 shows the block diagram of HERO. It features a shared virtual memory system ...RTL language (SystemVerilog or Verilog or VHDL). Having followed the VLSI 1 course is recommended.6 KB (902 words) - 19:07, 20 January 2021
- <!-- (1-2S): An RPC DRAM Implementation for Energy-Efficient ASICs --> .... These ''reduced pin count DDR'' (RPC DDR) [[[#ref-rpc_dram_website|1]]] memories only require a simple on-chip PHY and can operate with regular8 KB (1,214 words) - 15:18, 9 July 2021
- ...e state-of-the-art in feature map compression algorithms, especially EBPC [1] [1]: [https://arxiv.org/abs/1908.11645 EBPC: Extended Bit-Plane Compression fo3 KB (438 words) - 08:41, 17 February 2021
- ...t in smartphone cameras over the last decade [<nowiki/>[[#ref-Skafisk2017|1]]]. These image sensors, boasting tens of millions of pixels, create a huge ...For more details refer to [http://eda.ee.ethz.ch/index.php/Design_review (1)].9 KB (1,311 words) - 00:08, 13 March 2021
- ...communication promises to be the true enabler of the wireless Gbits/s era [1]. ...cell-free massive MIMO with mmWave has been barely explored until now. In [1], channel estimation in this specific scenario is carefully studied. Low-co7 KB (882 words) - 21:34, 13 July 2022
- ...ow on, the expectation is to have more than 50 billions connected devices [1] in the network. To meet this demand, technologies that improve energy effi In [1], a RIS is used in the downlink of a MIMO system to investigate the improve8 KB (1,011 words) - 12:25, 16 November 2023
- #Redirect [[A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)]]2 KB (365 words) - 20:03, 15 February 2021
- : Looking for 1-2 Semester/Master students5 KB (653 words) - 11:08, 12 November 2020
- ...uired from this first step with “Finite-Alphabet Baseband Processing” [1], a novel beamforming paradigm that uses low-resolution numbers to reduce p [1] O. Castañeda, S. Jacobsson, G. Durisi, T. Goldstein, and C. Studer, "Fini6 KB (829 words) - 11:37, 12 November 2020
- ...obtain the same solution quality with only half the number of iterations! [1] ...tañeda, S. Jacobsson, G. Durisi, and C. Studer, "Neural-Network Optimized 1-bit Precoding for Massive MU-MIMO," IEEE 20th International Workshop on Sig6 KB (748 words) - 13:57, 12 November 2020
- ...algorithms are necessary when targetting aggressive quantisation schemes (1-bit, 2-bits). ...er obtained by projecting a full-precision network on a constrained space [1, 2], or by progressively “hardening” a relaxed version of a QNN towards6 KB (868 words) - 14:15, 15 February 2024
- ...ed towards the parameters of DNNs that use quantised activation functions [1]. [1] G. P. Leonardi and M. Spallanzani, “Analytical aspects of non-differenti4 KB (596 words) - 14:06, 15 February 2024
- : Looking for 1-2 Semester/Master students3 KB (501 words) - 19:40, 16 November 2020
- ...is an open-source, 6-stage, 64-bit, in-order RISC-V core developed at IIS [1]. It is capable of booting Linux and it is widely used both in academia and * [1] https://github.com/openhwgroup/cva63 KB (391 words) - 08:49, 21 June 2022
- ...ng beamspace processing algorithms that have been developed very recently [1,2]. ...estimation and data detection algorithms, such as BEACHES, COMP, and EOMP [1], [3]. The goals are to (i) identify the key processing bottlenecks and (ii4 KB (620 words) - 00:16, 11 January 2022
- In recent research [1], we explored the opportunity of adding streaming semantic to the processor proposals [1,2] in the gem5 simulator [3], on top of an existing model of an ARM server-7 KB (1,003 words) - 13:25, 10 August 2021
- ...Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) --> ...Ariane cores, and die-to-die serial link. [[#ref-zaruba2020manticore|[1]]]]]11 KB (1,602 words) - 15:19, 9 July 2021
- ...he multi-core system according to Amdahl’s law [[#ref-Hennessy2017|[1]]]. Efficient means of synchronization are therefore of great importanc <span class="csl-left-margin">[1] </span><span class="csl-right-inline">J. L. Hennessy and D. A. Patters12 KB (1,864 words) - 12:08, 29 August 2022
- * After a comparison with emFloat, a commercial optimized FP library [1], it was clear that the RVfplib division can be further optimized both in c [1] emFloat: https://www.segger.com/products/development-tools/runtime-library4 KB (536 words) - 13:25, 12 August 2022
- ...r variable frequency operation. IEEE transactions on power electronics, 29(1), 287-301.'')]]2 KB (296 words) - 11:36, 20 August 2021
- ...count in smartphone cameras over the last decade [[#ref-Skafisk2017|[1]]]. These image sensors, boasting tens of millions of pixels, create a ...coarse grained reconfigurable architecture (CGRA). As shown in [[#fig:cgra|1]], these architectures implement a systolic array of configurable processin13 KB (1,887 words) - 15:51, 17 November 2021
- Ara is working well, with a prototype achieving an operating frequency of 1 GHz in a modern technology. 1. Familiarize with the RISC-V Vector Extension and the Ara source code. (~26 KB (916 words) - 15:25, 9 July 2021
- '''Ariane''' (recently renamed to CVA6, [1]) is an open-source, general-purpose RISC-V CPU architecture which implemen * [1] https://github.com/openhwgroup/cva67 KB (1,122 words) - 15:21, 9 July 2021
- <!-- (1-2S/B): A Snitch-Based SoC on iCE40 FPGAs --> With the iCE40 FPGA family, Lattice Semiconductor [[[#ref-fpga|1]]] provides FPGAs with the world’s smallest form factor, optimized for u8 KB (1,220 words) - 15:18, 9 July 2021
- ...adoption of the open RISC-V instruction set [[#ref-waterman2014riscv|[1]]] has reinvigorated computer architecture in teaching and research ali ...t familiar with the RISC-V base integer ISA [[#ref-waterman2014riscv|[1]]] and our specification.10 KB (1,521 words) - 15:21, 9 July 2021
- <!-- LLVM and DaCe for Snitch (1-2S) --> The Snitch ecosystem [[#ref-zaruba2020snitch|[1]]] targets energy-efficient high-performance systems. It is built aroun11 KB (1,519 words) - 15:20, 9 July 2021
- ...parameters and activations are quantized to one of three values: -1, 0 or 1. At IIS, we have been collecting experience with TNNs for a good while and5 KB (768 words) - 15:14, 4 August 2022
- ...ing to a certain class. A schematic of a KWS system can be seen in Figure 1. ...'e.g''. <span>TCNs, RNNs, transformers</span>) [[#ref-deAndrade2018|[1]]]–[[#ref-Zeng2019|[3]]]. These approaches obtained high accu11 KB (1,610 words) - 11:00, 14 November 2022
- ...by traditional supervised machine learning methods (such as random forest [1], support vector machines [6], Bayesian analysis [8], artificial neural net 1 - Development in a high-level programming language (python) of graph neural10 KB (1,306 words) - 19:58, 10 March 2024
- ...d hiding have been developed [https://dl.acm.org/doi/book/10.5555/1208234 #1]. The goal of this project is to 1) take an existing open-source implementation of a cryptographic device, e.g6 KB (849 words) - 18:43, 23 November 2021
- The Advanced Encryption Standard (AES) [1] is an encryption algorithm used in many of today's applications. It operat * [1] http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.197.pdf2 KB (267 words) - 19:14, 6 December 2021
- ...rs and ISA extensions for existing RISC-V processor cores. Just like Ibex [1], the work for this extension interface has been started at ETH Zürich and : Looking for 1-2 Interested Master Students (Semester Project)6 KB (835 words) - 12:52, 27 April 2021
- ...ulky. RC-based timer is a good alternative that can be integrated on-chip [1][2][3]. Capacitors are relatively insensitive to temperature change, so it 1. Study prior art2 KB (293 words) - 11:06, 21 February 2022
- ...oring motor function while reducing the damage caused by the implantation [1][2]. However, such system also poses stringent constraints on the power con Researchers have developed mm-scale neural probe [1][2] and efficient algorithms [3][4] to tackle the problem. Our goal is to h4 KB (519 words) - 16:16, 9 January 2023
- : Looking for 1 Master/ industrial internship student4 KB (606 words) - 13:53, 23 June 2021
- Researchers have developed mm-scale implantable neural probe [1][2] aiming to restore motor function while reducing the damage caused by th 1. Study prior art, including and not limited to LSM, SNN5 KB (662 words) - 20:05, 10 March 2024
- Looking for 1-2 students for a Semester project, or potentially a single student for a Ma5 KB (784 words) - 11:32, 29 October 2021
- ...NNs), where all weights and activations are quantized to 3 levels: {-1, 0, 1}.3 KB (404 words) - 09:54, 8 March 2023
- : Looking for 1 Master student4 KB (546 words) - 13:07, 23 July 2021
- ...loping our own many-core system called MemPool [[#ref-Cavalcante2020|[1]]], [[#ref-Riedel2021|[2]]]. It boasts 256 lightweight 32-bit S [1] M. Cavalcante, S. Riedel, A. Pullini, and L. Benini, “MemPool: A sha10 KB (1,434 words) - 17:20, 2 August 2021
- [1] O.Shachamand, M.Reynders, "Pixel Visual Core: image processing and machine ...loating-Point Intensive Workloads," IEEE TRANSACTIONS ON COMPUTERS, pp.1–1, feb 2020. [Online]. Available: http://arxiv.org/abs/2002.1014311 KB (1,609 words) - 10:00, 30 June 2022
- ...ts following predefined address patterns. Recent architectural extensions [1-2] propose handling such streams in hardware. This frees processors from ex In our group, we developed Stream Semantic Registers (SSRs) [1]. These map memory streams directly to general-purpose registers in a RISC-3 KB (425 words) - 17:32, 17 November 2021
- <!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> ...ts following predefined address patterns. Recent architectural extensions [1-5] propose handling such streams in hardware. This frees processors from ex4 KB (557 words) - 16:14, 6 November 2022
- ...r Unattended Ground Sensor Nodes. IEEE Journal of Solid-State Circuits, 53(1), 261–274. https://doi.org/10.1109/JSSC.2017.2728787 ..., & Member, S. (2018). A 1-V 0 . 25- μ W Inverter Stacking Amplifier With 1 . 07 Noise Efficiency Factor. 53(3), 896–905.3 KB (379 words) - 15:19, 19 December 2022
- ...ct, the student works with the Temple University (TUH) EEG Corpus dataset [1] labeled with multiple artifact types. The data is labeled channel-wise, me ...ified as an artifact such that the labeled dataset has the dimension of (N,1) -> where N is the total number of samples we have.4 KB (561 words) - 15:25, 23 October 2023
- : Type: Bachelor's Thesis or Semester Project for 1-2 student(s)2 KB (249 words) - 17:18, 14 September 2021
- : Looking for 1 or several Master student3 KB (387 words) - 17:04, 16 September 2021
- We are looking for 1 Master student.5 KB (659 words) - 14:08, 15 February 2024
- .... A deep learning pipeline for KWS integrating MFCC is presented in Figure 1. ...gram [[#ref-kim2021|[4]]]. Moreover, surveys [[#ref-alim2018|[1]]] [[#ref-sharma2020|[7]]] [[#ref-choi2021|[3]]] [[#ref12 KB (1,688 words) - 11:00, 14 November 2022
- ...ging to a certain class. A schematic of a KWS system can be seen in Figure 1. ...eyword Spotting in Any Language", Mazumder et al. [[#ref-mazumder2021|[1]]] propose a few-shot learning approach towards fine-tuning a classific12 KB (1,869 words) - 17:37, 1 September 2023
- ...e EDA tool-flow for asynchronous VLSI design developed at Yale University [1], in order to design, implement, and fabricate a low-density parity check ( [1] S. Ataei et al., “An Open-Source EDA Flow for Asynchronous Logic,” IEE6 KB (725 words) - 17:36, 20 October 2021
- Looking for 1-2 students for a Semester project. If you have any questions, suggestions f8 KB (1,101 words) - 20:04, 10 March 2024
- <!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> ...s following a predefined address pattern. Recent architectural extensions [1,2] propose handling such streams in hardware, which brings many benefits: i3 KB (431 words) - 16:13, 6 November 2022
- #Redirect [[Streaming Integer Extensions for Snitch (M/1-2S)]]62 bytes (9 words) - 16:49, 20 November 2021
- ...posed PPAC (Parallel Processor in Associative Content-Addressable Memory) [1], a PIM architecture that is able to accelerate several operations that hav [1] O. Castañeda, M. Bobbett, A. Gallyas-Sanhueza, and C. Studer, "PPAC: A Ve7 KB (933 words) - 19:29, 21 November 2021
- ...merly Ariane) is a 6-stage, 64-bit, in-order RISC-V core developed at IIS [1]. It is capable of booting Linux and it is widely used both in academia and [1] [https://github.com/openhwgroup/cva6 CVA6: CVA6 RISC-V CPU] (GitHub reposi3 KB (440 words) - 10:53, 15 November 2022
- [[File:Snitch-bd.png|thumb|350px|The ''Snitch'' cluster [1] couples tiny RISC-V ''Snitch'' cores with performant double-precision FPUs The Snitch system [1] targets energy-efficient high-performance computing. It is built around th4 KB (567 words) - 13:57, 7 September 2022
- The Snitch ecosystem [1] targets energy-efficient high-performance systems, like the Manticore conc * Looking for 1 Semester or 1 Master student4 KB (613 words) - 10:13, 2 November 2022
- <!-- Counter-based Fast Power Estimation using FPGAs (M/1-3S) --> ...ly approximated by randomly selecting a handful of signals to be observed [1].5 KB (688 words) - 13:51, 27 October 2022
- ...trollers, operating with a single US channel and consuming less than 20mW [1]. ...gle-channel ultrasound data platforms, such as the probe developed at IIS [1]3 KB (336 words) - 19:03, 6 December 2023
- #REDIRECT [[Adding Linux Support to our DMA Engine (1-2S/B)]]61 bytes (11 words) - 17:27, 19 November 2021
- ...of cycles it takes to execute said piece of code. Non-blocking algorithms [1] [2] [3] do away with critical sections and instead use atomic read-modify- [1] [https://en.wikipedia.org/wiki/Non-blocking_algorithm Non-blocking Algorit4 KB (508 words) - 18:59, 10 January 2022
- [[File:rt_system.png|center|600px|High-level view of a Real-Time system [1]]] [1] Kopetz H., ''Real-Time Systems'', 19964 KB (518 words) - 09:54, 10 January 2022
- The Snitch ecosystem [1] targets energy-efficient high-performance systems. It is built around the [1] https://ieeexplore.ieee.org/document/92165524 KB (554 words) - 09:49, 17 August 2022
- ...capable of simulating our manycore architectures [[#ref-Banshee2021|[1]]]. It is written in Rust, making it easy to extend, and thanks to its <span class="csl-left-margin">[1] </span><span class="csl-right-inline">PULP Team, <span>“<span>Banshe10 KB (1,428 words) - 13:31, 27 October 2022
- <!-- Streaming Integer Extensions for Snitch (M/1-2S) --> The Snitch ecosystem [1] targets energy-efficient high-performance systems. It is built around the6 KB (770 words) - 14:19, 15 September 2022
- PPAC (Parallel Processor in Associative Content-Addressable Memory) [1] is a hardware accelerator that aims at accelerating not only matrix-vector ...C only consider matrix-vector products in the context of machine learning [1] and equalization for wireless communications [2]. In this project, the stu7 KB (804 words) - 19:45, 21 November 2021
- ...th the OS via the System Control and Management Interface (SCMI) protocol [1], which provides a set of OS-agnostic standard SW and HW interfaces [2] for * Get to know the protocol by reading the SCMI specification document [1]3 KB (467 words) - 13:55, 12 October 2022
- <!-- Desigining a Power Mangement Unit for PULP SoCs (M/1-2S) --> [1] https://ieeexplore.ieee.org/document/92165523 KB (420 words) - 11:22, 18 August 2022
- ...pheral Event Linking System For Real-Time Capable Energy-Efficient SoCs (M/1-2S) -->8 KB (1,127 words) - 19:54, 1 March 2023
- ...or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). ...eks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''5 KB (614 words) - 09:49, 15 January 2024
- 1. Study prior art3 KB (381 words) - 19:19, 25 November 2021
- ...and tested application class 6-stage RISC-V CPU capable of booting Linux [1]. The ultimate goal is to compare the performance of a broad set of functio * [1] CVA6 (fka Ariane) Github Repository.[[https://github.com/openhwgroup/cva66 KB (905 words) - 21:41, 6 December 2021
- <!--Watchdog Timer for PULP (1-2S/B) --> <div> [1] [https://github.com/riscv-non-isa/riscv-watchdog RISC-V Watchdog Specifica2 KB (337 words) - 08:49, 21 June 2022
- <!-- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) --> ...r processors are complex and require an immensely large circuit area. Ara [1], our in-house vector Processor (RISC-V Vector Extension Version 0.10) e.g.3 KB (384 words) - 12:13, 21 June 2022
- <!-- Enhancing our DMA Engine with Fault Tolerance (1-2S/B) --> * Stretch goal: add AXI5 compliance (parity check) [1]2 KB (348 words) - 13:16, 24 October 2023
- [[File:FBNet.png|400px|thumb|right|Differentiable Neural Arcitechture Search [1]]] ...Many different flavors of NAS exist, such as being differentiable or DNAS [1], NAS methods that utilize evolutionary algorithms, and NAS methods that us5 KB (705 words) - 12:58, 16 January 2023
- [1] https://developer.arm.com/documentation/den0056/latest4 KB (515 words) - 15:06, 5 August 2022
- PULP (Parallel Ultra-Low-Power) [1] is an open-source multi-core computing platform. It consists of an advance 1. '''Synchronous (blocking) offload:''' the manager core has to wait (poll)6 KB (835 words) - 16:27, 7 July 2023
- ...% of adults with hypertension are unaware that they have the condition.”(1) The blood pressure is a challenging parameter to measure outside the docto We are looking for 1-2 motivated Bachelor/Semester/Masters Thesis students4 KB (535 words) - 16:56, 12 July 2022
- ...ation scenario, Tag 0 performs ranging with each anchor, and only then Tag 1 starts ranging with the anchors. The drawback of this scheme is that it can ...ncurrent ranging." ACM Transactions on Sensor Networks (TOSN) 16.4 (2020): 1-41.4 KB (611 words) - 16:58, 4 February 2022
- Video 1: https://www.youtube.com/watch?v=cU40pqu24bw [[File:dronepic.png|thumb|center|300|The Crazyflie 2.1 featuring our custom deck based on the multi-zone ToF sensor]]4 KB (604 words) - 14:07, 10 March 2022
- ...trinsic computational capabilities and flexibility inherited from the Cray-1 processor. For example, “FUGAKU”, the most performant supercomputer in ...ll, some critical instructions are missing to claim FULL compliance to RVV 1.0 and run every vector program produced by an RVV compiler.4 KB (580 words) - 11:37, 3 November 2023
- ...a reduction of the average number of multiplications performed per second [1,2]. For uplink data detection and downlink precoding, we have recently desi ...rix-vector product engine which is designed based on the idea proposed in [1].5 KB (662 words) - 17:14, 26 September 2023
- ...which makes the beamspace-domain representation of channel vectors sparse [1]. This beamspace-domain sparsity provides an opportunity for designing low- ...enerator, so that twiddle factors can be programmed to perform the desired 1-D or 2-D FFT operations. We will then implement the resulting 2-D FFT core5 KB (771 words) - 16:32, 8 February 2022
- ...to efficient hardware implementations of data detectors for massive MIMO [1,2,3]. However, most of the research has focused on implementing the detecto [1] M. Wu, B. Yin, G. Wang, C. Dick, J. R. Cavallaro, and C. Studer, “Large-6 KB (843 words) - 17:16, 26 September 2023
- [1] Y. Dan et al., “LTE-Based Passive Radar for Drone Detection and its Expe : Looking for 1-2 Semester/Bachelor/Master students5 KB (564 words) - 16:12, 9 February 2022
- ...detect activities inside a building using through-the-wall radar imaging [1]. First, the project will explore the main types of radar operating in the [1] P. K. Nkwari, “Through-the-Wall Radar Imaging: A Review,” IETE Technic5 KB (586 words) - 16:15, 9 February 2022
- [[File:Uwb_gap8.png|thumb|right|300|The Crazyflie 2.1 with Philip Wiese's semester project - a deck with UWB and GAP8, the camera .../www.bitcraze.io/products/crazyflie-2-1/ <nowiki> [1] Bitcraze CrazyFlie 2.1</nowiki>]3 KB (507 words) - 15:09, 11 February 2022
- <!-- Creating Extension and Evaluation of TinyDMA (1-2S/B/2-3G) --> Currently, TinyDMA is based on the AMBA AXI4[1] on-chip communication standard. Next to AXI4, simpler protocols are used t2 KB (312 words) - 09:35, 3 November 2023
- ...ship of deep learning-based autonomous navigation engines for nano-drones [1,2]. This shallow convolutional neural network (CNN) runs aboard a 27-grams More in the details, the nano-drone platform is the Bitcraze Crazyflie 2.1 [4] extended by a powerful multicore System-on-Chip (SoC), the parallel ult4 KB (550 words) - 21:25, 15 February 2022
- We are looking for 1 Master student.7 KB (831 words) - 19:36, 12 January 2023
- We are looking for 1 Master student.6 KB (839 words) - 14:08, 15 February 2024
- ...rocess that aims at checking both temporal violations and functional bugs [1]. 1. '''Cycle Contention Stack (CCS):''' monitors working and contention cycles6 KB (869 words) - 14:47, 7 July 2023
- ...e designed and assembled. Example solutions include string-based phantoms [1] or liquid-flow phantoms [2]. * design and implementation of US doppler phantom (taking inspiration from [1][2])3 KB (363 words) - 17:18, 3 May 2024
- ...rgy-Scalable Oscillator Collapse-Based Comparator with Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC,” IEEE J. Solid-State Circuits, vol. 52,2 KB (313 words) - 13:36, 14 February 2024
- This project follows the trail of the PULP-Dronet research project [1,2], deep learning-based autonomous navigation engines for nano-drones. This ...ims to enhance the autonomous navigation capabilities aboard a Crazyflie 2.1 nano-drone [3] by optimizing the onboard execution of minimal variants of t4 KB (489 words) - 14:33, 17 May 2022
- : Looking for 1-2 Semester/Master students : VLSI 11 KB (138 words) - 13:34, 25 May 2022
- : Looking for 1-2 Semester/Master students : VLSI 1990 bytes (143 words) - 14:36, 25 May 2022
- : Looking for 1-2 Semester/Bachelor/Master students4 KB (503 words) - 13:54, 30 May 2022
- : Looking for 1-2 Semester/Master students4 KB (470 words) - 18:16, 27 May 2022
- : Looking for 1 Semester/Master students4 KB (492 words) - 10:55, 16 June 2022
- :Looking for 1 master or semester student3 KB (365 words) - 10:19, 31 May 2022
- on insights gained in our recent works on low-resolution jammer mitigation [1], [2]. After familiarizing yourself with these works, you will develop a li [1] G. Marti, O. Castañeda, and C. Studer, "Jammer Mitigation via Beam-Slicin5 KB (662 words) - 13:33, 10 May 2023
- ...d the next generation of wearable ultra low power (ULP) ultrasound probes [1], which is based on an MSP430 MCU for handling the ultrasound signal genera3 KB (366 words) - 15:10, 23 October 2023
- ...ng Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) -->2 KB (282 words) - 09:27, 3 November 2023
- ...ng a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) -->2 KB (226 words) - 14:22, 27 February 2024
- ...age (SystemVerilog or Verilog or VHDL). Having followed/following the VLSI 1 course is recommended.8 KB (1,239 words) - 12:36, 29 January 2024
- ...y chain. Existing standards for IoT communication systems include LoRaWAN [1], mioty [2,3], or LTE-M [4]. The mioty standard is a promising candidate in [1] LoRa Alliance, "LoRa Alliance®," [Online]. Available:5 KB (586 words) - 15:34, 11 July 2022
- ...a few. This project follows the trail of the PULP-Dronet research project [1,2]: a deep learning-based autonomous navigation engine for nano-drones. As * [1] D. Palossi et al., "A 64-mW DNN-based visual navigation engine for autonom4 KB (505 words) - 18:25, 26 July 2022
- <!-- Creating Towards Formal Verification of the iDMA Engine (1-3S/B) -->2 KB (272 words) - 10:21, 3 November 2023
- <!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) -->2 KB (214 words) - 09:39, 23 August 2023
- ...tems matters (automotive and aerospace above all). Among these, Zephyr OS [1] is a promising scalable real-time operating system with small memory footp [1] https://github.com/zephyrproject-rtos/zephyr3 KB (483 words) - 15:28, 19 February 2024
- ControlPULP is an open-source HW/SW platform based on PULP [1], a parallel embedded MCU implementing the RISC-V ISA. ControlPULP has been [1] https://github.com/pulp-platform/pulp3 KB (438 words) - 16:51, 5 August 2022
- [[File:Fpu_block_diagram.png|thumb|300px|FPnew block diagram [1]. Each operation group block can be instantiated through a parameter. In th ...le highly-parametrized open-source floating-point unit (FPU) called FPnew [1,2] has been developed at IIS.3 KB (380 words) - 14:27, 15 May 2023
- ...at runtime (On-Demand Redundancy Grouping, ODRG)[[#ref-Rogenmoser2022|[1]]]. [1] M. Rogenmoser, N. Wistoff, P. Vogel, F. Gürkaynak, L. Benini, “On-D4 KB (497 words) - 14:15, 29 June 2023
- == 1 Project Description and Timeline == https://www.mdpi.com/2079-9292/9/1/134/pdf4 KB (549 words) - 11:35, 3 November 2023
- The Snitch ecosystem [1] targets energy-efficient high-performance systems. It is built around the [1] https://ieeexplore.ieee.org/document/90684653 KB (349 words) - 14:34, 15 August 2022
- <!-- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) --> ...arrays in fixed, possibly irregular patterns relative to each grid point [1]. They are widespread in high-performance computing (HPC) and underly vario3 KB (431 words) - 22:29, 19 January 2023
- ...should choose how many ports each slave gives access to the masters (e.g., 1 port from the SPI, 4 ports from memory, etc.), and whether the access is gi ...ts are used interleaved if the base address goes to port 0, base+1 to port 1, ..., base+4 to port0 again, etc.8 KB (1,304 words) - 14:44, 23 October 2023
- ...eating Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) -->3 KB (392 words) - 09:38, 3 November 2023
- .../asic.ethz.ch/2022/Neo.html Neo], feature a Linux-capable '''CVA6''' core [1] and a '''Serial Link''' off-chip interface. While the chips contain a few * [1] https://github.com/openhwgroup/cva63 KB (416 words) - 10:49, 25 January 2024
- * Experience with the System Verilog language, VLSI 12 KB (308 words) - 14:30, 8 March 2023
- ...trollers, operating with a single US channel and consuming less than 20mW [1]. ...nd in a synchronized way US and PPG data. The ultra-low-power US probe of [1] will be considered as starting design point, and an integrated prototype a3 KB (354 words) - 19:02, 6 December 2023
- * Type: Semester Thesis (2 students), Master Thesis (1 student)6 KB (846 words) - 16:50, 3 November 2022
- * Type: Master Thesis (1 student) [[File:maddness_floorplan.png|thumb|350px|Figure 1: Clock layout of the MADDness accelerator using ASAP7 technology]]6 KB (823 words) - 16:32, 3 November 2022
- ...the sparse update scheme proposed by Lin et al.[[#ref-linondevice2022|[1]]], evaluating it on MobileNetV2 [[#ref-mobilenetsandler2018|[2] <span class="csl-left-margin">[1] </span><span class="csl-right-inline">Lin, Ji and Zhu, Ligeng and Chen7 KB (935 words) - 13:29, 2 November 2023
- ...g., as used for the lead synthesizer in Harold Faltermeyer's Fletch Theme [1]. While it is known how to synchronize oscillators generating sawtooth or r [1] https://www.youtube.com/watch?v=r-lu0vjHSO05 KB (577 words) - 09:48, 5 October 2022
- ...trinsic computational capabilities and flexibility inherited from the Cray-1 processor. For example, “FUGAKU”, the most performant supercomputer in ...irst instance, you will familiarize with Ara and then study and understand 1) OpenHW Group’s verification environment and 2) Force RISC-V instruction5 KB (665 words) - 14:19, 18 October 2022
- ...trinsic computational capabilities and flexibility inherited from the Cray-1 processor. For example, “FUGAKU”, the most performant supercomputer in ...vector processor Ara, fresh from an update to the last specifications RVV 1.0. Ara behaves like a vector accelerator coupled with CVA6, one of the most5 KB (769 words) - 11:38, 3 November 2023
- ...e task of converting spoken speech into written words[[#ref-malik2021|[1]]], whilst the latter being the conversion of lip movement into written <li><p>'''Task 1: Familiarize yourself with the project specifics (1-2 Weeks)'''</p>11 KB (1,467 words) - 14:15, 1 March 2024
- ...the concept Manticore architecture that went on display at HotChips 2020 [1]. It couples a 64-bit RISC-V application-class out-of-order CVA6 core [2,3] [1] [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9296802 Manticor7 KB (944 words) - 10:47, 25 January 2024
- MemPool [[#ref-Cavalcante2020|[1]]] is a IIS-born many-core system, having 256 Snitch cores and 1024 ban [1] M. Cavalcante, S. Riedel, A. Pullini, and L. Benini, “MemPool: A sha3 KB (490 words) - 10:38, 2 November 2023
- ...do not fit on a single FPGA it might not be possible to have an exact 1-to-1 correspondence between the FPGA implementation and the original design. ...o the simulation and communicate with the processor through the JTAG port [1]. This method is extremely powerful, as the debugger provides us with the d8 KB (1,186 words) - 11:49, 13 March 2024
- <span class="csl-left-margin">[1] </span><span class="csl-right-inline">M. Cavalcante, S. Riedel, A. Pul3 KB (422 words) - 10:39, 2 November 2023
- ...pendent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) -->2 KB (335 words) - 13:58, 27 October 2022
- * Type: 2 Semester Thesis or 1 Master Thesis * Experience with System Verilog, VLSI 12 KB (252 words) - 14:43, 23 October 2023
- <!-- All the flavours of FFT on MemPool (1-2S/B) --> MemPool [[#ref-Cavalcante2020|[1]]] is a IIS-born many-core system, having 256 Snitch cores and 1024 ban3 KB (460 words) - 18:54, 9 November 2022
- [1] Ara: https://arxiv.org/pdf/1906.00478.pdf3 KB (470 words) - 11:34, 3 November 2023
- ...ing A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --> ...effort. A simple solution to this problem was introduced in 1996 with USB 1.0.2 KB (220 words) - 09:27, 3 November 2023
- ...s a High-performance Open-source Verification Suite for AXI-based Systems (1-3S/B) -->2 KB (290 words) - 09:38, 3 November 2023
- ...ndent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) -->2 KB (223 words) - 17:18, 18 December 2023
- ...ng a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) -->2 KB (250 words) - 09:31, 29 August 2023
- <!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) -->2 KB (249 words) - 09:36, 3 November 2023
- [[File:Fpu_block_diagram.png|thumb|300px|FPnew block diagram [1]. Each operation group block can be instantiated through a parameter. In th A low-precision FP dot product unit was recently developed at IIS [1], [2]. The module computes 8 or 16-bit dot products and accumulates the res2 KB (307 words) - 18:20, 3 November 2023
- <!-- Creating Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) --> TileLink (https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf) is a chip-scale interconnect standard providing multiple maste1 KB (181 words) - 09:36, 3 November 2023
- <!-- Creating Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) -->2 KB (297 words) - 09:36, 3 November 2023
- #REDIRECT [[All the flavours of FFT on MemPool (1-2S/B)]]57 bytes (11 words) - 18:54, 9 November 2022
- #REDIRECT [[Runtime partitioning of L1 memory in Mempool (1-2S/B)]]67 bytes (11 words) - 18:56, 9 November 2022
- : Looking for 1 Master student2 KB (302 words) - 18:47, 10 November 2022
- ...Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) --> ...heavily present in communications kernels. The Spatz [[#ref-Spatz2022|[1]]], a small and energy-efficient vector unit based on the RISC-V vector6 KB (775 words) - 11:57, 31 October 2023
- <!-- Resource Partitioning of RPC DRAM (1-2S/B) --> ...and low pin-count FPGAs and ASICs. These reduced pin count DDR (RPC DDR) [1] memories only require a simple on-chip PHY and can operate with regular di3 KB (379 words) - 09:32, 15 January 2024
- <!-- Resource Partitioning of Caches(1-2S/B) --> ...wn schemes such as randomization, cache-coloring and temporal partitioning[1] that can serve as starting point.3 KB (347 words) - 14:07, 4 March 2024
- ...ely used both in academia and industry. Ariane features a write-back level 1 data cache, which temporally stores a copy of recently accessed memory cont * [1] https://github.com/openhwgroup/cva62 KB (260 words) - 16:41, 15 November 2022
- ...lore innovative solutions that leverage the concept of repetition-in-time [1,2] (rather than spatial replication) to implement fault-detection (and corr [1] https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=42729825 KB (752 words) - 13:23, 24 October 2023
- [1] https://ieeexplore.ieee.org/abstract/document/9369027 ...M. Cavalcante, F. Schuiki, F. Zaruba, M. Schaffner, and L. Benini, "Ara: A 1-GHz+ scalable and energy-efficient RISC-V vector processor with multiprecis5 KB (651 words) - 20:42, 22 November 2022
- ...orks (LAN), metropolitan area networks (MAN) and wide area networks (WAN) [1]. It was commercially introduced in 1980 and first standardized in 1983 as ...om the original 2.94 Mbit/s [2] to the latest 400 Gbit/s, with rates up to 1.6 Tbit/s under development. The Ethernet standards include several wiring a5 KB (631 words) - 09:28, 3 November 2023
- ...s, including by the transmitting device. More information can be found in [1]. [1] CAN Bus: https://en.wikipedia.org/wiki/CAN_bus4 KB (554 words) - 09:28, 3 November 2023
- 1. Get to know more about Neural Recording state of the art work3 KB (466 words) - 10:26, 21 February 2024
- ...ame time. For discrete Qubits, the readout system usually works at the sub-1 GHz frequency range. However, for a compact footprint and the integration o2 KB (372 words) - 10:32, 14 February 2023
- ...uld provide a gain tuning range > 10 dB with a linear (in dB) step size of 1 dB.1 KB (213 words) - 10:44, 14 February 2023
- <li><p>'''Task 1 - Familiarise yourself with the project specifics (3-4 Weeks) '''</p>8 KB (1,271 words) - 15:04, 20 July 2023
- ...e task of converting spoken speech into written words[[#ref-malik2021|[1]]], whilst the latter being the conversion of lip movement into written <li><p>'''Task 1: Familiarize yourself with the project specifics (1-2 Weeks)'''</p>9 KB (1,283 words) - 17:44, 1 September 2023
- ...nal frequency division multiplexing (OFDM) is employed in the 5G standard [1], like many other standards such as LTE and IEEE 802.11 (WiFi). 1. Large number of basestation (BS) antennas in massive MIMO results in large4 KB (576 words) - 16:51, 8 January 2024
- : Looking for 1 Master student3 KB (460 words) - 17:28, 20 February 2023
- ...r variable frequency operation. IEEE transactions on power electronics, 29(1), 287-301.'')]] ...s to efficiently reduce the voltage from 3.7V (nominal battery voltage) to 1.5V (input of the LDO). The analog part of this DC/DC has already been desig2 KB (336 words) - 18:06, 1 March 2023
- : Looking for 1 semester/bachelor’s/master’s student.3 KB (446 words) - 15:56, 1 May 2023
- ...jammer mitation, such as Joint Jammer Mitigation and Data Detection (JMD) [1] or Jammer Mitigation via Subspace Hiding (MASH) [2]. However, these method [1] G. Marti and C. Studer, "Joint Jammer Mitigation and Data Detection for Sm3 KB (385 words) - 16:23, 20 September 2023
- We have already developed several novel methods for jammer mitigation [1], [2], but they all require successfull synchronization between the transmi [1] G. Marti and C. Studer, "Joint Jammer Mitigation and Data Detection for Sm2 KB (257 words) - 16:22, 20 September 2023
- <!-- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) --> [[File:occamy_block_diagram.png|thumb|Figure 1: A block diagram of the Occamy chip architecture]]8 KB (1,177 words) - 11:45, 13 March 2024
- * Type: Semester Thesis (1 or 2 students) [[File:FPU_with_DivSqrt.png|thumb|300px|CVFPU block diagram [1]. CVFPU is a modular floating-point unit (FPU) in which each operation grou2 KB (307 words) - 15:40, 15 February 2024
- : Looking for 1-2 Semester/Bachelor/Master students : VLSI 15 KB (578 words) - 12:39, 14 June 2023
- <!-- FPGA mapping of RPC DRAM (1-2S/B) --> ...and low pin-count FPGAs and ASICs. These reduced pin count DDR (RPC DDR) [1] memories only require a simple on-chip PHY and can operate with regular di3 KB (484 words) - 20:29, 21 February 2024
- : Looking for 1 Semester/master student : Familiarity with FPGA programming (VLSI 1 or similar)6 KB (720 words) - 16:27, 27 September 2023