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Showing below up to 145 results in range #751 to #895.
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- Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
- Signal to Noise Ratio Estimation for 3G standards
- Simulation of 2D artificial cilia metasurface in COMSOL
- Simulation of Li-ion batteries and comparison with experimental data
- Simulation of Negative Capacitance Ferroelectric Transistor
- Simultaneous Sensing and Communication
- Single-Bit-Synapse Spiking Neural System-on-Chip
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Skin coupling media characterization for fitnesstracker applications (1 B/S)
- SmartRing
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S)
- Smart Meters
- Smart Patch For Heath Care And Rehabilitation
- Smart Virtual Memory Sharing
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Smart e-glasses for concealed recording of EEG signals
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- Softmax for Transformers (M/1-2S)
- Software
- Software-Defined Paging in the Snitch Cluster (2-3S)
- Spatio-Temporal Video Filtering
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Spiking Neural Network for Autonomous Navigation
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Stand-Alone Edge Computing with GAP8
- Standard Cell Compatible Memory Array Design
- State-Saving @ NXP
- Stefan Lippuner
- Stefan Mach
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Streaming Integer Extensions for Snitch (M/1-2S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets
- Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub-Noise Floor Channel Tracking
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Subject specific embeddings for transfer learning in brain-computer interfaces
- Successive Approximation Register (SAR) ADC
- Successive Interference Cancellation for 3G Downlink
- Super Resolution Radar/Imaging at mm-Wave frequencies
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Switched Capacitor Based Bandgap-Reference
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- System Emulation for AR and VR devices
- TCNs vs. LSTMs for Embedded Platforms
- Taimir Aguacil
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- Tbenz
- Telecommunications
- Template
- Ternary Neural Networks for Face Recognition
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Test page
- Test project
- Testbed Design for Self-sustainable IoT Sensors
- Theory, Algorithms, and Hardware for Beyond 5G
- Thermal Control of Mobile Devices
- Through Wall Radar Imaging using Machine Learning
- Time Gain Compensation for Ultrasound Imaging
- Time Synchronization for 3G Mobile Communications
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Timing Channel Mitigations for RISC-V Cores
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Toward Superposition of Brain-Computer Interface Models
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Towards Autonomous Navigation for Nano-Blimps
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards Online Training of CNNs: Hebbian-Based Deep Learning
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards Self Sustainable UAVs
- Towards The Integration of E-skin into Prosthetic Devices
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards global Brain-Computer Interfaces
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Trace Debugger for custom RISC-V Core
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Decoder Design for High Code Rates
- Turbo Equalization for Cellular IoT
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Ultra-low power processor design
- Ultra-low power sampling front-end for acquisition of physiological signals
- Ultra-low power transceiver for implantable devices
- Ultra-wideband Concurrent Ranging
- Ultra Low-Power Oscillator
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Ultra low power wearable ultrasound probe
- Ultrafast Medical Ultrasound imaging on a GPU
- Ultrasound
- Ultrasound-EMG combined hand gesture recognition
- Ultrasound Doppler system development
- Ultrasound High Speed Microbubble Tracking
- Ultrasound Low power WiFi with IMX7
- Ultrasound based hand gesture recognition
- Ultrasound image data recycler
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- Ultrasound signal processing acceleration with CUDA
- Unconventional phase change memory device concepts for in-memory and neuromorphic computin
- Using Motion Sensors to Support Indoor Localization
- VLSI Design of an Asynchronous LDPC Decoder
- VLSI Implementation Polar Decoder using High Level Synthesis
- VLSI Implementation of a 5G Ciphering Accelerator
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM
- Variability Tolerant Ultra Low Power Cluster
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- Vector Processor for In-Memory Computing
- Versatile HW SW Digital PHY for inter chip communication
- Virtual Memory Ara
- Visualization of Neural Architecture Search Spaces
- Visualizing Functional Microbubbles using Ultrasound Imaging
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- Wake Up Radio For Energy Efficient Communication System and IC Design
- Watchdog Timer for PULP
- Weak-strong massive MIMO communication with low-resolution ADCs
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Wearable Ultrasound for Artery monitoring
- Wearables for Sports and Fitness Tracking
- Wearables for Sports and Life Enhancement
- Wearables in Fashion
- Weekly Reports
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
- Wireless Biomedical Signal Acquisition Device
- Wireless Communication Systems for the IoT
- Wireless EEG Acquisition and Processing
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- Wireless Sensing With Long Range Comminication (LoRa)
- Writing a Hero runtime for EPAC (1-3S/B)
- XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
- Zephyr RTOS on PULP
- Zero Power Touch Sensor and Reciever For Body Communication
