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Showing below up to 500 results in range #251 to #750.

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  1. VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM‏‎ (4 revisions)
  2. Near-Memory Training of Neural Networks‏‎ (4 revisions)
  3. Intelligent Power Management Unit (iPMU)‏‎ (4 revisions)
  4. Positioning for the cellular Internet of Things‏‎ (4 revisions)
  5. Improving our Smart Camera System‏‎ (4 revisions)
  6. Ibex: Bit-Manipulation Extension‏‎ (4 revisions)
  7. Variability Tolerant Ultra Low Power Cluster‏‎ (4 revisions)
  8. An FPGA-Based Testbed for 3G Mobile Communications Receivers‏‎ (4 revisions)
  9. Enhancing our DMA Engine with Fault Tolerance‏‎ (4 revisions)
  10. Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning‏‎ (4 revisions)
  11. Super Resolution Radar/Imaging at mm-Wave frequencies‏‎ (4 revisions)
  12. Wireless Biomedical Signal Acquisition Device‏‎ (4 revisions)
  13. FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications‏‎ (4 revisions)
  14. Spiking Neural Network for Motor Function Decoding Based on Neural Dust‏‎ (4 revisions)
  15. Hardware Exploration of Shared-Exponent MiniFloats (M)‏‎ (4 revisions)
  16. In-ear EEG signal acquisition‏‎ (4 revisions)
  17. CPS Software-Configurable State-Machine‏‎ (4 revisions)
  18. Theory, Algorithms, and Hardware for Beyond 5G‏‎ (4 revisions)
  19. ASIC Design of a Sigma Point Processor‏‎ (4 revisions)
  20. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications‏‎ (4 revisions)
  21. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)‏‎ (4 revisions)
  22. Smart e-glasses for concealed recording of EEG signals‏‎ (4 revisions)
  23. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations‏‎ (4 revisions)
  24. Power Optimization in Multipliers‏‎ (4 revisions)
  25. Low-power chip-to-chip communication network‏‎ (4 revisions)
  26. Final Report‏‎ (4 revisions)
  27. High performance continous-time Delta-Sigma ADC for biomedical applications‏‎ (4 revisions)
  28. Coherence-Capable Write-Back L1 Data Cache for Ariane‏‎ (4 revisions - redirect page)
  29. Forward error-correction ASIC using GRAND‏‎ (4 revisions)
  30. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)‏‎ (4 revisions)
  31. Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets‏‎ (4 revisions)
  32. Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)‏‎ (4 revisions)
  33. Adding Linux Support to our DMA engine (1-2S/B)‏‎ (4 revisions - redirect page)
  34. SHAre - An application Specific Instruction Set Processor for SHA-2/3‏‎ (4 revisions)
  35. Eye movements‏‎ (4 revisions)
  36. Palm size chip NMR‏‎ (4 revisions)
  37. Implementation of an AES Hardware Processing Engine (B/S)‏‎ (4 revisions)
  38. Telecommunications‏‎ (4 revisions)
  39. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM‏‎ (4 revisions)
  40. Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S)‏‎ (4 revisions)
  41. NAND Flash Open Research Platform‏‎ (4 revisions)
  42. Ultra-low power sampling front-end for acquisition of physiological signals‏‎ (4 revisions)
  43. Finite element modeling of electrochemical random access memory‏‎ (4 revisions)
  44. Ultrasound High Speed Microbubble Tracking‏‎ (4 revisions)
  45. EEG artifact detection with machine learning‏‎ (4 revisions)
  46. Stefan Lippuner‏‎ (4 revisions)
  47. Advanced Data Movers for Modern Neural Networks‏‎ (4 revisions)
  48. Virtual Memory Ara‏‎ (4 revisions)
  49. Efficient TNN compression‏‎ (4 revisions)
  50. Jammer-Resilient Synchronization for Wireless Communications‏‎ (4 revisions)
  51. SSR combined with FREP in LLVM/Clang (M/1-3S)‏‎ (4 revisions - redirect page)
  52. Sub-Noise Floor Channel Tracking‏‎ (4 revisions)
  53. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core‏‎ (4 revisions)
  54. Pascal Hager‏‎ (4 revisions)
  55. RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB‏‎ (5 revisions)
  56. Internet of Things SoC Characterization‏‎ (5 revisions)
  57. Ternary Neural Networks for Face Recognition‏‎ (5 revisions)
  58. A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography‏‎ (5 revisions)
  59. Precise Ultra-low-power Timer‏‎ (5 revisions)
  60. Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S)‏‎ (5 revisions)
  61. Embedded Systems and autonomous UAVs‏‎ (5 revisions)
  62. LightProbe - Thermal-Power aware on-head Beamforming‏‎ (5 revisions)
  63. Data Augmentation Techniques in Biosignal Classification‏‎ (5 revisions)
  64. IP-Based SoC Generation and Configuration (1-3S/B)‏‎ (5 revisions)
  65. Predict eye movement through brain activity‏‎ (5 revisions)
  66. Subject specific embeddings for transfer learning in brain-computer interfaces‏‎ (5 revisions)
  67. Design of a Prototype Chip with Interleaved Memory and Network-on-Chip‏‎ (5 revisions)
  68. Hardware Accelerator for Model Predictive Controller‏‎ (5 revisions)
  69. Noise Figure Measurement for Cryogenic System‏‎ (5 revisions)
  70. An Energy Efficient Brain-Computer Interface using Mr.Wolf‏‎ (5 revisions)
  71. Engineering For Kids‏‎ (5 revisions)
  72. Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device‏‎ (5 revisions)
  73. Toward Superposition of Brain-Computer Interface Models‏‎ (5 revisions)
  74. Ultra Low Power Conversion Circuit For Batteryless Applications‏‎ (5 revisions)
  75. Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor‏‎ (5 revisions)
  76. ASIC Design Projects‏‎ (5 revisions)
  77. A Wearable System To Control Phone And Electronic Device Without Hands‏‎ (5 revisions)
  78. Predictable Execution on GPU Caches‏‎ (5 revisions)
  79. Federico Villani‏‎ (5 revisions)
  80. Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration‏‎ (5 revisions)
  81. Ultra Low Power Wake Up Radio for Wireless Sensor Network‏‎ (5 revisions)
  82. Design and Implementation of ultra low power vision system‏‎ (5 revisions)
  83. Ultrasound signal processing acceleration with CUDA‏‎ (5 revisions)
  84. Fast Simulation of Manycore Systems (1S)‏‎ (5 revisions)
  85. WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing‏‎ (5 revisions)
  86. Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring‏‎ (5 revisions)
  87. Low-power Clock Generation Solutions for 65nm Technology‏‎ (5 revisions)
  88. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)‏‎ (5 revisions)
  89. Towards Autonomous Navigation for Nano-Blimps‏‎ (5 revisions)
  90. On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)‏‎ (5 revisions)
  91. Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea‏‎ (5 revisions)
  92. TCNs vs. LSTMs for Embedded Platforms‏‎ (5 revisions)
  93. Compression of Ultrasound data on FPGA‏‎ (5 revisions)
  94. High-Speed SAR ADC for next generation wireless communication in 12nm FinFET‏‎ (5 revisions)
  95. Electrothermal characterization of van der Waals Heterostructures with a partial overlap‏‎ (5 revisions)
  96. Final Presentation‏‎ (5 revisions)
  97. Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path‏‎ (5 revisions)
  98. Ultrafast Medical Ultrasound imaging on a GPU‏‎ (5 revisions)
  99. Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)‏‎ (5 revisions)
  100. Universal Stream Semantic Registers for Snitch (1S)‏‎ (5 revisions - redirect page)
  101. Phase-change memory devices for emerging computing paradigms‏‎ (5 revisions)
  102. Artificial Reverberation for Embedded Systems‏‎ (5 revisions)
  103. High-Throughput Authenticated Encryption Architectures based on Block Ciphers‏‎ (5 revisions)
  104. LLVM and DaCe for Snitch (1-2S)‏‎ (5 revisions)
  105. Channel Shortening Prefilter‏‎ (5 revisions - redirect page)
  106. Snitch meets iCE40 (1-2S/B)‏‎ (5 revisions - redirect page)
  107. Counter-based Fast Power Estimation using FPGAs (M/1-3S)‏‎ (5 revisions)
  108. Implementation of a NB-IoT Positioning System‏‎ (5 revisions)
  109. Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces‏‎ (5 revisions)
  110. Adding Linux Support to our DMA Engine (1-2S/B)‏‎ (5 revisions)
  111. Indoor Smart Tracking of Hospital instrumentation‏‎ (5 revisions)
  112. Beat DigRF‏‎ (5 revisions)
  113. A Wireless Sensor Network for a Smart Building Monitor and Control‏‎ (5 revisions)
  114. Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC‏‎ (5 revisions)
  115. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)‏‎ (5 revisions)
  116. IBM A2O Core‏‎ (5 revisions)
  117. Designing a Power Management Unit for PULP SoCs‏‎ (5 revisions)
  118. Inductive Charging Circuit for Implantable Devices‏‎ (5 revisions)
  119. Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control‏‎ (5 revisions)
  120. Image Sensor Interface and Pre-processing‏‎ (5 revisions)
  121. An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications‏‎ (5 revisions)
  122. Embedded Artificial Intelligence:Systems And Applications‏‎ (5 revisions)
  123. Low Latency Brain-Machine Interfaces‏‎ (5 revisions)
  124. Hardware/software codesign neural decoding algorithm for “neural dust”‏‎ (5 revisions)
  125. Resource Partitioning of Caches‏‎ (5 revisions)
  126. FPGA Testbed Implementation for Bluetooth Indoor Positioning‏‎ (5 revisions)
  127. State-Saving @ NXP‏‎ (5 revisions)
  128. Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)‏‎ (5 revisions)
  129. Low-Complexity MIMO Detection‏‎ (5 revisions)
  130. Design of a Fused Multiply Add Floating Point Unit‏‎ (5 revisions)
  131. Development of an efficient algorithm for quantum transport codes‏‎ (5 revisions)
  132. Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams‏‎ (5 revisions)
  133. Eye tracking‏‎ (5 revisions)
  134. Open Power-On Chip Controller Study and Integration‏‎ (5 revisions)
  135. Andreas Kurth‏‎ (5 revisions)
  136. LightProbe - Frontend Firmware and Control Side Channel‏‎ (5 revisions)
  137. Simulation of 2D artificial cilia metasurface in COMSOL‏‎ (5 revisions)
  138. Machine Learning for extracting Muscle features from Ultrasound raw data‏‎ (5 revisions)
  139. 5G Cellular RF Front-end Design in 22nm CMOS Technology‏‎ (5 revisions)
  140. Ultra-low power transceiver for implantable devices‏‎ (5 revisions)
  141. Learning Image Compression with Convolutional Networks‏‎ (5 revisions)
  142. Software-Defined Paging in the Snitch Cluster (2-3S)‏‎ (5 revisions)
  143. Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)‏‎ (5 revisions)
  144. Android Software Design‏‎ (6 revisions)
  145. FPGA mapping of RPC DRAM‏‎ (6 revisions)
  146. VLSI Implementation of a 5G Ciphering Accelerator‏‎ (6 revisions)
  147. Design of a Low Power Smart Sensing Multi-modal Vision Platform‏‎ (6 revisions)
  148. Learning Image Decompression with Convolutional Networks‏‎ (6 revisions)
  149. Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)‏‎ (6 revisions)
  150. Moritz Schneider‏‎ (6 revisions)
  151. Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)‏‎ (6 revisions)
  152. Graph neural networks for epileptic seizure detection‏‎ (6 revisions)
  153. Enabling Efficient Systolic Execution on MemPool (M)‏‎ (6 revisions)
  154. Ultrasound image data recycler‏‎ (6 revisions)
  155. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)‏‎ (6 revisions)
  156. LightProbe - Ultracompact Power Supply PCB‏‎ (6 revisions)
  157. Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening‏‎ (6 revisions)
  158. Channel Estimation for 3GPP TD-SCDMA‏‎ (6 revisions)
  159. Implementing Configurable Dual-Core Redundancy‏‎ (6 revisions)
  160. Autonomous Smart Watches: Hardware and Software Desing‏‎ (6 revisions)
  161. Creating a HDMI Video Interface for PULP‏‎ (6 revisions)
  162. System Emulation for AR and VR devices‏‎ (6 revisions)
  163. Implementation of a Heterogeneous System for Image Processing on an FPGA‏‎ (6 revisions)
  164. Implementing DSP Instructions in Banshee (1S)‏‎ (6 revisions)
  165. CMOS power amplifier for field measurements in MRI systems‏‎ (6 revisions)
  166. Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)‏‎ (6 revisions)
  167. MemPool on HERO (1S)‏‎ (6 revisions)
  168. Bluetooth Low Energy receiver in 65nm CMOS‏‎ (6 revisions)
  169. Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing‏‎ (6 revisions)
  170. New RVV 1.0 Vector Instructions for Ara‏‎ (6 revisions)
  171. Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets‏‎ (6 revisions)
  172. Low-power Temperature-insensitive Timer‏‎ (6 revisions)
  173. PULPonFPGA: Lightweight Virtual Memory Support - Software Cache‏‎ (6 revisions)
  174. Improved Collision Avoidance for Nano-drones‏‎ (6 revisions)
  175. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things‏‎ (6 revisions)
  176. Floating-Point Divide & Square Root Unit for Transprecision‏‎ (6 revisions)
  177. A Recurrent Neural Network Speech Recognition Chip‏‎ (6 revisions)
  178. Beat Cadence‏‎ (6 revisions)
  179. Exploring Algorithms for Early Seizure Detection‏‎ (6 revisions)
  180. Compression of iEEG Data‏‎ (6 revisions)
  181. Ultra-Efficient Visual Classification on Movidius Myriad2‏‎ (6 revisions)
  182. Switched Capacitor Based Bandgap-Reference‏‎ (6 revisions)
  183. Resilient Brain-Inspired Hyperdimensional Computing Architectures‏‎ (6 revisions)
  184. FPGA Optimizations of Dense Binary Hyperdimensional Computing‏‎ (6 revisions)
  185. Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)‏‎ (6 revisions)
  186. Exploring NAS spaces with C-BRED‏‎ (6 revisions)
  187. Multiuser Equalization and Detection for 3GPP TD-SCDMA‏‎ (6 revisions)
  188. Novel Metastability Mitigation Technique‏‎ (6 revisions)
  189. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms‏‎ (6 revisions)
  190. Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)‏‎ (6 revisions)
  191. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)‏‎ (6 revisions)
  192. Efficient Synchronization of Manycore Systems (M/1S)‏‎ (6 revisions)
  193. Novel Methods for Jammer Mitigation‏‎ (6 revisions)
  194. Synchronization and Power Control Concepts for 3GPP TD-SCDMA‏‎ (6 revisions)
  195. Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors‏‎ (6 revisions)
  196. VLSI Design of an Asynchronous LDPC Decoder‏‎ (6 revisions)
  197. Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)‏‎ (6 revisions)
  198. Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)‏‎ (6 revisions)
  199. Writing a Hero runtime for EPAC (1-3S/B)‏‎ (6 revisions)
  200. Next Generation Channel Decoder‏‎ (6 revisions)
  201. IBM Research–Zurich‏‎ (6 revisions)
  202. Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)‏‎ (6 revisions)
  203. Change-based Evaluation of Convolutional Neural Networks‏‎ (6 revisions)
  204. Self Aware Epilepsy Monitoring‏‎ (6 revisions)
  205. Towards Self Sustainable UAVs‏‎ (6 revisions)
  206. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs‏‎ (6 revisions)
  207. EEG earbud‏‎ (7 revisions)
  208. Development of statistics and contention monitoring unit for PULP‏‎ (7 revisions)
  209. SW/HW Predictability and Security‏‎ (7 revisions)
  210. Feature Extraction and Architecture Clustering for Keyword Spotting (1S)‏‎ (7 revisions)
  211. Sub Noise Floor Channel Estimation for the Cellular Internet of Things‏‎ (7 revisions)
  212. Gomeza old project5‏‎ (7 revisions)
  213. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core‏‎ (7 revisions)
  214. Charging System for Implantable Electronics‏‎ (7 revisions)
  215. Physical Layer Implementation of HSPA+ 4G Mobile Transceiver‏‎ (7 revisions)
  216. Zephyr RTOS on PULP‏‎ (7 revisions)
  217. RVfplib‏‎ (7 revisions)
  218. Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)‏‎ (7 revisions)
  219. Transforming MemPool into a CGRA (M)‏‎ (7 revisions)
  220. Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients‏‎ (7 revisions)
  221. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT‏‎ (7 revisions)
  222. Putting Together What Fits Together - GrÆStl‏‎ (7 revisions)
  223. FFT HDL Code Generator for Multi-Antenna mmWave Communication‏‎ (7 revisions)
  224. Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)‏‎ (7 revisions)
  225. System Analysis and VLSI Design of NB-IoT Baseband Processing‏‎ (7 revisions)
  226. Bateryless Heart Rate Monitoring‏‎ (7 revisions)
  227. ISA extensions in the Snitch Processor for Signal Processing (1M)‏‎ (7 revisions)
  228. Predictable Execution‏‎ (7 revisions)
  229. Satellite Internet of Things‏‎ (7 revisions)
  230. Mauro Salomon‏‎ (7 revisions)
  231. A RISC-V ISA Extension for Scalar Chaining in Snitch (M)‏‎ (7 revisions)
  232. Compressed Sensing for Wireless Biosignal Monitoring‏‎ (7 revisions)
  233. Outdoor Precision Object Tracking for Rockfall Experiments‏‎ (7 revisions)
  234. Spiking Neural Network for Autonomous Navigation‏‎ (7 revisions)
  235. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations‏‎ (7 revisions)
  236. Battery indifferent wearable Ultrasound‏‎ (7 revisions)
  237. Make Cellular Internet of Things Receivers Smart‏‎ (7 revisions)
  238. High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS‏‎ (7 revisions)
  239. A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities‏‎ (7 revisions)
  240. Streaming Integer Extensions for Snitch (M/1-2S)‏‎ (7 revisions)
  241. Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea‏‎ (7 revisions)
  242. Ibex: FPGA Optimizations‏‎ (7 revisions)
  243. Variable Bit Precision Logic for Deep Learning and Artificial Intelligence‏‎ (7 revisions)
  244. Digital Audio Interface for Smart Intensive Computing Triggering‏‎ (7 revisions)
  245. Memory Augmented Neural Networks in Brain-Computer Interfaces‏‎ (7 revisions)
  246. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)‏‎ (7 revisions)
  247. Indoor Positioning with Bluetooth‏‎ (7 revisions)
  248. Efficient NB-IoT Uplink Design‏‎ (7 revisions)
  249. RazorEDGE: An Evolved EDGE DBB ASIC‏‎ (7 revisions)
  250. Development of a Rockfall Sensor Node‏‎ (7 revisions)
  251. Digital Audio Processor for Cellular Applications‏‎ (7 revisions)
  252. Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications‏‎ (7 revisions)
  253. LightProbe - 200G Remote DMA for GPU FPGA Data Transfers‏‎ (7 revisions)
  254. Efficient Search Design for Hyperdimensional Computing‏‎ (7 revisions)
  255. Synchronisation and Cyclic Prefix Handling For LTE Testbed‏‎ (7 revisions)
  256. Ultra-low power processor design‏‎ (7 revisions)
  257. LTE IoT Network Synchronization‏‎ (7 revisions)
  258. EEG artifact detection for epilepsy monitoring‏‎ (7 revisions)
  259. Optimizing the Pipeline in our Floating Point Architectures (1S)‏‎ (7 revisions)
  260. IoT Turbo Decoder‏‎ (7 revisions)
  261. Fault Tolerance‏‎ (7 revisions)
  262. Characterization techniques for silicon photonics-Lumiphase‏‎ (7 revisions)
  263. Internet of Things Network Synchronizer‏‎ (7 revisions)
  264. Development of an implantable Force sensor for orthopedic applications‏‎ (7 revisions)
  265. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications‏‎ (7 revisions)
  266. Autonomous Sensing For Trains In The IoT Era‏‎ (7 revisions)
  267. Ultrasound Low power WiFi with IMX7‏‎ (7 revisions)
  268. Extend the RI5CY core with priviledge extensions‏‎ (8 revisions)
  269. NVDLA meets PULP‏‎ (8 revisions)
  270. Hardware Accelerator Integration into Embedded Linux‏‎ (8 revisions)
  271. Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications‏‎ (8 revisions)
  272. A Unified Compute Kernel Library for Snitch (1-2S)‏‎ (8 revisions)
  273. Audio Video Preprocessing In Parallel Ultra Low Power Platform‏‎ (8 revisions)
  274. Sandro Belfanti‏‎ (8 revisions)
  275. Low-Power Environmental Sensing‏‎ (8 revisions)
  276. Ultra Low-Power Oscillator‏‎ (8 revisions)
  277. Implementation of a Cache Reliability Mechanism (1S/M)‏‎ (8 revisions)
  278. Learning at the Edge with Hardware-Aware Algorithms‏‎ (8 revisions)
  279. Evaluating SoA Post-Training Quantization Algorithms‏‎ (8 revisions)
  280. Semi-Custom Digital VLSI for Processing-in-Memory‏‎ (8 revisions)
  281. Investigation of Metal Diffusion in Oxides for CBRAM Applications‏‎ (8 revisions)
  282. Machine Learning on Ultrasound Images‏‎ (8 revisions)
  283. Weekly Reports‏‎ (8 revisions)
  284. Analog Compute-in-Memory Accelerator Interface and Integration‏‎ (8 revisions)
  285. (M/1-2S): A Snitch-based Compute Accelerator for HERO‏‎ (8 revisions - redirect page)
  286. Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)‏‎ (8 revisions)
  287. Pirmin Vogel‏‎ (8 revisions)
  288. ISA extensions in the Snitch Processor for Signal Processing (M)‏‎ (8 revisions)
  289. An FPGA-Based Evaluation Platform for Mobile Communications‏‎ (8 revisions)
  290. PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker‏‎ (8 revisions)
  291. Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification‏‎ (8 revisions)
  292. Flexible Electronic Systems and Epidermal Devices‏‎ (8 revisions - redirect page)
  293. Implementing Hibernation on the ARM Cortex M0‏‎ (8 revisions)
  294. Evaluating the RiscV Architecture‏‎ (8 revisions)
  295. A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)‏‎ (8 revisions)
  296. Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs‏‎ (8 revisions)
  297. Manycore System on FPGA (M/S/G)‏‎ (8 revisions)
  298. Multi issue OoO Ariane Backend (M)‏‎ (8 revisions)
  299. PREM Runtime Scheduling Policies‏‎ (8 revisions)
  300. Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC‏‎ (8 revisions)
  301. BCI-controlled Drone‏‎ (8 revisions)
  302. Fast Wakeup From Deep Sleep State‏‎ (8 revisions)
  303. Streaming Layer Normalization in ITA (M/1-2S)‏‎ (8 revisions)
  304. Wireless EEG Acquisition and Processing‏‎ (8 revisions)
  305. Modular Distributed Data Collection Platform‏‎ (8 revisions)
  306. Hypervisor Extension for Ariane (M)‏‎ (8 revisions)
  307. Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)‏‎ (8 revisions)
  308. SCMI Support for Power Controller Subsystem‏‎ (8 revisions)
  309. Linux Driver for fine-grain and low overhead access to on-chip performance counters‏‎ (8 revisions)
  310. Deep Convolutional Autoencoder for iEEG Signals‏‎ (8 revisions)
  311. Development of a fingertip blood pressure sensor‏‎ (8 revisions)
  312. Hardware/software co-programming on the Parallella platform‏‎ (8 revisions)
  313. Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)‏‎ (8 revisions)
  314. Fault-Tolerant Floating-Point Units (M)‏‎ (8 revisions)
  315. ASIC Implementation of Jammer Mitigation‏‎ (8 revisions)
  316. Physical Implementation of ITA (2S)‏‎ (8 revisions)
  317. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format‏‎ (8 revisions)
  318. OTDOA Positioning for LTE Cat-M‏‎ (8 revisions)
  319. Resource Partitioning of RPC DRAM‏‎ (8 revisions)
  320. A Trustworthy Three-Factor Authentication System‏‎ (8 revisions)
  321. Object Detection and Tracking on the Edge‏‎ (8 revisions)
  322. A computational memory unit using phase-change memory devices‏‎ (8 revisions)
  323. Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)‏‎ (8 revisions)
  324. EvalEDGE: A 2G Cellular Transceiver FMC‏‎ (8 revisions)
  325. Next Generation Synchronization Signals‏‎ (9 revisions)
  326. Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration‏‎ (9 revisions)
  327. Machine Learning for extracting Muscle features using Ultrasound 2‏‎ (9 revisions)
  328. Karim Badawi‏‎ (9 revisions)
  329. Feature Extraction for Speech Recognition (1S)‏‎ (9 revisions)
  330. Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces‏‎ (9 revisions)
  331. Design and Implementation of an Approximate Floating Point Unit‏‎ (9 revisions)
  332. Knowledge Distillation for Embedded Machine Learning‏‎ (9 revisions)
  333. Hyper-Dimensional Computing Based Predictive Maintenance‏‎ (9 revisions)
  334. Efficient Implementation of an Active-Set QP Solver for FPGAs‏‎ (9 revisions)
  335. Deconvolution Accelerator for On-Chip Semi-Supervised Learning‏‎ (9 revisions)
  336. HERO: TLB Invalidation‏‎ (9 revisions)
  337. PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory‏‎ (9 revisions)
  338. Hyper Meccano: Acceleration of Hyperdimensional Computing‏‎ (9 revisions)
  339. Design of a 25 Gbps SerDes for optical chip-to-chip communication‏‎ (9 revisions)
  340. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)‏‎ (9 revisions)
  341. Real-Time Pedestrian Detection For Privacy Enhancement‏‎ (9 revisions)
  342. Runtime partitioning of L1 memory in Mempool (M)‏‎ (9 revisions)
  343. Integrating Hardware Accelerators into Snitch‏‎ (9 revisions)
  344. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)‏‎ (9 revisions)
  345. Harald Kröll‏‎ (9 revisions)
  346. Improved Reacquisition for the 5G Cellular IoT‏‎ (9 revisions)
  347. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)‏‎ (9 revisions)
  348. Automatic unplugging detection for Ultrasound probes‏‎ (9 revisions)
  349. LTE-Advanced RF Front-end Design in 28nm CMOS Technology‏‎ (9 revisions)
  350. Ultrasound-EMG combined hand gesture recognition‏‎ (9 revisions)
  351. DC-DC Buck converter in 65nm CMOS‏‎ (9 revisions)
  352. Practical Reconfigurable Intelligent Surfaces (RIS)‏‎ (9 revisions)
  353. Energy Efficient SoCs‏‎ (9 revisions)
  354. Configurable Ultra Low Power LDO‏‎ (9 revisions)
  355. Gomeza old project2‏‎ (9 revisions)
  356. Real-time View Synthesis using Image Domain Warping‏‎ (9 revisions)
  357. Michael Rogenmoser‏‎ (9 revisions)
  358. A Multiview Synthesis Core in 65 nm CMOS‏‎ (9 revisions)
  359. OpenRISC SoC for Sensor Applications‏‎ (9 revisions)
  360. Improved State Estimation on PULP-based Nano-UAVs‏‎ (9 revisions)
  361. Freedom from Interference in Heterogeneous COTS SoCs‏‎ (9 revisions)
  362. Real-time eye movement analysis on a tablet computer‏‎ (9 revisions)
  363. Minimal Cost RISC-V core‏‎ (9 revisions)
  364. Hardware Accelerated Derivative Pricing‏‎ (9 revisions)
  365. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging‏‎ (9 revisions)
  366. Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication‏‎ (9 revisions)
  367. Gomeza old project4‏‎ (9 revisions)
  368. Time and Frequency Synchronization in LTE Cat-0 Devices‏‎ (9 revisions)
  369. LightProbe - Implementation of compressed-sensing algorithms‏‎ (10 revisions)
  370. Machine Learning for extracting Muscle features using Ultrasound‏‎ (10 revisions)
  371. Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools‏‎ (10 revisions)
  372. Open Source Basestation for Evolved EDGE‏‎ (10 revisions - redirect page)
  373. Ultrasound based hand gesture recognition‏‎ (10 revisions)
  374. Robert Balas‏‎ (10 revisions)
  375. Visualizing Functional Microbubbles using Ultrasound Imaging‏‎ (10 revisions)
  376. Wearables in Fashion‏‎ (10 revisions)
  377. PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB‏‎ (10 revisions)
  378. Enabling Standalone Operation‏‎ (10 revisions)
  379. Radiation Testing of a PULP ASIC‏‎ (10 revisions)
  380. GSM Voice Capacity Evolution - VAMOS‏‎ (10 revisions)
  381. Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)‏‎ (10 revisions)
  382. Quest for the smallest Turing-complete core (2-3G)‏‎ (10 revisions - redirect page)
  383. Cell-Free mmWave Massive MIMO Communication‏‎ (10 revisions)
  384. A Wireless Sensor Network for HPC monitoring‏‎ (10 revisions)
  385. BigPULP: Shared Virtual Memory Multicluster Extensions‏‎ (10 revisions)
  386. Design of a VLIW processor architecture based on RISC-V‏‎ (10 revisions)
  387. MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.‏‎ (10 revisions)
  388. Cell Measurements for the 5G Internet of Things‏‎ (10 revisions)
  389. Fast and Accurate Multiclass Inference for Brain–Computer Interfaces‏‎ (10 revisions)
  390. Event-Driven Vision on an embedded platform‏‎ (10 revisions)
  391. ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)‏‎ (10 revisions)
  392. Design of Charge-Pump PLL in 22nm for 5G communication applications‏‎ (10 revisions)
  393. Time Gain Compensation for Ultrasound Imaging‏‎ (10 revisions)
  394. Gomeza old project3‏‎ (10 revisions)
  395. Wearable Ultrasound for Artery monitoring‏‎ (10 revisions)
  396. Self-Supervised User Positioning in Cell-Free Massive MIMO Systems‏‎ (10 revisions)
  397. SystemVerilog formatter for our LowRISC-based guidelines (2-3G)‏‎ (10 revisions)
  398. Implementation of an Accelerator for Retentive Networks (1-2S)‏‎ (10 revisions)
  399. All the flavours of FFT on MemPool (1-2S/B)‏‎ (10 revisions)
  400. Matteo Perotti‏‎ (10 revisions)
  401. Advanced EEG glasses‏‎ (11 revisions)
  402. Monocular Vision-based Object Following on Nano-size Robotic Blimp‏‎ (11 revisions)
  403. Timing Channel Mitigations for RISC-V Cores‏‎ (11 revisions)
  404. Pulse Oximetry Fachpraktikum‏‎ (11 revisions)
  405. Design of combined Ultrasound and Electromyography systems‏‎ (11 revisions)
  406. Baseband Processor Development for 4G IoT‏‎ (11 revisions)
  407. Evolved EDGE Physical Layer Incremental Redundancy Architecture‏‎ (11 revisions)
  408. Channel Estimation and Equalization for LTE Advanced‏‎ (11 revisions)
  409. PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions‏‎ (11 revisions)
  410. Design and Implementation of a multi-mode multi-master I2C peripheral‏‎ (11 revisions)
  411. Design of combined Ultrasound and PPG systems‏‎ (11 revisions)
  412. Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment‏‎ (11 revisions)
  413. FPGA-Based Digital Frontend for 3G Receivers‏‎ (11 revisions)
  414. Hardware Constrained Neural Architechture Search‏‎ (11 revisions)
  415. LightProbe - WIFI extension (PCB)‏‎ (11 revisions)
  416. Non-blocking Algorithms in Real-Time Operating Systems‏‎ (11 revisions)
  417. Audio Visual Speech Separation and Recognition (1S/1M)‏‎ (11 revisions)
  418. Energy-Efficient Brain-Inspired Hyperdimensional Computing‏‎ (11 revisions)
  419. Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)‏‎ (11 revisions)
  420. Adaptively Controlled Hysteresis Curve Tracer For Polymer Ultrasonic Transducers (1 S/B)‏‎ (11 revisions - redirect page)
  421. Interference Cancellation for EC-GSM-IoT‏‎ (11 revisions)
  422. Design and Evaluation of a Small Size Avalanche Beacon‏‎ (11 revisions)
  423. Real-time Linux on RISC-V‏‎ (11 revisions)
  424. Towards Online Training of CNNs: Hebbian-Based Deep Learning‏‎ (11 revisions)
  425. FPGA System Design for Computer Vision with Convolutional Neural Networks‏‎ (11 revisions)
  426. Deep Learning-based Global Local Planner for Autonomous Nano-drones‏‎ (11 revisions)
  427. Design of a Digital Audio Module for Ultra-Low Power Cellular Applications‏‎ (11 revisions)
  428. Self-Learning Drones based on Neural Networks‏‎ (11 revisions)
  429. FPGA acceleration of ultrasound computed tomography for in vivo tumor screening‏‎ (11 revisions)
  430. Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)‏‎ (11 revisions)
  431. Minimum Variance Beamforming for Wearable Ultrasound Probes‏‎ (11 revisions)
  432. Hardware Acceleration‏‎ (11 revisions)
  433. ASIC implementation of an interpolation-based wideband massive MIMO detector‏‎ (12 revisions)
  434. PULPonFPGA: Hardware L2 Cache‏‎ (12 revisions)
  435. Spatio-Temporal Video Filtering‏‎ (12 revisions)
  436. A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)‏‎ (12 revisions)
  437. Deep neural networks for seizure detection‏‎ (12 revisions)
  438. Sensor Fusion for Rockfall Sensor Node‏‎ (12 revisions)
  439. Hardware Accelerators for Lossless Quantized Deep Neural Networks‏‎ (12 revisions)
  440. Peak-to-average power Reduction‏‎ (12 revisions)
  441. Investigation of Quantization Strategies for Retentive Networks (1S)‏‎ (12 revisions)
  442. Digital Audio High Level Synthesis for FPGAs‏‎ (12 revisions - redirect page)
  443. Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)‏‎ (12 revisions)
  444. BigPULP: Multicluster Synchronization Extensions‏‎ (12 revisions)
  445. Event-Driven Computing‏‎ (12 revisions)
  446. Bridging QuantLab with LPDNN‏‎ (12 revisions)
  447. Investigation of Redox Processes in CBRAM‏‎ (12 revisions)
  448. Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device‏‎ (12 revisions)
  449. Scattering Networks for Scene Labeling‏‎ (12 revisions)
  450. Accelerating Matrix Multiplication on a 216-core MPSoC (1M)‏‎ (12 revisions)
  451. Event-Driven Convolutional Neural Network Modular Accelerator‏‎ (12 revisions)
  452. Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device‏‎ (12 revisions)
  453. Stand-Alone Edge Computing with GAP8‏‎ (12 revisions)
  454. Covariant Feature Detector on Parallel Ultra Low Power Architecture‏‎ (12 revisions)
  455. SmartRing‏‎ (12 revisions)
  456. Ultrasound Doppler system development‏‎ (12 revisions)
  457. Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control‏‎ (12 revisions)
  458. Image and Video Processing‏‎ (12 revisions)
  459. Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex‏‎ (12 revisions)
  460. Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems‏‎ (12 revisions)
  461. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials‏‎ (12 revisions)
  462. Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems‏‎ (12 revisions)
  463. Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)‏‎ (13 revisions)
  464. Efficient collective communications in FlooNoC (1M)‏‎ (13 revisions)
  465. Deep Learning for Brain-Computer Interface‏‎ (13 revisions)
  466. On-Board Software for PULP on a Satellite‏‎ (13 revisions)
  467. Neural Recording Interface and Signal Processing‏‎ (13 revisions)
  468. CLIC for the CVA6‏‎ (13 revisions)
  469. StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC‏‎ (13 revisions)
  470. Level Crossing ADC For a Many Channels Neural Recording Interface‏‎ (13 revisions)
  471. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT‏‎ (13 revisions)
  472. Towards global Brain-Computer Interfaces‏‎ (13 revisions)
  473. Integrated silicon photonic structures‏‎ (13 revisions)
  474. LAPACK/BLAS for FPGA‏‎ (13 revisions)
  475. Shared Correlation Accelerator for an RF SoC‏‎ (13 revisions)
  476. GUI-developement for an action-cam-based eye tracking device‏‎ (13 revisions)
  477. Turbo Equalization for Cellular IoT‏‎ (13 revisions)
  478. On-chip clock synthesizer design and porting‏‎ (13 revisions)
  479. Cycle-Accurate Event-Based Simulation of Snitch Core‏‎ (13 revisions)
  480. Gomeza old project1‏‎ (13 revisions)
  481. Online Learning of User Features (1S)‏‎ (13 revisions)
  482. MatPHY: An Open-Source Physical Layer Development Framework‏‎ (13 revisions)
  483. Acceleration and Transprecision‏‎ (13 revisions)
  484. A Wireless Sensor Network for a Smart LED Lighting control‏‎ (13 revisions)
  485. ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G‏‎ (13 revisions)
  486. Application Specific Frequency Synthesizers (Analog/Digital PLLs)‏‎ (14 revisions)
  487. ASIC Design of a Gaussian Message Passing Processor‏‎ (14 revisions)
  488. Ultra low power wearable ultrasound probe‏‎ (14 revisions)
  489. Beamspace processing for 5G mmWave massive MIMO on GPU‏‎ (14 revisions)
  490. HW/SW Safety and Security‏‎ (14 revisions)
  491. Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)‏‎ (14 revisions)
  492. Heroino: Design of the next CORE-V Microcontroller‏‎ (14 revisions)
  493. Physical Implementation of Ara, PULP's Vector Machine (1-2S)‏‎ (14 revisions)
  494. Finite Element Simulations of Transistors for Quantum Computing‏‎ (14 revisions)
  495. High-speed Scene Labeling on FPGA‏‎ (14 revisions)
  496. PULP in space - Fault Tolerant PULP System for Critical Space Applications‏‎ (14 revisions)
  497. Completed‏‎ (15 revisions)
  498. Active-Set QP Solver on FPGA‏‎ (15 revisions)
  499. Digital Transmitter for Mobile Communications‏‎ (15 revisions)
  500. Elliptic Curve Accelerator for zkSNARKs‏‎ (15 revisions)

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