Pages with the most categories
From iis-projects
Showing below up to 100 results in range #151 to #250.
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- ISA extensions in the Snitch Processor for Signal Processing (M) (10 categories)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (10 categories)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B) (10 categories)
- Wireless Communication Systems for the IoT (10 categories)
- PULP Freertos with LLVM (10 categories)
- Floating-Point Divide & Square Root Unit for Transprecision (10 categories)
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications (10 categories)
- Machine Learning for extracting Muscle features from Ultrasound raw data (10 categories)
- Softmax for Transformers (M/1-2S) (10 categories)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S) (9 categories)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (9 categories)
- Self Aware Epilepsy Monitoring (9 categories)
- Level Crossing ADC For a Many Channels Neural Recording Interface (9 categories)
- Probing the limits of fake-quantised neural networks (9 categories)
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) (9 categories)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S) (9 categories)
- LightProbe - WIFI extension (PCB) (9 categories)
- A Multiview Synthesis Core in 65 nm CMOS (9 categories)
- Trace Debugger for custom RISC-V Core (9 categories)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (9 categories)
- Advanced 5G Repetition Combining (9 categories)
- Improving Cold-Start in Batteryless And Energy Harvesting Systems (9 categories)
- Hardware Constrained Neural Architechture Search (9 categories)
- Machine Learning for extracting Muscle features using Ultrasound 2 (9 categories)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M) (9 categories)
- Implementation of an Accelerator for Retentive Networks (1-2S) (9 categories)
- Internet of Things Network Synchronizer (9 categories)
- On-Device Federated Continual Learning on Nano-Drone Swarms (9 categories)
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection (9 categories)
- Writing a Hero runtime for EPAC (1-3S/B) (9 categories)
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels (9 categories)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S) (9 categories)
- On-Device Learnable Embeddings for Acoustic Environments (9 categories)
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients (9 categories)
- Design and Implementation of an Approximate Floating Point Unit (9 categories)
- Knowledge Distillation for Embedded Machine Learning (9 categories)
- Outdoor Precision Object Tracking for Rockfall Experiments (9 categories)
- Cycle-Accurate Event-Based Simulation of Snitch Core (9 categories)
- Integrating Hardware Accelerators into Snitch (1S) (9 categories)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (9 categories)
- HERO: TLB Invalidation (9 categories)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (9 categories)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) (9 categories)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (9 categories)
- Ultrasound signal processing acceleration with CUDA (9 categories)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications (9 categories)
- Deep neural networks for seizure detection (9 categories)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (9 categories)
- EEG artifact detection for epilepsy monitoring (9 categories)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) (9 categories)
- On - Device Continual Learning for Seizure Detection on GAP9 (9 categories)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (9 categories)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (9 categories)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B) (9 categories)
- Investigation of Quantization Strategies for Retentive Networks (1S) (9 categories)
- EEG artifact detection with machine learning (9 categories)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S) (9 categories)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (9 categories)
- AXI-based Network on Chip (NoC) system (9 categories)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (9 categories)
- BLISS - Battery-Less Identification System for Security (9 categories)
- Hardware/software codesign neural decoding algorithm for “neural dust” (9 categories)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (9 categories)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (9 categories)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (9 categories)
- Flexfloat DL Training Framework (9 categories)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (9 categories)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (9 categories)
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B) (9 categories)
- NVDLA meets PULP (9 categories)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (9 categories)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (9 categories)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S) (9 categories)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (9 categories)
- Active-Set QP Solver on FPGA (9 categories)
- NeuroSoC RISC-V Component (M/1-2S) (9 categories)
- Physics is looking for PULP (9 categories)
- Learning Image Decompression with Convolutional Networks (9 categories)
- Exploring NAS spaces with C-BRED (9 categories)
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET (9 categories)
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B) (9 categories)
- Extreme-Edge Experience Replay for Keyword Spotting (9 categories)
- Ternary Neural Networks for Face Recognition (9 categories)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M) (9 categories)
- An Efficient Compiler Backend for Snitch (1S/B) (9 categories)
- Wireless EEG Acquisition and Processing (9 categories)
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor (9 categories)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (9 categories)
- Learning at the Edge with Hardware-Aware Algorithms (9 categories)
- ASIC Development of 5G-NR LDPC Decoder (9 categories)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications (9 categories)
- MemPool on HERO (1S) (9 categories)
- Adding Linux Support to our DMA Engine (1-2S/B) (9 categories)
- Improved State Estimation on PULP-based Nano-UAVs (9 categories)
- Monocular Vision-based Object Following on Nano-size Robotic Blimp (9 categories)
- Event-Driven Convolutional Neural Network Modular Accelerator (9 categories)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (8 categories)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (8 categories)
- Ibex: FPGA Optimizations (8 categories)
- Embedded Gesture Recognition Using Novel Mini Radar Sensors (8 categories)