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Showing below up to 100 results in range #351 to #450.

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  1. Eye movements
  2. Eye tracking
  3. Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
  4. FFT-based Convolutional Network Accelerator
  5. FFT HDL Code Generator for Multi-Antenna mmWave Communication
  6. FPGA
  7. FPGA-Based Digital Frontend for 3G Receivers
  8. FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
  9. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  10. FPGA Optimizations of Dense Binary Hyperdimensional Computing
  11. FPGA System Design for Computer Vision with Convolutional Neural Networks
  12. FPGA Testbed Implementation for Bluetooth Indoor Positioning
  13. FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  14. FPGA mapping of RPC DRAM
  15. Fabian Schuiki
  16. Fast Accelerator Context Switch for PULP
  17. Fast Simulation of Manycore Systems (1S)
  18. Fast Wakeup From Deep Sleep State
  19. Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
  20. Fault-Tolerant Floating-Point Units (M)
  21. Fault Tolerance
  22. Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
  23. Feature Extraction for Speech Recognition (1S)
  24. Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
  25. Federico Villani
  26. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
  27. Final Presentation
  28. Final Report
  29. Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
  30. Finite Element Simulations of Transistors for Quantum Computing
  31. Finite element modeling of electrochemical random access memory
  32. Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
  33. Flexfloat DL Training Framework
  34. Flexible Electronic Systems and Embedded Epidermal Devices
  35. Flexible Front-End Circuit for Biomedical Data Acquisition
  36. Floating-Point Divide & Square Root Unit for Transprecision
  37. Forward error-correction ASIC using GRAND
  38. Frank K. Gürkaynak
  39. Freedom from Interference in Heterogeneous COTS SoCs
  40. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  41. GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
  42. GPT on the edge
  43. GRAND Hardware Implementation
  44. GSM Voice Capacity Evolution - VAMOS
  45. GUI-developement for an action-cam-based eye tracking device
  46. Glitches Reduce Listening Time of Your iPod
  47. Gomeza old project1
  48. Gomeza old project2
  49. Gomeza old project3
  50. Gomeza old project4
  51. Gomeza old project5
  52. Graph neural networks for epileptic seizure detection
  53. Guillaume Mocquard
  54. HERO: TLB Invalidation
  55. HW/SW Safety and Security
  56. Harald Kröll
  57. Hardware/software co-programming on the Parallella platform
  58. Hardware/software codesign neural decoding algorithm for “neural dust”
  59. Hardware Accelerated Derivative Pricing
  60. Hardware Acceleration
  61. Hardware Accelerator Integration into Embedded Linux
  62. Hardware Accelerator for Model Predictive Controller
  63. Hardware Accelerators for Lossless Quantized Deep Neural Networks
  64. Hardware Constrained Neural Architechture Search
  65. Hardware Exploration of Shared-Exponent MiniFloats (M)
  66. Hardware Support for IDE in Multicore Environment
  67. Heroino: Design of the next CORE-V Microcontroller
  68. Herschmi
  69. Heterogeneous SoCs
  70. High-Resolution, Calibrated Folding ADCs
  71. High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
  72. High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
  73. High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
  74. High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  75. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  76. High-speed Scene Labeling on FPGA
  77. High-throughput Embedded System For Neurotechnology in collaboration with INI
  78. High Performance Cellular Receivers in Very Advanced CMOS
  79. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  80. High Performance SoCs
  81. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
  82. High Speed FPGA Trigger Logic for Particle Physics Experiments
  83. High Throughput Turbo Decoder Design
  84. High performance continous-time Delta-Sigma ADC for biomedical applications
  85. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  86. High resolution, low power Sigma Delta ADC
  87. Huawei Research
  88. Human Intranet
  89. Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  90. Hyper-Dimensional Computing Based Predictive Maintenance
  91. Hyper Meccano: Acceleration of Hyperdimensional Computing
  92. Hyperdimensional Computing
  93. Hypervisor Extension for Ariane (M)
  94. IBM A2O Core
  95. IBM Research
  96. IBM Research–Zurich
  97. IP-Based SoC Generation and Configuration (1-3S)
  98. IP-Based SoC Generation and Configuration (1-3S/B)
  99. ISA extensions in the Snitch Processor for Signal Processing (1M)
  100. ISA extensions in the Snitch Processor for Signal Processing (M)

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