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Showing below up to 100 results in range #351 to #450.

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  1. Extreme-Edge Experience Replay for Keyword Spotting
  2. Eye movements
  3. Eye tracking
  4. Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
  5. FFT-based Convolutional Network Accelerator
  6. FFT HDL Code Generator for Multi-Antenna mmWave Communication
  7. FPGA
  8. FPGA-Based Digital Frontend for 3G Receivers
  9. FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
  10. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  11. FPGA Optimizations of Dense Binary Hyperdimensional Computing
  12. FPGA System Design for Computer Vision with Convolutional Neural Networks
  13. FPGA Testbed Implementation for Bluetooth Indoor Positioning
  14. FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  15. FPGA mapping of RPC DRAM
  16. Fabian Schuiki
  17. Fast Accelerator Context Switch for PULP
  18. Fast Simulation of Manycore Systems (1S)
  19. Fast Wakeup From Deep Sleep State
  20. Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
  21. Fault-Tolerant Floating-Point Units (M)
  22. Fault Tolerance
  23. Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
  24. Feature Extraction for Speech Recognition (1S)
  25. Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
  26. Federico Villani
  27. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
  28. Final Presentation
  29. Final Report
  30. Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
  31. Finite Element Simulations of Transistors for Quantum Computing
  32. Finite element modeling of electrochemical random access memory
  33. Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
  34. Flexfloat DL Training Framework
  35. Flexible Electronic Systems and Embedded Epidermal Devices
  36. Flexible Front-End Circuit for Biomedical Data Acquisition
  37. Floating-Point Divide & Square Root Unit for Transprecision
  38. Forward error-correction ASIC using GRAND
  39. Frank K. Gürkaynak
  40. Freedom from Interference in Heterogeneous COTS SoCs
  41. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  42. GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
  43. GPT on the edge
  44. GRAND Hardware Implementation
  45. GSM Voice Capacity Evolution - VAMOS
  46. GUI-developement for an action-cam-based eye tracking device
  47. Glitches Reduce Listening Time of Your iPod
  48. Gomeza old project1
  49. Gomeza old project2
  50. Gomeza old project3
  51. Gomeza old project4
  52. Gomeza old project5
  53. Graph neural networks for epileptic seizure detection
  54. Guillaume Mocquard
  55. HERO: TLB Invalidation
  56. HW/SW Safety and Security
  57. Harald Kröll
  58. Hardware/software co-programming on the Parallella platform
  59. Hardware/software codesign neural decoding algorithm for “neural dust”
  60. Hardware Accelerated Derivative Pricing
  61. Hardware Acceleration
  62. Hardware Accelerator Integration into Embedded Linux
  63. Hardware Accelerator for Model Predictive Controller
  64. Hardware Accelerators for Lossless Quantized Deep Neural Networks
  65. Hardware Constrained Neural Architechture Search
  66. Hardware Exploration of Shared-Exponent MiniFloats (M)
  67. Hardware Support for IDE in Multicore Environment
  68. Heroino: Design of the next CORE-V Microcontroller
  69. Herschmi
  70. Heterogeneous SoCs
  71. High-Resolution, Calibrated Folding ADCs
  72. High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
  73. High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
  74. High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
  75. High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  76. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  77. High-speed Scene Labeling on FPGA
  78. High-throughput Embedded System For Neurotechnology in collaboration with INI
  79. High Performance Cellular Receivers in Very Advanced CMOS
  80. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  81. High Performance SoCs
  82. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
  83. High Speed FPGA Trigger Logic for Particle Physics Experiments
  84. High Throughput Turbo Decoder Design
  85. High performance continous-time Delta-Sigma ADC for biomedical applications
  86. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  87. High resolution, low power Sigma Delta ADC
  88. Huawei Research
  89. Human Intranet
  90. Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  91. Hyper-Dimensional Computing Based Predictive Maintenance
  92. Hyper Meccano: Acceleration of Hyperdimensional Computing
  93. Hyperdimensional Computing
  94. Hypervisor Extension for Ariane (M)
  95. IBM A2O Core
  96. IBM Research
  97. IBM Research–Zurich
  98. IP-Based SoC Generation and Configuration (1-3S)
  99. IP-Based SoC Generation and Configuration (1-3S/B)
  100. ISA extensions in the Snitch Processor for Signal Processing (1M)

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