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Showing below up to 100 results in range #401 to #500.

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  1. Gomeza old project5
  2. Graph neural networks for epileptic seizure detection
  3. Guillaume Mocquard
  4. HERO: TLB Invalidation
  5. HW/SW Safety and Security
  6. Harald Kröll
  7. Hardware/software co-programming on the Parallella platform
  8. Hardware/software codesign neural decoding algorithm for “neural dust”
  9. Hardware Accelerated Derivative Pricing
  10. Hardware Acceleration
  11. Hardware Accelerator Integration into Embedded Linux
  12. Hardware Accelerator for Model Predictive Controller
  13. Hardware Accelerators for Lossless Quantized Deep Neural Networks
  14. Hardware Constrained Neural Architechture Search
  15. Hardware Exploration of Shared-Exponent MiniFloats (M)
  16. Hardware Support for IDE in Multicore Environment
  17. Heroino: Design of the next CORE-V Microcontroller
  18. Herschmi
  19. Heterogeneous SoCs
  20. High-Resolution, Calibrated Folding ADCs
  21. High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
  22. High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
  23. High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
  24. High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  25. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  26. High-speed Scene Labeling on FPGA
  27. High-throughput Embedded System For Neurotechnology in collaboration with INI
  28. High Performance Cellular Receivers in Very Advanced CMOS
  29. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  30. High Performance SoCs
  31. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
  32. High Speed FPGA Trigger Logic for Particle Physics Experiments
  33. High Throughput Turbo Decoder Design
  34. High performance continous-time Delta-Sigma ADC for biomedical applications
  35. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  36. High resolution, low power Sigma Delta ADC
  37. Huawei Research
  38. Human Intranet
  39. Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  40. Hyper-Dimensional Computing Based Predictive Maintenance
  41. Hyper Meccano: Acceleration of Hyperdimensional Computing
  42. Hyperdimensional Computing
  43. Hypervisor Extension for Ariane (M)
  44. IBM A2O Core
  45. IBM Research
  46. IBM Research–Zurich
  47. IP-Based SoC Generation and Configuration (1-3S)
  48. IP-Based SoC Generation and Configuration (1-3S/B)
  49. ISA extensions in the Snitch Processor for Signal Processing (1M)
  50. ISA extensions in the Snitch Processor for Signal Processing (M)
  51. Ibex: Bit-Manipulation Extension
  52. Ibex: FPGA Optimizations
  53. Ibex: Tightly-Coupled Accelerators and ISA Extensions
  54. IcySoC
  55. Image Sensor Interface and Pre-processing
  56. Image and Video Processing
  57. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  58. Implementation of a 2-D model for Li-ion batteries
  59. Implementation of a Cache Reliability Mechanism (1S/M)
  60. Implementation of a Coherent Application-Class Multicore System (1-2S)
  61. Implementation of a Heterogeneous System for Image Processing on an FPGA
  62. Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  63. Implementation of a NB-IoT Positioning System
  64. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  65. Implementation of an AES Hardware Processing Engine (B/S)
  66. Implementation of an Accelerator for Retentive Networks (1-2S)
  67. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
  68. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
  69. Implementing A Low-Power Sensor Node Network
  70. Implementing Configurable Dual-Core Redundancy
  71. Implementing DSP Instructions in Banshee (1S)
  72. Implementing Hibernation on the ARM Cortex M0
  73. Improved Collision Avoidance for Nano-drones
  74. Improved Reacquisition for the 5G Cellular IoT
  75. Improved State Estimation on PULP-based Nano-UAVs
  76. Improving Cold-Start in Batteryless And Energy Harvesting Systems
  77. Improving Resiliency of Hyperdimensional Computing
  78. Improving Scene Labeling with Hyperspectral Data
  79. Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
  80. Improving datarate and efficiency of ultra low power wearable ultrasound
  81. Improving our Smart Camera System
  82. In-ear EEG signal acquisition
  83. Indoor Positioning with Bluetooth
  84. Indoor Smart Tracking of Hospital instrumentation
  85. Inductive Charging Circuit for Implantable Devices
  86. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
  87. Influence of the Initial Filament Geometry on the Forming Step in CBRAM
  88. Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
  89. Infrared Wake Up Radio
  90. Integrated Devices, Electronics, And Systems
  91. Integrated Information Processing
  92. Integrated silicon photonic structures
  93. Integrated silicon photonic structures-Lumiphase
  94. Integrating Hardware Accelerators into Snitch
  95. Integrating Hardware Accelerators into Snitch (1S)
  96. Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
  97. Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
  98. Integration Of A Smart Vision System
  99. Intelligent Power Management Unit (iPMU)
  100. Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea

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