Pages with the most categories
From iis-projects
Showing below up to 100 results in range #201 to #300.
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- Cycle-Accurate Event-Based Simulation of Snitch Core (9 categories)
- Integrating Hardware Accelerators into Snitch (1S) (9 categories)
- On-Device Learnable Embeddings for Acoustic Environments (9 categories)
- HERO: TLB Invalidation (9 categories)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (9 categories)
- Knowledge Distillation for Embedded Machine Learning (9 categories)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S) (9 categories)
- Outdoor Precision Object Tracking for Rockfall Experiments (9 categories)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (9 categories)
- Deep neural networks for seizure detection (9 categories)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S) (9 categories)
- EEG artifact detection for epilepsy monitoring (9 categories)
- Trace Debugger for custom RISC-V Core (9 categories)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (9 categories)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (9 categories)
- AXI-based Network on Chip (NoC) system (9 categories)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications (9 categories)
- EEG artifact detection with machine learning (9 categories)
- On - Device Continual Learning for Seizure Detection on GAP9 (9 categories)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S) (9 categories)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) (9 categories)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B) (9 categories)
- Writing a Hero runtime for EPAC (1-3S/B) (9 categories)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (9 categories)
- Investigation of Quantization Strategies for Retentive Networks (1S) (9 categories)
- BLISS - Battery-Less Identification System for Security (9 categories)
- Hardware/software codesign neural decoding algorithm for “neural dust” (9 categories)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (9 categories)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (9 categories)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (9 categories)
- Flexfloat DL Training Framework (9 categories)
- Active-Set QP Solver on FPGA (9 categories)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (9 categories)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (9 categories)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S) (9 categories)
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B) (9 categories)
- Ultrasound signal processing acceleration with CUDA (9 categories)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (9 categories)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (9 categories)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) (9 categories)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (9 categories)
- ASIC Development of 5G-NR LDPC Decoder (9 categories)
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B) (9 categories)
- NVDLA meets PULP (9 categories)
- Exploring NAS spaces with C-BRED (9 categories)
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET (9 categories)
- Adding Linux Support to our DMA Engine (1-2S/B) (9 categories)
- NeuroSoC RISC-V Component (M/1-2S) (9 categories)
- Extreme-Edge Experience Replay for Keyword Spotting (9 categories)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M) (9 categories)
- An Efficient Compiler Backend for Snitch (1S/B) (9 categories)
- Analog building blocks for mmWave manipulation (8 categories)
- Wearables in Fashion (8 categories)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (8 categories)
- Deep Convolutional Autoencoder for iEEG Signals (8 categories)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (8 categories)
- Digital Control of a DC/DC Buck Converter (8 categories)
- Using Motion Sensors to Support Indoor Localization (8 categories)
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX (8 categories)
- Autonomous Sensing For Trains In The IoT Era (8 categories)
- TCNs vs. LSTMs for Embedded Platforms (8 categories)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf (8 categories)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (8 categories)
- Ibex: FPGA Optimizations (8 categories)
- Standard Cell Compatible Memory Array Design (8 categories)
- Embedded Gesture Recognition Using Novel Mini Radar Sensors (8 categories)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (8 categories)
- RedCap-5G for IOT application on prototype taped-out silicon (8 categories)
- New RVV 1.0 Vector Instructions for Ara (8 categories)
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems (8 categories)
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices (8 categories)
- 3D Matrix Multiplication Unit for ITA (1S) (8 categories)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments (8 categories)
- Event-Driven Vision on an embedded platform (8 categories)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (8 categories)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (8 categories)
- Digital Transmitter for Mobile Communications (8 categories)
- Efficient NB-IoT Uplink Design (8 categories)
- A Wearable System To Control Phone And Electronic Device Without Hands (8 categories)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing (8 categories)
- Hardware Exploration of Shared-Exponent MiniFloats (M) (8 categories)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) (8 categories)
- High-throughput Embedded System For Neurotechnology in collaboration with INI (8 categories)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (8 categories)
- Deep Learning for Brain-Computer Interface (8 categories)
- SmartRing (8 categories)
- Towards global Brain-Computer Interfaces (8 categories)
- VLSI Implementation of a 5G Ciphering Accelerator (8 categories)
- RVfplib (8 categories)
- Designing a Power Management Unit for PULP SoCs (8 categories)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing (8 categories)
- Accelerator for Boosted Binary Features (8 categories)
- Extended Verification for Ara (8 categories)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M) (8 categories)
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras (8 categories)
- Radiation Testing of a PULP ASIC (8 categories)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (8 categories)
- Android reliability governor (8 categories)
- DC-DC Buck converter in 65nm CMOS (8 categories)
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) (8 categories)
