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From iis-projects
Showing below up to 100 results in range #51 to #150.
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- (hist) Project Plan [453 bytes]
- (hist) Moritz Schneider [459 bytes]
- (hist) Software [473 bytes]
- (hist) Stefan Lippuner [532 bytes]
- (hist) Benjamin Sporrer [567 bytes]
- (hist) Philipp Schönle [569 bytes]
- (hist) Design Review [577 bytes]
- (hist) Nils Wistoff [578 bytes]
- (hist) Mauro Salomon [637 bytes]
- (hist) Cryptography [645 bytes]
- (hist) Libria [646 bytes]
- (hist) Karim Badawi [653 bytes]
- (hist) Matthias Korb [698 bytes]
- (hist) Energy Efficient Circuits and IoT Systems Group [736 bytes]
- (hist) EECIS [740 bytes]
- (hist) Harald Kröll [764 bytes]
- (hist) Pascal Hager [775 bytes]
- (hist) Research [789 bytes]
- (hist) Ultrasound [797 bytes]
- (hist) Federico Villani [834 bytes]
- (hist) Coding Guidelines [841 bytes]
- (hist) Herschmi [859 bytes]
- (hist) Matheus Cavalcante [890 bytes]
- (hist) Telecommunications [892 bytes]
- (hist) Benjamin Weber [894 bytes]
- (hist) Norbert Felber [897 bytes]
- (hist) Christoph Leitner [928 bytes]
- (hist) Robert Balas [931 bytes]
- (hist) GRAND Hardware Implementation [990 bytes]
- (hist) FPGA [1,020 bytes]
- (hist) Matteo Perotti [1,028 bytes]
- (hist) Andreas Kurth [1,029 bytes]
- (hist) Fabian Schuiki [1,031 bytes]
- (hist) Stefan Mach [1,044 bytes]
- (hist) Eye tracking [1,058 bytes]
- (hist) Integrated Devices, Electronics, And Systems [1,058 bytes]
- (hist) Frank K. Gürkaynak [1,072 bytes]
- (hist) Low-Power Time Synchronization for IoT Applications [1,085 bytes]
- (hist) Physical Layer Implementation of HSPA+ 4G Mobile Transceiver [1,088 bytes]
- (hist) Guillaume Mocquard [1,117 bytes]
- (hist) Final Presentation [1,130 bytes]
- (hist) Channel Estimation for 3GPP TD-SCDMA [1,144 bytes]
- (hist) Synchronization and Power Control Concepts for 3GPP TD-SCDMA [1,145 bytes]
- (hist) Michael Muehlberghuber [1,160 bytes]
- (hist) An FPGA-Based Testbed for 3G Mobile Communications Receivers [1,168 bytes]
- (hist) FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications [1,194 bytes]
- (hist) Michael Rogenmoser [1,211 bytes]
- (hist) Interference Cancellation for EC-GSM-IoT [1,281 bytes]
- (hist) Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) [1,284 bytes]
- (hist) ASIC [1,286 bytes]
- (hist) PREM on PULP [1,304 bytes]
- (hist) Configurable Ultra Low Power LDO [1,306 bytes]
- (hist) Exploring Algorithms for Early Seizure Detection [1,329 bytes]
- (hist) SW/HW Predictability and Security [1,333 bytes]
- (hist) Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) [1,378 bytes]
- (hist) Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) [1,408 bytes]
- (hist) Design of low mismatch DAC used for VAD [1,409 bytes]
- (hist) Scan Chain Fault Injection in a PULP SoC (1S) [1,421 bytes]
- (hist) Receiver design for the DigRF 4G high speed serial link [1,431 bytes]
- (hist) Beat Cadence [1,442 bytes]
- (hist) Precise Ultra-low-power Timer [1,446 bytes]
- (hist) Digital Audio Processor for Cellular Applications [1,448 bytes]
- (hist) Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) [1,466 bytes]
- (hist) Multiuser Equalization and Detection for 3GPP TD-SCDMA [1,484 bytes]
- (hist) Creating A Boundry Scan Generator (1-3S/B/2-3G) [1,488 bytes]
- (hist) Design of a D-Band Variable Gain Amplifier for 6G Communication [1,522 bytes]
- (hist) Positioning for the cellular Internet of Things [1,525 bytes]
- (hist) ASIC Design of a Gaussian Message Passing Processor [1,526 bytes]
- (hist) Pirmin Vogel [1,528 bytes]
- (hist) Novel Metastability Mitigation Technique [1,561 bytes]
- (hist) High resolution, low power Sigma Delta ADC [1,568 bytes]
- (hist) Marco Bertuletti [1,571 bytes]
- (hist) Hardware Accelerator Integration into Embedded Linux [1,578 bytes]
- (hist) LightProbe - CNN-Based-Image-Reconstruction [1,582 bytes]
- (hist) Hardware Support for IDE in Multicore Environment [1,591 bytes]
- (hist) Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) [1,597 bytes]
- (hist) Ultrasound signal processing acceleration with CUDA [1,600 bytes]
- (hist) Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) [1,645 bytes]
- (hist) Synchronisation and Cyclic Prefix Handling For LTE Testbed [1,649 bytes]
- (hist) Audio Video Preprocessing In Parallel Ultra Low Power Platform [1,650 bytes]
- (hist) Fast Wakeup From Deep Sleep State [1,665 bytes]
- (hist) Fault Tolerance [1,665 bytes]
- (hist) EvaLTE: A 2G/3G/4G Cellular Transceiver FMC [1,679 bytes]
- (hist) Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) [1,705 bytes]
- (hist) GSM Voice Capacity Evolution - VAMOS [1,707 bytes]
- (hist) Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) [1,722 bytes]
- (hist) Design and Implementation of a multi-mode multi-master I2C peripheral [1,729 bytes]
- (hist) Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) [1,729 bytes]
- (hist) System Analysis and VLSI Design of NB-IoT Baseband Processing [1,736 bytes]
- (hist) Toward Superposition of Brain-Computer Interface Models [1,758 bytes]
- (hist) State-Saving @ NXP [1,767 bytes]
- (hist) Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) [1,776 bytes]
- (hist) Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) [1,794 bytes]
- (hist) Power Saver Mode for Cellular Internet of Things Receivers [1,795 bytes]
- (hist) Bluetooth Low Energy receiver in 65nm CMOS [1,795 bytes]
- (hist) Adding Linux Support to our DMA Engine (1-2S/B) [1,795 bytes]
- (hist) LTE-Advanced RF Front-end Design in 28nm CMOS Technology [1,811 bytes]
- (hist) 5G Cellular RF Front-end Design in 22nm CMOS Technology [1,818 bytes]
- (hist) AXI-based Network on Chip (NoC) system [1,825 bytes]
- (hist) Energy Efficient Serial Link [1,833 bytes]