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  • Main Page
    * [[Noise Figure Measurement for Cryogenic System]] * [[A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities]]
    5 KB (540 words) - 12:31, 8 May 2024
  • Ultra-low power processor design
    ...er, there is a lot of functionality which will never be used in the target system and it is therefore not necessary to maintain all this functionality. Remov ...Adding User I/O to the Processor''': If the processor is not embedded in a system, it is like a blackbox which computes something and stores the result in th
    10 KB (1,669 words) - 19:01, 30 January 2014
  • Coding Guidelines
    ...ilog code, is the '''emacs''' editor, as it has a really advanced VHDL and System Verilog mode. Because of this, you should get comfortable with the idea of
    841 bytes (137 words) - 14:42, 16 January 2014
  • Variability Tolerant Ultra Low Power Cluster
    dynamically modify the timing constrains aiming to tolerate at system level reliable computing system in nano-meter technology operating in
    3 KB (409 words) - 10:52, 27 March 2014
  • Template
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    4 KB (397 words) - 15:44, 14 February 2023
  • Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
    ...-process this data in order to compact it for the transport to the imaging system. A special challenge pose the high-speed output pin drivers. In case of int ...o reduce the incidental data rates between the sensor head and the backend system, and second, new beamforming strategies to minimize the computational burde
    4 KB (614 words) - 20:10, 17 February 2015
  • Category:UltrasoundToGo
    ...tion of this work is to provide the means for achieving a portable medical system that can provide high-quality images while being battery operated, and thus ...latform utilization and efficiency. One of the distinctive features of the system will be to support a qualified software deployment and maintenance model wh
    18 members (0 subcategories, 0 files) - 15:06, 17 January 2014
  • Multiuser Equalization and Detection for 3GPP TD-SCDMA
    TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD na
    1 KB (206 words) - 14:07, 9 February 2015
  • Channel Estimation for 3GPP TD-SCDMA
    TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD na
    1 KB (160 words) - 11:17, 23 September 2016
  • Flexible Electronic Systems and Embedded Epidermal Devices
    ...le or strechable materials to form wearable and conformable devices. These system are often composed of various flexible, bendable but also small ridgid comp
    4 KB (444 words) - 12:43, 23 July 2023
  • Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
    ...ure in such a way that later studies will allow '''ML-based control of the system'''. ...architecture is to be designed in such a way that ML-based control of the system is possible.
    6 KB (741 words) - 18:14, 21 July 2023
  • Synchronization and Power Control Concepts for 3GPP TD-SCDMA
    TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD na
    1 KB (158 words) - 11:17, 23 September 2016
  • Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
    TD-HSPA is a 3GPP standard that combines an advanced TDMA/TDD system with an adap- MLSD computation for a system with such dimensions practically impossible given the current
    5 KB (684 words) - 10:43, 6 November 2017
  • Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
    ...ject, you will assess the effect of carrier aggregation in an LTE-Advanced system. You will start by implementing a MATLAB framework to simulate the LTE-Adva
    3 KB (405 words) - 16:13, 29 December 2016
  • Digital Transmitter for Mobile Communications
    ...he chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emer ...ring the VLSI III lecture. For an implementation on an FPGA, the resulting system (combined with the existing analog transceiver) can be tested using a proto
    3 KB (382 words) - 20:00, 26 September 2017
  • User:Schaffner
    * Digital circuit and system design (FPGA/ASIC)
    922 bytes (125 words) - 12:42, 1 June 2017
  • ASIC Implementation of High-Throughput Next Generation Turbo Decoders
    Forward error correction is a crucial part in any communication system, since it enables reliable transmission over unreliable channels. In mobile
    3 KB (508 words) - 11:12, 14 April 2016
  • Category:UlpSoC
    Ultra Low Power System on a Chip (UlpSoC) is the flagship project at the IIS that aims to design e
    8 members (0 subcategories, 0 files) - 19:42, 16 January 2014
  • Low-power chip-to-chip communication network
    ...ill form the standard chip to chip communication standard for the [[PULP]] system.
    3 KB (492 words) - 12:34, 7 November 2017
  • Accelerators for object detection and tracking
    applications for this system is in real-time video applications, expecially system, improving the energy efficiency of the system. The accelerator will
    3 KB (407 words) - 10:57, 5 November 2019
  • Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
    The IIS 2G testbed has no operating system (OS) running on [4] FreeRTOS - Market leading RTOS (Real Time Operating System) for embedded systems
    3 KB (421 words) - 10:40, 6 November 2017
  • Open Source Baseband Firmware for 2G Cellular Networks
    ...tp://www.freertos.org/ FreeRTOS - Market leading RTOS (Real Time Operating System) for embedded systems with Internet of Things extensions], June 2015.
    2 KB (273 words) - 11:30, 24 February 2017
  • CPS Software-Configurable State-Machine
    ...data over a wireless link. Some of these system even include an actuation system, which reacts depending on the captured data. ...nnected and operate and act collaboratively it is called a 'cyper-physical system' (CPS).
    3 KB (418 words) - 11:24, 10 November 2017
  • Design and Implementation of an Approximate Floating Point Unit
    ...tion of the FPUs and therefore reduce the overall power consumption of the system. Sharing FPUs allows to employ several different units, which can be either ...nd is a promising approach to further improve the energy efficiency of the system. One way to approximate FP-operations is to use Newton's method to compute
    3 KB (377 words) - 10:58, 21 February 2018
  • Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
    ...egory:Qcrypt|QCRYPT]] was the development of the 100 Gbit/s link encryptor system with a variety of optical interfaces on the plain-text side and a 100 Gbit ...main focus lay on the development of a second version of the PCB for this system. The layer stackup was modified to enhance the high-frequency quality of th
    2 KB (359 words) - 20:06, 17 February 2015
  • High-Throughput Authenticated Encryption Architectures based on Block Ciphers
    ''2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)'', Santa Cruz, California, USA, 7-10 Oct 2012
    3 KB (392 words) - 12:25, 26 March 2015
  • Category:Qcrypt
    ...of quantum mechanics. However, existing systems are too slow. The new QKD system will be capable of producing keys at 1 Mbps rate, which means it will allow
    2 members (0 subcategories, 0 files) - 17:27, 28 January 2014
  • Real-time View Synthesis using Image Domain Warping
    ...erent mobile platforms, most productions are captured with one acquisition system at fixed parameters. Examples for content adaption algorithms are content-a ...ons and VLSI Implementations", ''VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, volume 418 of IFIP Advances in Information and Communicatio
    4 KB (520 words) - 16:04, 13 May 2015
  • Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
    ...IC/FPGA system which implements the first three steps of this process. Our system is able to extract SKB features from one 720p video stream in real time (30
    3 KB (487 words) - 15:57, 13 May 2015
  • Pirmin Vogel
    ...ing and embedded heterogeneous systems on a chip with a focus on operating system, driver, runtime and programming model support for efficient and transparen
    1 KB (193 words) - 15:39, 3 March 2020
  • Image Sensor Interface and Pre-processing
    ...the image is being acquired and forward this information to a larger host system for further processing. ...algorithm steps directly ion hardware and interface with the host computer system.
    3 KB (357 words) - 18:53, 6 December 2014
  • High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
    ...bits. Such data converters are intended to be embedded in a mostly digital system, and this legitimates the adoption of ultra-scaled CMOS technologies from w
    2 KB (277 words) - 17:28, 29 January 2014
  • Category:Placitus
    ...ying downscaling of CMOS technology to the nano scale device size and tera system complexity. This aggressive downscaling has allowed the number of transisto ...stem functionality into digital, analog and RF or sensor realizations on a system on chip optimally is one of the key topics that will impact the era of nano
    7 members (0 subcategories, 2 files) - 17:31, 29 January 2014
  • Category:I-IronIC
    ==Implantable/Wearable System for on-line Monitoring of Human Metabolic Conditions== ...surements, while at the same time reducing analysis time and cost. The new system will investigate many different metabolic compounds of interest in cardiova
    1 member (0 subcategories, 0 files) - 18:14, 29 January 2014
  • Wireless Biomedical Signal Acquisition Device
    Although the wireless and battery-powered nature of this system reduces the impact of mains interference, its amplitude might nonetheless b ...ed by an off-the-shelf mobile phone battery which is sufficient to run the system for several hours - the battery life-time is mainly limited by the Bluetoot
    2 KB (280 words) - 10:54, 10 March 2015
  • Benjamin Weber
    his PhD thesis entitled "An Evolved EDGE System on Chip for the Cellular
    894 bytes (115 words) - 17:17, 30 November 2021
  • Digitally-Controlled Analog Subtractive Sound Synthesis
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    5 KB (597 words) - 12:56, 4 December 2021
  • MatPHY: An Open-Source Physical Layer Development Framework
    ...upper layers of the OsmocomBB GSM protocol stack. The functionality of the system is verified with a testbed comprising a base station and a receiver board w
    3 KB (360 words) - 14:14, 27 May 2015
  • Evolved EDGE Physical Layer Incremental Redundancy Architecture
    ...ssor and the unit where RLC blocks are processed for IR is attached to the system processor. The decoding of the RLC blocks takes place on a PHY Digital Sign
    3 KB (397 words) - 14:12, 27 May 2015
  • A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
    ...ons such as those in the time-duplexing high speed packet access (TD-HSPA) system.
    2 KB (266 words) - 10:43, 9 February 2015
  • IcySoC
    ...terms of parallelism, performances and robustness. One has to revisit the system design in terms of usage of hardware accelerators, heterogeneous or homogen
    4 KB (568 words) - 12:48, 9 February 2015
  • File:Exploitation of Inherent Error Resilience of Wireless Systems.png
    ...communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect rates.
    (631 × 581 (187 KB)) - 10:33, 4 February 2014
  • Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
    ...communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect rates.]] ...Q operation that is critical for the average throughput performance of the system.
    2 KB (343 words) - 13:56, 9 February 2015
  • File:Data Mapping for Unreliable Memories.png
    ...channel with unreliable memory. Bottom: Bit-error rate performance of the system assuming convolutional coding for different data representations.
    (631 × 539 (130 KB)) - 10:39, 4 February 2014
  • Data Mapping for Unreliable Memories
    ...channel with unreliable memory. Bottom: Bit-error rate performance of the system assuming convolutional coding for different data representations.]] ...ion-specific cost functions) substantially increases the robustness of the system to unreliable memory operation, compared to the data representations most c
    3 KB (352 words) - 13:56, 9 February 2015
  • Design and Implementation of ultra low power vision system
    ...t role in this type of devices and in general in battery-operated embedded system. : Interest in Computer Architectures at system level
    2 KB (342 words) - 16:46, 11 February 2015
  • A Wireless Sensor Network for a Smart LED Lighting control
    ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors, intelligence and actuator interconnected ...e power consumption reduction, reliability, functionality and optimize the system.
    3 KB (487 words) - 12:02, 27 January 2016
  • Ultra Low Power Wake Up Radio for Wireless Sensor Network
    ...a low power radio wake up receiver can reduce the power consumption of the system while still keeping its response time low. Another role of the wake-up radi ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe
    4 KB (613 words) - 19:54, 9 February 2015
  • Infrared Wake Up Radio
    ...ices while still keeping its wake up time low. Another role of the wake-up system is that based on "intelligence" to select a specific device which has to be ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe
    3 KB (515 words) - 19:55, 9 February 2015
  • Accelerator for Boosted Binary Features
    [[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]] ...rrently used in the video analysis part of a more complex video processing system which performs [[Real-Time_Stereo_to_Multiview_Conversion|automatic multiv
    3 KB (373 words) - 11:51, 19 August 2017
  • Audio DAC Conversion Jitter Measurement System
    ...o experienced students) comprises the implementation of such a measurement system. Possible approaches include a cross-correlating spectrum analyzer or the u
    2 KB (251 words) - 20:06, 17 February 2015
  • Improving Scene Labeling with Hyperspectral Data
    ...uld be to evaluate and integrate this camera into a working scene labeling system [[http://dl.acm.org/citation.cfm?id=2744788 paper]] and would be very diver * create a system from the individual parts (build a case/box mounting the cameras, dev board
    6 KB (941 words) - 11:29, 5 February 2016
  • Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
    ...e with basic engineering tools (web search, basic usage of Linux operating system, compilers…) and of work independence
    5 KB (784 words) - 14:50, 30 November 2016
  • Android Software Design
    [[Category:Biomedical System on Chips]]
    2 KB (278 words) - 16:57, 12 July 2022
  • FPGA-Based Digital Frontend for 3G Receivers
    [[Category:System Design]]
    2 KB (348 words) - 20:01, 26 September 2017
  • ASIC
    * Designing the system architecture * Defining the circuit using hardware description languages (HDL) such as (System Verilog or VHDL) for [[:Category:Digital|digital projects]], and schematic
    1 KB (165 words) - 19:52, 10 February 2015
  • FPGA
    * Understand the different available peripherals on your system board * Run your system on the development board and collect the results.
    1,020 bytes (132 words) - 19:50, 10 February 2015
  • Hardware Accelerator Integration into Embedded Linux
    ...will be able to control the accelerator from the command line of the Linux system. :[3] [http://www.arm.com/products/system-ip/amba/amba-open-specifications.php ARM AMBA Specification]
    2 KB (236 words) - 09:46, 12 October 2017
  • PULP
    [[File:pulp_block_diag.png|thumb|400px|Basic block diagram of a PULP system.]] * [http://asic.ethz.ch/2020/Thestral.html Thestral] Snitch based system with 1x cluster (8x compute + 1x DMA core) and 1x governor core. Designed t
    10 KB (1,563 words) - 10:09, 19 August 2022
  • Indoor Positioning with Bluetooth
    [[Category:System Design]]
    3 KB (449 words) - 12:12, 4 November 2019
  • OpenRISC SoC for Sensor Applications
    ...r OpenRISC core with the following capabilities so that a standalone small system can be designed that can directly interface with various sensors and can co : For low power operations, we would like to shutdown most of the system including the processor, and wait until there is an event that requires the
    4 KB (667 words) - 15:23, 23 December 2016
  • Hardware Accelerator for Model Predictive Controller
    In recent years reseach works shows that thermal evolution of a multicore system can be effectively modelled with linear state-space representation enabling ...will then be part of a larger system and be part of the thermal management system. In this project the goal is to implement a novel MPC algorithm in hardware
    3 KB (456 words) - 08:35, 20 January 2021
  • 4th Generation Synchronization
    ..., R.N. Challa, and H.A. Mahmoud. Frequency Scan Method for Determining the System Center Frequency for LTE TDD, September 6 2013. WO Patent App. PCT/US2013/0
    2 KB (350 words) - 17:56, 14 April 2016
  • Analog
    ====[[Biomedical System on Chips|Biomedical System on Chips]]==== ...f wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless transmis
    3 KB (369 words) - 18:11, 1 March 2023
  • Ambient RF Energy harvesting for Wireless Sensor Network
    ...method by implementing our system.. Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe : Interest in Computer Architectures at system level
    3 KB (378 words) - 19:56, 9 February 2015
  • Android reliability governor
    Reliability (R(t)) is the probability that a given system does not fail before time t. It is becoming a major concern in modern multi ...bile]] [[Category:Temperature]] [[Category:Dynamic Management]] [[Category:System Design]]
    4 KB (573 words) - 17:24, 9 February 2015
  • Thermal Control of Mobile Devices
    ...s an heterogeneous thermal profile which is highly dependent on the actual system usage. As a matter of fact today and future mobile devices are thermally li ...thermal model can be directly identified from the target device by mean of system identification and self-calibrating routines.
    3 KB (452 words) - 11:03, 10 February 2015
  • Real-Time Pedestrian Detection For Privacy Enhancement
    [[Category:System Design]]
    3 KB (408 words) - 13:17, 5 February 2016
  • Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
    ...stem was proposed alongside the release-8 of the Long Term Evolution (LTE) system for the fourth generation (4G) of mobile communication. While the air inter ...tionality of a standard-compliant physical layer of a mobile communication system. Possibly, the student can also investigate and analyze an interesting perf
    1 KB (159 words) - 11:16, 23 September 2016
  • Digital Transmitter for Cellular IoT
    [1] ''Cellular system support for ultra-low complexity and low throughput Internet of Things (CIo
    3 KB (384 words) - 16:41, 17 July 2016
  • Design of an LTE Module for the Internet of Things
    ...E transceiver [2] will be used. You will start with your design by doing a system analysis on the required building blocks (Synchronization, FFT, Symbol dete [[Category:System Design]]
    3 KB (335 words) - 14:20, 4 November 2019
  • Active-Set QP Solver on FPGA
    : Matlab, C++, VHDL or System Verilog
    2 KB (351 words) - 13:09, 2 November 2015
  • LAPACK/BLAS for FPGA
    : Matlab, C++, VHDL or System Verilog
    2 KB (328 words) - 12:38, 1 June 2017
  • Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
    ...er, a careful design of each regulator is extremely important. A PCB-based system, containing of-the-shelf converter chips where available, and discrete-comp [[Category:System Design]]
    3 KB (438 words) - 18:06, 3 February 2015
  • Gomeza old project1
    ...be mapped to both cores. This results in a lower active time, allowing the system to enter a low-power sleep mode, and reduce the total energy consumption.
    3 KB (431 words) - 18:04, 28 January 2017
  • Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
    [[Category:System Design]]
    4 KB (589 words) - 10:14, 3 August 2018
  • User:Gomeza
    ...If you are interested in doing something with low-power, energy-efficient system design, just send me an e-mail. There is plenty of room for both theoretica
    890 bytes (114 words) - 19:10, 28 January 2017
  • Energy Neutral Multi Sensors Wearable Device
    : Interest in Computer Architectures at system level : Wearable system I (prof. Troester lectures)
    2 KB (319 words) - 16:24, 30 October 2020
  • Category:System Design
    ...s, microprocessors, FPGAs and get a demonstrator to work. Depending on the system this may require you to: * Program a microcontroller or a microprocessor system
    122 members (0 subcategories, 0 files) - 17:03, 3 February 2015
  • Real-Time Stereo to Multiview Conversion
    [[File:mvSystem.jpg|thumb|600px|a) Multiview system in action and b) closeup of the hardware prototype.]] Ideally, a 3D display system should not require the users to
    3 KB (509 words) - 09:09, 23 October 2015
  • Digital
    [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
    7 KB (816 words) - 11:57, 8 May 2024
  • Modeling FlooNoC in GVSoC (S/M)
    ...event-driven simulator designed for simulating IoT processors and complex system-on-chips (SoCs). It plays a crucial role in enabling agile design space exp * Experience with System Verilog is recommended but not strictly necessary
    4 KB (520 words) - 15:15, 4 December 2023
  • Time and Frequency Synchronization in LTE Cat-0 Devices
    ...k, Nitin Mangalvedhe, Amitava Ghosh, and Benny Vejlgaard. Narrowband LTE-M system for M2M communication. 2014.
    4 KB (561 words) - 10:43, 6 November 2017
  • File:Pulp block diag.png
    Block diagram of the PULP system
    (1,361 × 751 (137 KB)) - 18:47, 7 July 2015
  • Baseband Meets CPU
    is indispensable. Ideally, System-on-a-Chip (SoC) or System-in-a-Package (SiP) modems such as [1] are
    7 KB (1,105 words) - 20:02, 26 September 2017
  • Real-Time Optical Flow Using Neural Networks
    [[Category:Digital]] [[Category:System Design]]
    5 KB (707 words) - 11:22, 5 February 2016
  • An FPGA-Based Testbed for 3G Mobile Communications Receivers
    [[Category:System Design]]
    1 KB (169 words) - 16:42, 9 December 2015
  • PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
    ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...L1 scratchpad memory, and the shared main memory to optimally exploit the system's memory hierarchy and to achieve high performance.
    5 KB (716 words) - 13:43, 29 November 2019
  • DigitalUltrasoundHead
    ...e piezoelectric elements in the transducer head are connected to a backend system over a large cable containing hundreds of small coaxial cables. This is sho In order to do so, the entire analog frontend of the ultrasound system needs to be integrated into the transducer head and a digital link needs to
    3 KB (378 words) - 11:52, 10 January 2017
  • High-speed Scene Labeling on FPGA
    ...tation of an entire scene labeling network. In order to keep the developed system flexible in terms of the convolutional neural network that is applied as we ...rt software blocks to programmable logic and design an entire hetergeneous system using with software, FPGA fabric and hardwired interfaces.
    8 KB (1,197 words) - 18:18, 29 August 2016
  • Time Synchronization for 3G Mobile Communications
    [[Category:System Design]]
    3 KB (420 words) - 11:22, 14 April 2016
  • PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
    ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e This system design project requires work to be done at several layers of abstraction. M
    4 KB (585 words) - 17:57, 7 November 2017
  • PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
    ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e : VHDL/System Verilog, C
    4 KB (554 words) - 17:57, 7 November 2017
  • Autonomous Sensing For Trains In The IoT Era
    ...ment of novel zero-power sensors that act as a trigger for the rest of the system when an important event is detected and consume zero-power between two dete ...classification accuracy and energy efficiency and to further optimize the system.
    6 KB (774 words) - 08:36, 23 November 2022
  • Switched Capacitor Based Bandgap-Reference
    [[Category:System Design]] [[Category:System Design]]
    4 KB (471 words) - 11:13, 3 May 2018
  • Compressed Sensing for Wireless Biosignal Monitoring
    ...we have implemented and fabricated an 8-channel biosignal acquisition SoC (System-on-Chip) [http://asic.ee.ethz.ch/2014/CerebroV4.0_Homer.html] including ana
    2 KB (353 words) - 08:35, 20 January 2021
  • Scattering Networks for Scene Labeling
    [[Category:System Design]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Luk [[Category:Digital]] [[Category:System Design]]
    4 KB (563 words) - 11:29, 5 February 2016
  • Autonomous Smart Watches: Hardware and Software Desing
    ...classification accuracy and energy efficiency and to further optimize the system. : Interest in Computer Architectures at system level
    3 KB (448 words) - 11:59, 28 July 2015
  • A Wearable System for long term monitoring of human physiological parameters with E skin sensors
    : Interest in Computer Architectures at system level ...arning would be beneficial (i.e. semester project or exam done in Wearable system I prof. Troester)
    3 KB (380 words) - 11:59, 28 July 2015
  • Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
    [[Category:System Design]]
    4 KB (507 words) - 12:11, 16 February 2016

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