Difference between revisions of "Category:Digital"
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Revision as of 14:45, 16 January 2014
Projects that are part of the Digital Circuits and Systems group
Pages in category "Digital"
The following 200 pages are in this category, out of 607 total.
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- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- EvalEDGE: A 2G Cellular Transceiver FMC
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Evaluating An Ultra low Power Vision Node
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating the RiscV Architecture
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Event-based navigation on autonomous nano-drones
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring NAS spaces with C-BRED
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fabian Schuiki
- Fast Accelerator Context Switch for PULP
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fast Simulation of Manycore Systems (1S)
- Fast Wakeup From Deep Sleep State
- Fault-Tolerant Floating-Point Units (M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- FFT-based Convolutional Network Accelerator
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- User:Fischeti
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Floating-Point Divide & Square Root Unit for Transprecision
- FPGA mapping of RPC DRAM
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- Frank K. Gürkaynak
- Freedom from Interference in Heterogeneous COTS SoCs
G
H
- Harald Kröll
- Hardware Accelerated Derivative Pricing
- Hardware Accelerator for Model Predictive Controller
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Hardware Constrained Neural Architechture Search
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Hardware Support for IDE in Multicore Environment
- Hardware/software co-programming on the Parallella platform
- Hardware/software codesign neural decoding algorithm for “neural dust”
- HERO: TLB Invalidation
- Heroino: Design of the next CORE-V Microcontroller
- Herschmi
- User:Herschmi
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High-speed Scene Labeling on FPGA
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Huawei Research
- Human Intranet
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- IBM Research
- Image and Video Processing
- Image Sensor Interface and Pre-processing
- Implementation of a Cache Reliability Mechanism (1S/M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a NB-IoT Positioning System
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an Accelerator for Retentive Networks (1-2S)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing A Low-Power Sensor Node Network
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Implementing Hibernation on the ARM Cortex M0
- Improved Collision Avoidance for Nano-drones
- Improved Reacquisition for the 5G Cellular IoT
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Improving datarate and efficiency of ultra low power wearable ultrasound
- Improving our Smart Camera System
- Improving Resiliency of Hyperdimensional Computing
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- In-ear EEG signal acquisition
- Indoor Positioning with Bluetooth
- Indoor Smart Tracking of Hospital instrumentation
- Infrared Wake Up Radio
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Integrating Hardware Accelerators into Snitch (1S)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Integration Of A Smart Vision System
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Interference Cancellation for EC-GSM-IoT
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- IoT Turbo Decoder
- IP-Based SoC Generation and Configuration (1-3S/B)
- ISA extensions in the Snitch Processor for Signal Processing (M)
K
L
- User:Lbertaccini
- Learning at the Edge with Hardware-Aware Algorithms
- Learning Image Compression with Convolutional Networks
- Learning Image Decompression with Convolutional Networks
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Libria
- LightProbe
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - CNN-Based-Image-Reconstruction
- LightProbe - Design of a High-Speed Optical Link
- LightProbe - Frontend Firmware and Control Side Channel
- LightProbe - Implementation of compressed-sensing algorithms
- LightProbe - Thermal-Power aware on-head Beamforming
- LightProbe - Ultracompact Power Supply PCB
- LightProbe - WIFI extension (PCB)
- LLVM and DaCe for Snitch (1-2S)
- Low Latency Brain-Machine Interfaces
- Low Power Geolocalization And Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Precision Ara for ML
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Low-power Clock Generation Solutions for 65nm Technology
- LTE IoT Network Synchronization
- User:Lukasc
M
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Machine Learning on Ultrasound Images
- User:Mandrea
- Manycore System on FPGA (M/S/G)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Matheus Cavalcante
- User:Matheusd
- Matthias Korb
- Mauro Salomon
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- User:Meggiman
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- MemPool on HERO (1S)
- Minimal Cost RISC-V core
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- User:Mmaxim
- Modeling FlooNoC in GVSoC (S/M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Modular Distributed Data Collection Platform
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- Moritz Schneider
- Multi issue OoO Ariane Backend (M)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
N
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Network-off-Chip (M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- NeuroSoC RISC-V Component (M/1-2S)
- New RVV 1.0 Vector Instructions for Ara
- Next Generation Channel Decoder
- Next Generation Synchronization Signals
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
- Non-binary LDPC Decoder for Deep-Space Optical Communications
- Non-blocking Algorithms in Real-Time Operating Systems
- Norbert Felber
- NORX - an AEAD algorithm for the CAESAR competition