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Showing below up to 100 results in range #101 to #200.

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  1. (hist) ‎PREM on PULP ‎[1,304 bytes]
  2. (hist) ‎Configurable Ultra Low Power LDO ‎[1,306 bytes]
  3. (hist) ‎Exploring Algorithms for Early Seizure Detection ‎[1,329 bytes]
  4. (hist) ‎SW/HW Predictability and Security ‎[1,333 bytes]
  5. (hist) ‎Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) ‎[1,378 bytes]
  6. (hist) ‎Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) ‎[1,408 bytes]
  7. (hist) ‎Design of low mismatch DAC used for VAD ‎[1,409 bytes]
  8. (hist) ‎Scan Chain Fault Injection in a PULP SoC (1S) ‎[1,421 bytes]
  9. (hist) ‎Receiver design for the DigRF 4G high speed serial link ‎[1,431 bytes]
  10. (hist) ‎Beat Cadence ‎[1,442 bytes]
  11. (hist) ‎Precise Ultra-low-power Timer ‎[1,446 bytes]
  12. (hist) ‎Digital Audio Processor for Cellular Applications ‎[1,448 bytes]
  13. (hist) ‎Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) ‎[1,466 bytes]
  14. (hist) ‎Multiuser Equalization and Detection for 3GPP TD-SCDMA ‎[1,484 bytes]
  15. (hist) ‎Creating A Boundry Scan Generator (1-3S/B/2-3G) ‎[1,488 bytes]
  16. (hist) ‎Design of a D-Band Variable Gain Amplifier for 6G Communication ‎[1,522 bytes]
  17. (hist) ‎Positioning for the cellular Internet of Things ‎[1,525 bytes]
  18. (hist) ‎ASIC Design of a Gaussian Message Passing Processor ‎[1,526 bytes]
  19. (hist) ‎Pirmin Vogel ‎[1,528 bytes]
  20. (hist) ‎Novel Metastability Mitigation Technique ‎[1,561 bytes]
  21. (hist) ‎High resolution, low power Sigma Delta ADC ‎[1,568 bytes]
  22. (hist) ‎Marco Bertuletti ‎[1,571 bytes]
  23. (hist) ‎Hardware Accelerator Integration into Embedded Linux ‎[1,578 bytes]
  24. (hist) ‎LightProbe - CNN-Based-Image-Reconstruction ‎[1,582 bytes]
  25. (hist) ‎Hardware Support for IDE in Multicore Environment ‎[1,591 bytes]
  26. (hist) ‎Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) ‎[1,597 bytes]
  27. (hist) ‎Ultrasound signal processing acceleration with CUDA ‎[1,600 bytes]
  28. (hist) ‎Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) ‎[1,645 bytes]
  29. (hist) ‎Synchronisation and Cyclic Prefix Handling For LTE Testbed ‎[1,649 bytes]
  30. (hist) ‎Audio Video Preprocessing In Parallel Ultra Low Power Platform ‎[1,650 bytes]
  31. (hist) ‎Fast Wakeup From Deep Sleep State ‎[1,665 bytes]
  32. (hist) ‎Fault Tolerance ‎[1,665 bytes]
  33. (hist) ‎EvaLTE: A 2G/3G/4G Cellular Transceiver FMC ‎[1,679 bytes]
  34. (hist) ‎Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) ‎[1,705 bytes]
  35. (hist) ‎GSM Voice Capacity Evolution - VAMOS ‎[1,707 bytes]
  36. (hist) ‎Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) ‎[1,722 bytes]
  37. (hist) ‎Design and Implementation of a multi-mode multi-master I2C peripheral ‎[1,729 bytes]
  38. (hist) ‎Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) ‎[1,729 bytes]
  39. (hist) ‎System Analysis and VLSI Design of NB-IoT Baseband Processing ‎[1,736 bytes]
  40. (hist) ‎Toward Superposition of Brain-Computer Interface Models ‎[1,758 bytes]
  41. (hist) ‎State-Saving @ NXP ‎[1,767 bytes]
  42. (hist) ‎Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) ‎[1,776 bytes]
  43. (hist) ‎Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) ‎[1,794 bytes]
  44. (hist) ‎Power Saver Mode for Cellular Internet of Things Receivers ‎[1,795 bytes]
  45. (hist) ‎Bluetooth Low Energy receiver in 65nm CMOS ‎[1,795 bytes]
  46. (hist) ‎Adding Linux Support to our DMA Engine (1-2S/B) ‎[1,795 bytes]
  47. (hist) ‎LTE-Advanced RF Front-end Design in 28nm CMOS Technology ‎[1,811 bytes]
  48. (hist) ‎5G Cellular RF Front-end Design in 22nm CMOS Technology ‎[1,818 bytes]
  49. (hist) ‎AXI-based Network on Chip (NoC) system ‎[1,825 bytes]
  50. (hist) ‎Energy Efficient Serial Link ‎[1,833 bytes]
  51. (hist) ‎LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) ‎[1,841 bytes]
  52. (hist) ‎Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets ‎[1,852 bytes]
  53. (hist) ‎Open Source Baseband Firmware for 2G Cellular Networks ‎[1,858 bytes]
  54. (hist) ‎Interference Cancellation for the cellular Internet of Things ‎[1,860 bytes]
  55. (hist) ‎Bluetooth Low Energy network with optimized data throughput ‎[1,860 bytes]
  56. (hist) ‎Ultrasound Low power WiFi with IMX7 ‎[1,861 bytes]
  57. (hist) ‎Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets ‎[1,863 bytes]
  58. (hist) ‎Fast and Accurate Multiclass Inference for Brain–Computer Interfaces ‎[1,865 bytes]
  59. (hist) ‎Low-Dropout Regulators for Magnetic Resonance Imaging ‎[1,867 bytes]
  60. (hist) ‎Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) ‎[1,878 bytes]
  61. (hist) ‎Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf ‎[1,896 bytes]
  62. (hist) ‎Implementation of a Coherent Application-Class Multicore System (1-2S) ‎[1,897 bytes]
  63. (hist) ‎Multi-Band Receiver Design for LTE Mobile Communication ‎[1,907 bytes]
  64. (hist) ‎LightProbe ‎[1,907 bytes]
  65. (hist) ‎Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA ‎[1,914 bytes]
  66. (hist) ‎Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) ‎[1,929 bytes]
  67. (hist) ‎Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen ‎[1,931 bytes]
  68. (hist) ‎Enabling Standalone Operation for a Mobile Health Platform ‎[1,934 bytes]
  69. (hist) ‎Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC ‎[1,946 bytes]
  70. (hist) ‎GUI-developement for an action-cam-based eye tracking device ‎[1,949 bytes]
  71. (hist) ‎High Performance Cellular Receivers in Very Advanced CMOS ‎[1,952 bytes]
  72. (hist) ‎Make Cellular Internet of Things Receivers Smart ‎[1,954 bytes]
  73. (hist) ‎Towards Formal Verification of the iDMA Engine (1-3S/B) ‎[1,954 bytes]
  74. (hist) ‎Non-binary LDPC Decoder for Deep-Space Optical Communications ‎[1,958 bytes]
  75. (hist) ‎Jammer-Resilient Synchronization for Wireless Communications ‎[1,962 bytes]
  76. (hist) ‎Wireless Biomedical Signal Acquisition Device ‎[1,982 bytes]
  77. (hist) ‎3D Ultrasound Bubble Tracking ‎[1,982 bytes]
  78. (hist) ‎RazorEDGE: An Evolved EDGE DBB ASIC ‎[1,995 bytes]
  79. (hist) ‎Implementation of a Cache Reliability Mechanism (1S/M) ‎[1,996 bytes]
  80. (hist) ‎ASIC Design of a Sigma Point Processor ‎[1,998 bytes]
  81. (hist) ‎Beat DigRF ‎[2,000 bytes]
  82. (hist) ‎Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening ‎[2,001 bytes]
  83. (hist) ‎Energy Efficient AXI Interface to Serial Link Physical Layer ‎[2,020 bytes]
  84. (hist) ‎High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS ‎[2,024 bytes]
  85. (hist) ‎Signal to Noise Ratio Estimation for 3G standards ‎[2,025 bytes]
  86. (hist) ‎Channel Estimation for TD-HSPA ‎[2,028 bytes]
  87. (hist) ‎Event-Driven Computing ‎[2,043 bytes]
  88. (hist) ‎Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC ‎[2,044 bytes]
  89. (hist) ‎Acceleration and Transprecision ‎[2,054 bytes]
  90. (hist) ‎Implementation of an AES Hardware Processing Engine (B/S) ‎[2,064 bytes]
  91. (hist) ‎Analog building blocks for mmWave manipulation ‎[2,064 bytes]
  92. (hist) ‎Intelligent Power Management Unit (iPMU) ‎[2,067 bytes]
  93. (hist) ‎Compression of Ultrasound data on FPGA ‎[2,067 bytes]
  94. (hist) ‎Predictable Execution ‎[2,068 bytes]
  95. (hist) ‎Machine Learning on Ultrasound Images ‎[2,071 bytes]
  96. (hist) ‎Design of a Digital Audio Module for Ultra-Low Power Cellular Applications ‎[2,072 bytes]
  97. (hist) ‎Improving Resiliency of Hyperdimensional Computing ‎[2,073 bytes]
  98. (hist) ‎Audio DAC Conversion Jitter Measurement System ‎[2,075 bytes]
  99. (hist) ‎Sub Noise Floor Channel Estimation for the Cellular Internet of Things ‎[2,078 bytes]
  100. (hist) ‎Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) ‎[2,089 bytes]

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