Short pages
From iis-projects
Showing below up to 100 results in range #101 to #200.
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- (hist) PREM on PULP [1,304 bytes]
- (hist) Configurable Ultra Low Power LDO [1,306 bytes]
- (hist) Exploring Algorithms for Early Seizure Detection [1,329 bytes]
- (hist) SW/HW Predictability and Security [1,333 bytes]
- (hist) Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) [1,378 bytes]
- (hist) Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) [1,408 bytes]
- (hist) Design of low mismatch DAC used for VAD [1,409 bytes]
- (hist) Scan Chain Fault Injection in a PULP SoC (1S) [1,421 bytes]
- (hist) Receiver design for the DigRF 4G high speed serial link [1,431 bytes]
- (hist) Beat Cadence [1,442 bytes]
- (hist) Precise Ultra-low-power Timer [1,446 bytes]
- (hist) Digital Audio Processor for Cellular Applications [1,448 bytes]
- (hist) Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) [1,466 bytes]
- (hist) Multiuser Equalization and Detection for 3GPP TD-SCDMA [1,484 bytes]
- (hist) Creating A Boundry Scan Generator (1-3S/B/2-3G) [1,488 bytes]
- (hist) Design of a D-Band Variable Gain Amplifier for 6G Communication [1,522 bytes]
- (hist) Positioning for the cellular Internet of Things [1,525 bytes]
- (hist) ASIC Design of a Gaussian Message Passing Processor [1,526 bytes]
- (hist) Pirmin Vogel [1,528 bytes]
- (hist) Novel Metastability Mitigation Technique [1,561 bytes]
- (hist) High resolution, low power Sigma Delta ADC [1,568 bytes]
- (hist) Marco Bertuletti [1,571 bytes]
- (hist) Hardware Accelerator Integration into Embedded Linux [1,578 bytes]
- (hist) LightProbe - CNN-Based-Image-Reconstruction [1,582 bytes]
- (hist) Hardware Support for IDE in Multicore Environment [1,591 bytes]
- (hist) Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) [1,597 bytes]
- (hist) Ultrasound signal processing acceleration with CUDA [1,600 bytes]
- (hist) Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) [1,645 bytes]
- (hist) Synchronisation and Cyclic Prefix Handling For LTE Testbed [1,649 bytes]
- (hist) Audio Video Preprocessing In Parallel Ultra Low Power Platform [1,650 bytes]
- (hist) Fast Wakeup From Deep Sleep State [1,665 bytes]
- (hist) Fault Tolerance [1,665 bytes]
- (hist) EvaLTE: A 2G/3G/4G Cellular Transceiver FMC [1,679 bytes]
- (hist) Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) [1,705 bytes]
- (hist) GSM Voice Capacity Evolution - VAMOS [1,707 bytes]
- (hist) Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) [1,722 bytes]
- (hist) Design and Implementation of a multi-mode multi-master I2C peripheral [1,729 bytes]
- (hist) Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) [1,729 bytes]
- (hist) System Analysis and VLSI Design of NB-IoT Baseband Processing [1,736 bytes]
- (hist) Toward Superposition of Brain-Computer Interface Models [1,758 bytes]
- (hist) State-Saving @ NXP [1,767 bytes]
- (hist) Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) [1,776 bytes]
- (hist) Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) [1,794 bytes]
- (hist) Power Saver Mode for Cellular Internet of Things Receivers [1,795 bytes]
- (hist) Bluetooth Low Energy receiver in 65nm CMOS [1,795 bytes]
- (hist) Adding Linux Support to our DMA Engine (1-2S/B) [1,795 bytes]
- (hist) LTE-Advanced RF Front-end Design in 28nm CMOS Technology [1,811 bytes]
- (hist) 5G Cellular RF Front-end Design in 22nm CMOS Technology [1,818 bytes]
- (hist) AXI-based Network on Chip (NoC) system [1,825 bytes]
- (hist) Energy Efficient Serial Link [1,833 bytes]
- (hist) LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) [1,841 bytes]
- (hist) Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets [1,852 bytes]
- (hist) Open Source Baseband Firmware for 2G Cellular Networks [1,858 bytes]
- (hist) Interference Cancellation for the cellular Internet of Things [1,860 bytes]
- (hist) Bluetooth Low Energy network with optimized data throughput [1,860 bytes]
- (hist) Ultrasound Low power WiFi with IMX7 [1,861 bytes]
- (hist) Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets [1,863 bytes]
- (hist) Fast and Accurate Multiclass Inference for Brain–Computer Interfaces [1,865 bytes]
- (hist) Low-Dropout Regulators for Magnetic Resonance Imaging [1,867 bytes]
- (hist) Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) [1,878 bytes]
- (hist) Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf [1,896 bytes]
- (hist) Implementation of a Coherent Application-Class Multicore System (1-2S) [1,897 bytes]
- (hist) Multi-Band Receiver Design for LTE Mobile Communication [1,907 bytes]
- (hist) LightProbe [1,907 bytes]
- (hist) Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA [1,914 bytes]
- (hist) Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) [1,929 bytes]
- (hist) Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen [1,931 bytes]
- (hist) Enabling Standalone Operation for a Mobile Health Platform [1,934 bytes]
- (hist) Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC [1,946 bytes]
- (hist) GUI-developement for an action-cam-based eye tracking device [1,949 bytes]
- (hist) High Performance Cellular Receivers in Very Advanced CMOS [1,952 bytes]
- (hist) Make Cellular Internet of Things Receivers Smart [1,954 bytes]
- (hist) Towards Formal Verification of the iDMA Engine (1-3S/B) [1,954 bytes]
- (hist) Non-binary LDPC Decoder for Deep-Space Optical Communications [1,958 bytes]
- (hist) Jammer-Resilient Synchronization for Wireless Communications [1,962 bytes]
- (hist) Wireless Biomedical Signal Acquisition Device [1,982 bytes]
- (hist) 3D Ultrasound Bubble Tracking [1,982 bytes]
- (hist) RazorEDGE: An Evolved EDGE DBB ASIC [1,995 bytes]
- (hist) Implementation of a Cache Reliability Mechanism (1S/M) [1,996 bytes]
- (hist) ASIC Design of a Sigma Point Processor [1,998 bytes]
- (hist) Beat DigRF [2,000 bytes]
- (hist) Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening [2,001 bytes]
- (hist) Energy Efficient AXI Interface to Serial Link Physical Layer [2,020 bytes]
- (hist) High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS [2,024 bytes]
- (hist) Signal to Noise Ratio Estimation for 3G standards [2,025 bytes]
- (hist) Channel Estimation for TD-HSPA [2,028 bytes]
- (hist) Event-Driven Computing [2,043 bytes]
- (hist) Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC [2,044 bytes]
- (hist) Acceleration and Transprecision [2,054 bytes]
- (hist) Implementation of an AES Hardware Processing Engine (B/S) [2,064 bytes]
- (hist) Analog building blocks for mmWave manipulation [2,064 bytes]
- (hist) Intelligent Power Management Unit (iPMU) [2,067 bytes]
- (hist) Compression of Ultrasound data on FPGA [2,067 bytes]
- (hist) Predictable Execution [2,068 bytes]
- (hist) Machine Learning on Ultrasound Images [2,071 bytes]
- (hist) Design of a Digital Audio Module for Ultra-Low Power Cellular Applications [2,072 bytes]
- (hist) Improving Resiliency of Hyperdimensional Computing [2,073 bytes]
- (hist) Audio DAC Conversion Jitter Measurement System [2,075 bytes]
- (hist) Sub Noise Floor Channel Estimation for the Cellular Internet of Things [2,078 bytes]
- (hist) Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) [2,089 bytes]