Difference between revisions of "Brunn test"
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Revision as of 11:12, 3 May 2018
- Ultrasound Doppler system development
- Ultrasound-EMG combined hand gesture recognition
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Exploring NAS spaces with C-BRED
- Bandwidth Efficient NEureka
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Resource Partitioning of Caches
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Enabling Efficient Systolic Execution on MemPool (M)
- Network-off-Chip (M)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Evaluating SoA Post-Training Quantization Algorithms
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Smart e-glasses for concealed recording of EEG signals
- Transformer Deployment on Heterogeneous Many-Core Systems
- Smart Meters
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Wireless EEG Acquisition and Processing
- Development of statistics and contention monitoring unit for PULP
- Implementing Configurable Dual-Core Redundancy
- Running Rust on PULP
- Ultrasound based hand gesture recognition
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Weak-strong massive MIMO communication with low-resolution ADCs
- Novel Methods for Jammer Mitigation
- ASIC Implementation of Jammer Mitigation
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Bridging QuantLab with LPDNN
- Bluetooth Low Energy receiver in 65nm CMOS
- Design of MEMs Sensor Interface
- Precise Ultra-low-power Timer
- Novel Metastability Mitigation Technique
- Analog Compute-in-Memory Accelerator Interface and Integration
- Wearables in Fashion
- Outdoor Precision Object Tracking for Rockfall Experiments
- Autonomous Sensing For Trains In The IoT Era
- CLIC for the CVA6
- Flexfloat DL Training Framework
- Online Learning of User Features (1S)
- Feature Extraction for Speech Recognition (1S)
- SCMI Support for Power Controller Subsystem
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Aliasing-Free Wavetable Music Synthesizer
- Implementing DSP Instructions in Banshee (1S)
- Streaming Integer Extensions for Snitch (M/1-2S)
- Efficient Synchronization of Manycore Systems (M/1S)
- Design of combined Ultrasound and Electromyography systems
- Designing a Power Management Unit for PULP SoCs
- A Unified Compute Kernel Library for Snitch (1-2S)
- PULP’s CLIC extensions for fast interrupt handling
- Cell-Free mmWave Massive MIMO Communication
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Triple-Core PULPissimo
- Watchdog Timer for PULP
- Hypervisor Extension for Ariane (M)
- Advanced 5G Repetition Combining
- Next Generation Synchronization Signals
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Low-power Temperature-insensitive Timer
- Improved State Estimation on PULP-based Nano-UAVs
- Ultra low power wearable ultrasound probe
- Machine Learning for extracting Muscle features using Ultrasound 2
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Hardware Constrained Neural Architechture Search
- Implementation of an AES Hardware Processing Engine (B/S)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Transforming MemPool into a CGRA (M)
- Multi issue OoO Ariane Backend (M)
- Exploring schedules for incremental and annealing quantization algorithms
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Hyper-Dimensional Computing Based Predictive Maintenance
- Low Latency Brain-Machine Interfaces
- Ultrasound Low power WiFi with IMX7
- Ultrasound signal processing acceleration with CUDA
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Machine Learning for extracting Muscle features using Ultrasound
- Compression of Ultrasound data on FPGA
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Inductive Charging Circuit for Implantable Devices
- Ultra-low power transceiver for implantable devices
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- Low-Dropout Regulators for Magnetic Resonance Imaging
- DC-DC Buck converter in 65nm CMOS
- Semi-Custom Digital VLSI for Processing-in-Memory
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- LLVM and DaCe for Snitch (1-2S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Manycore System on FPGA (M/S/G)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- Time Gain Compensation for Ultrasound Imaging
- Neural Networks Framwork for Embedded Plattforms
- Stand-Alone Edge Computing with GAP8
- Securing Block Ciphers against SCA and SIFA
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- Design and Evaluation of a Small Size Avalanche Beacon
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- MemPool on HERO (1S)
- NVDLA meets PULP
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- A Recurrent Neural Network Speech Recognition Chip
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- Deep Convolutional Autoencoder for iEEG Signals
- Ibex: FPGA Optimizations
- Ibex: Bit-Manipulation Extension
- Floating-Point Divide & Square Root Unit for Transprecision
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- TCNs vs. LSTMs for Embedded Platforms
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- Timing Channel Mitigations for RISC-V Cores
- A computational memory unit using phase-change memory devices
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time ECG Contractions Classification
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Exploring Algorithms for Early Seizure Detection
- HERO: TLB Invalidation
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Indoor Positioning with Bluetooth
- Improving Resiliency of Hyperdimensional Computing
- Toward Superposition of Brain-Computer Interface Models
- Predictable Execution on GPU Caches
- Freedom from Interference in Heterogeneous COTS SoCs
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- CMOS power amplifier for field measurements in MRI systems
- Ultra-low power sampling front-end for acquisition of physiological signals
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Deep Learning for Brain-Computer Interface
- LightProbe - WIFI extension (PCB)
- Digital Audio Interface for Smart Intensive Computing Triggering
- Trace Debugger for custom RISC-V Core
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Turbo Equalization for Cellular IoT
- Shared Correlation Accelerator for an RF SoC
- IoT Turbo Decoder
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Sensor Fusion for Rockfall Sensor Node
- Development of a Rockfall Sensor Node
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Intelligent Power Management Unit (iPMU)
- Ultrafast Medical Ultrasound imaging on a GPU
- LightProbe - Implementation of compressed-sensing algorithms
- A Wireless Sensor Network for a Smart Building Monitor and Control
- Creating a HDMI Video Interface for PULP
- Standard Cell Compatible Memory Array Design
- Efficient NB-IoT Uplink Design
- Interference Cancellation for EC-GSM-IoT
- A Wireless Sensor Network for HPC monitoring
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Study and Development of Intelligent Capability for Small-Size UAVs
- Towards Autonomous Navigation for Nano-Blimps
- PULP-Shield for Autonomous UAV
- Self-Learning Drones based on Neural Networks
- BigPULP: Multicluster Synchronization Extensions
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
- Design of low-offset dynamic comparators
- Switched Capacitor Based Bandgap-Reference
- Smart Virtual Memory Sharing