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• Ultra-low power processor design
  [[File:Ultra-low power processor design.jpg|thumb]] ...use a state of the art 28nm SOI process to evaluate the performance of the processor.
  10 KB (1,669 words) - 19:01, 30 January 2014
• SHAre - An application Specific Instruction Set Processor for SHA-2/3
  2 KB (302 words) - 12:09, 26 March 2015
• DMA Streaming Co-processor
  ...le:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]] ...icient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability.
  2 KB (344 words) - 10:30, 5 November 2019
• ASIC Design of a Gaussian Message Passing Processor
  ...is usually attached as a fixed-function-unit to a heterogeneous multicore processor. The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod
  1 KB (210 words) - 08:34, 20 January 2021
• ASIC Design of a Sigma Point Processor
  ...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this ...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.
  2 KB (265 words) - 08:34, 20 January 2021
• Vector Processor for In-Memory Computing
  ...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r : Interest in processor design
  3 KB (443 words) - 13:10, 2 November 2015
• Digital Audio Processor for Cellular Applications
  ...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp
  1 KB (229 words) - 18:01, 29 March 2017
• Baseband Processor Development for 4G IoT
  The goal of this project is to design a processor using existing components and port it to an FPGA-based prototyping platform
  2 KB (347 words) - 17:58, 14 April 2016
• Design of a VLIW processor architecture based on RISC-V
  ...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
  3 KB (377 words) - 10:25, 5 November 2019
• Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
  ...d system architecture will be developed around an Ultra low power parallel processor developed at IIS to show to be ideally suited to interface
  4 KB (518 words) - 11:40, 2 February 2018
• Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
  ...ery effectively, providing better energy efficiency than a general purpose processor for applications that fit its execution model. ...ner, Luca Benini. Ara: A 1GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22nm FD-SOI. [https://doi.or
  4 KB (627 words) - 14:42, 29 October 2020
• Real-Time Motor-Imagery Classification Using Neuromorphic Processor
  ...classes motor-imagery and often they are not implemented in a neuromorphic processor, and none of them are presenting a whole system from the data acquisition t
  6 KB (815 words) - 20:02, 10 March 2024
• ISA extensions in the Snitch Processor for Signal Processing (1M)
  0 bytes (0 words) - 19:24, 2 November 2020
• ISA extensions in the Snitch Processor for Signal Processing (M)
  ...nally, it can support he ‘M’ and ‘F’ extension through a custom co-processor interface. However, currently, there is no support for domain-specific inst ...the OpenHW Group [<nowiki/>[[#ref-CV32E40P|7]]]. It is a 32-bit in-order processor with 4 pipeline stages. In contrast to Snitch, it features custom DSP instr
  9 KB (1,311 words) - 00:08, 13 March 2021
• Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
  <!-- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) --> The aim of this project is to design a reconfigurable vector processor cluster for area-optimized, yet compute and energy-efficient, radar signal
  5 KB (651 words) - 20:42, 22 November 2022

Page text matches

• Ultra-low power processor design
  [[File:Ultra-low power processor design.jpg|thumb]] ...use a state of the art 28nm SOI process to evaluate the performance of the processor.
  10 KB (1,669 words) - 19:01, 30 January 2014
• Variability Tolerant Ultra Low Power Cluster
  At the IIS we are working on an ultra low-power multi-processor (PULP) multi-processor shared-memory cluster.
  3 KB (409 words) - 10:52, 27 March 2014
• Template
  [[Category:Processor]]
  4 KB (397 words) - 15:44, 14 February 2023
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  [[Category:Processor]]
  6 KB (741 words) - 18:14, 21 July 2023
• Accelerators for object detection and tracking
  At the IIS we are working on an ultra low-power multi-processor processing applications that can be included in the multi-processor
  3 KB (407 words) - 10:57, 5 November 2019
• Digital Audio High Level Synthesis for FPGAs
  #REDIRECT [[Digital Audio Processor for Cellular Applications]]
  63 bytes (7 words) - 16:36, 3 August 2015
• CPS Software-Configurable State-Machine
  ...ry simple tasks at a very low power budget, without having to power up the processor. Together with a low power timer, the state-machine forms what we call the
  3 KB (418 words) - 11:24, 10 November 2017
• Design and Implementation of an Approximate Floating Point Unit
  ...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi ...referred algorithm in hardware such that it can be integrated in the multi-processor platform.
  3 KB (377 words) - 10:58, 21 February 2018
• Putting Together What Fits Together - GrÆStl
  GrÆStl cryptographic co-processor. Bottom: Photo of the manufactured Chameleon chip, host- ...r to accelerate the computations of the cryptographic primitives. Both the processor and GrÆStl were ported onto a low-cost FPGA and finally a comparison betwe
  3 KB (434 words) - 12:01, 26 March 2015
• Digitally-Controlled Analog Subtractive Sound Synthesis
  [[Category:Processor]]
  5 KB (597 words) - 12:56, 4 December 2021
• MatPHY: An Open-Source Physical Layer Development Framework
  ...e physical baseband receiver that is typically implemented on the baseband processor, assisted by accelerator blocks in dedicated hardware including TPU, digita
  3 KB (360 words) - 14:14, 27 May 2015
• Evolved EDGE Physical Layer Incremental Redundancy Architecture
  ...cessor. The decoding of the RLC blocks takes place on a PHY Digital Signal Processor (DSP) and an accelerator attached to it.
  3 KB (397 words) - 14:12, 27 May 2015
• IcySoC
  ...n in terms of usage of hardware accelerators, heterogeneous or homogeneous processor cores and of communication or network-on-chip that has to be implemented fo
  4 KB (568 words) - 12:48, 9 February 2015
• DMA Streaming Co-processor
  ...le:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]] ...icient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability.
  2 KB (344 words) - 10:30, 5 November 2019
• Improving Scene Labeling with Hyperspectral Data
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  6 KB (941 words) - 11:29, 5 February 2016
• A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  An application-specific instruction-set processor (ASIP) tailored to In addition to the "pseudo-processor-controlled approach", the
  2 KB (326 words) - 12:26, 26 March 2015
• Hardware Accelerator Integration into Embedded Linux
  :[1] [http://arxiv.org/abs/1404.3162 A Signal Processor for Gaussian Message Passing]
  2 KB (236 words) - 09:46, 12 October 2017
• PULP
  * [http://asic.ethz.ch/2021/Marsellus.html Marsellus] IoT processor based on PULPopen * [http://asic.ethz.ch/2021/Kraken.html Kraken] IoT Processor with 3 accelerators based on PULPopen. Total of 9x 32bit RI5CY cores.
  10 KB (1,563 words) - 10:09, 19 August 2022
• Indoor Positioning with Bluetooth
  [[Category:Processor]]
  3 KB (449 words) - 12:12, 4 November 2019
• OpenRISC SoC for Sensor Applications
  ...mplementation of the OpenRisc was completed as part of a [[Ultra-low power processor design | previous semester thesis]]. We are already using this core in our ...e, during this wake up it will store the incoming message and allowing the processor to access the incoming data and react to it.
  4 KB (667 words) - 15:23, 23 December 2016
• ASIC Design of a Gaussian Message Passing Processor
  ...is usually attached as a fixed-function-unit to a heterogeneous multicore processor. The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod
  1 KB (210 words) - 08:34, 20 January 2021
• Analog
  ...sed measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recor ...he field of wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless t
  3 KB (369 words) - 18:11, 1 March 2023
• ASIC Design of a Sigma Point Processor
  ...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this ...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.
  2 KB (265 words) - 08:34, 20 January 2021
• Android reliability governor
  Dynamic Reliability Management (DRM) techniques aims at trading-off processor performance with lifetime at run-time by modulating the working temperature
  4 KB (573 words) - 17:24, 9 February 2015
• Design of an LTE Module for the Internet of Things
  [[Category:Processor]]
  3 KB (335 words) - 14:20, 4 November 2019
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  9 KB (1,289 words) - 19:45, 24 March 2015
• Low-power Clock Generation Solutions for 65nm Technology
  operating voltage, the clock rate of such a processor will be between
  3 KB (466 words) - 19:37, 3 March 2016
• Evaluating the RiscV Architecture
  [[Category:Processor]]
  3 KB (374 words) - 16:24, 30 October 2020
• Hardware/software co-programming on the Parallella platform
  ...power platform similar to the Raspberry Pi. It features a dual-core ARM A9 processor running Linux, a powerful FPGA and a 16-core accelerator chip called "Epiph
  3 KB (501 words) - 14:26, 2 September 2015
• Gomeza old project1
  # Characterization of the time/memory overhead incurred by the inter-processor communication.
  3 KB (431 words) - 18:04, 28 January 2017
• Acceleration and Transprecision
  ...e the backbone of big data and scientific computing. While general purpose processor architectures such as Intel's x86 provide good performance across a wide va
  2 KB (275 words) - 17:05, 24 November 2023
• Linear Solvers for Image and Video Processing Applications
  #REDIRECT [[DMA Streaming Co-processor]]
  40 bytes (4 words) - 18:10, 14 April 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance. ...n allows the programmer to share virtual address pointers between the host processor and the accelerator in a completely transparent manner, it still requires t
  5 KB (716 words) - 13:43, 29 November 2019
• Vector Processor for In-Memory Computing
  ...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r : Interest in processor design
  3 KB (443 words) - 13:10, 2 November 2015
• FFT-based Convolutional Network Accelerator
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  8 KB (1,145 words) - 11:30, 5 February 2016
• High-speed Scene Labeling on FPGA
  ...the types of layer in the ConvNet, interaction between a flow controlling processor (e.g. an ARM core on a Xilinx Zynq) and the programmable logic is foreseen. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  8 KB (1,197 words) - 18:18, 29 August 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  4 KB (585 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  4 KB (554 words) - 17:57, 7 November 2017
• Digital Audio Processor for Cellular Applications
  ...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp
  1 KB (229 words) - 18:01, 29 March 2017
• Switched Capacitor Based Bandgap-Reference
  [[Category:Processor]]
  4 KB (471 words) - 11:13, 3 May 2018
• Baseband Processor Development for 4G IoT
  The goal of this project is to design a processor using existing components and port it to an FPGA-based prototyping platform
  2 KB (347 words) - 17:58, 14 April 2016
• An FPGA-Based Testbed for 4G/LTE Mobile Communication
  #REDIRECT [[Baseband Processor Development for 4G IoT]]
  55 bytes (7 words) - 14:46, 28 May 2015
• Improving our Smart Camera System
  ...X1 board to get best performance transferring data from the sensor to the processor. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  8 KB (1,176 words) - 16:26, 30 October 2020
• System Analysis and VLSI Design of NB-IoT Baseband Processing
  [[File:lteTestbed.jpg|thumb|Figure 2: LTE testbed with digital baseband and processor on an FPGA and RF-IC on the [[evaLTE]] FMC module.]]
  2 KB (245 words) - 10:39, 6 November 2017
• Implementing Hibernation on the ARM Cortex M0
  ...ailable before the power outage, i.e., the supply voltage is dropping, the processor state can be saved only when a power outage is imminent and thus superfluou Both scenarios require a mechanism to save a snapshot of the processor state in a non-volatile memory. This mechanism is commonly known as '''hibe
  3 KB (390 words) - 11:59, 20 June 2016
• Design of State Retentive Flip-Flops
  ...ation to be retained between two calls, it is not acceptable for an entire processor core idling, for example while waiting for a DMA transfer to be completed.
  2 KB (364 words) - 09:34, 25 July 2017
• Standard Cell Compatible Memory Array Design
  ...ocks of any processing system, in fact most of the performance of a modern processor is determined by its ability to efficiently store and retrieve data. For IC
  5 KB (769 words) - 15:54, 23 May 2018
• Intelligent Power Management Unit (iPMU)
  ...PMU should schedule the system tasks in an optimal way and wakeup the main processor if required. Naturally, the iPMU should consume as little power as possible
  2 KB (292 words) - 11:40, 2 June 2021
• Change-based Evaluation of Convolutional Neural Networks
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  5 KB (747 words) - 18:04, 29 August 2016
• Rethinking our Convolutional Network Accelerator Architecture
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  9 KB (1,263 words) - 18:52, 12 December 2016
• Design of a VLIW processor architecture based on RISC-V
  ...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
  3 KB (377 words) - 10:25, 5 November 2019
• Minimal Cost RISC-V core
  ...n are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is enough. A very simple 2-3stag ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
  3 KB (384 words) - 17:24, 21 August 2019
• Turbo Equalization for Cellular IoT
  [[Category:Processor]]
  3 KB (450 words) - 11:43, 13 November 2018
• PULPonFPGA: Hardware L2 Cache
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  5 KB (711 words) - 10:27, 5 November 2019
• NextGenChannelDec
  [[Category:Processor]]
  3 KB (402 words) - 15:31, 13 April 2016
• Next Generation Channel Decoder
  [[Category:Processor]]
  3 KB (418 words) - 14:01, 13 November 2020
• Implementation of a NB-IoT Positioning System
  ...ftware co-design in which part of the algorithm will be mapped onto a PULP processor while computational complex tasks are realized in dedicated hardware accele [[Category:Processor]]
  4 KB (555 words) - 16:36, 23 May 2018
• Design of a Fused Multiply Add Floating Point Unit
  ...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi ...multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.
  2 KB (346 words) - 10:26, 5 November 2019
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  5 KB (712 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  6 KB (866 words) - 13:43, 29 November 2019
• Towards The Integration of E-skin into Prosthetic Devices
  ...sensors and one or two algorithms will be implemented directly in the PULP processor. One of main challenging goal of the project is bring these algorithm in an * programming the PULP processor for the specific application, otimize the code and carry out in-field testi
  4 KB (631 words) - 11:39, 21 July 2017
• Bringing XNOR-nets (ConvNets) to Silicon
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  10 KB (1,357 words) - 16:25, 30 October 2020
• Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
  *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]
  3 KB (351 words) - 16:19, 27 February 2018
• Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...m the ADC HW-FIFO to SW-FIFO at kernel-space and the real-time embedded co-processor ([http://beagleboard.org/pru PRU]) for post-processing of the data-stream. *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet]
  3 KB (394 words) - 16:19, 27 February 2018
• Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]
  3 KB (440 words) - 16:15, 1 September 2017
• PVT Dynamic Adaptation in PULPv3
  ...mic power controller algorithm is then needed to always configure the PULP processor in the most energy efficient point.
  3 KB (348 words) - 15:31, 13 September 2016
• On-chip clock synthesizer design and porting
  ...ps (SoCs) often consist of various independent subsystems (e.g., different processor cores, hardware accelerators, analog IPs, etc), each with its own clocking
  3 KB (389 words) - 11:20, 14 September 2016
• Efficient NB-IoT Uplink Design
  while the DBB processing can be done in a CPU, a Digital Signal Processor (DSP), an Appli- Open-RISC processor. The processor can be used to control the baseband blocks as well as to
  6 KB (900 words) - 16:58, 7 May 2018
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...ystems Laboratory (IIS) we have been working on a Parallel Ultra-Low Power Processor (PULP) System for the past two years. PULP is intended to be used for near-
  9 KB (1,427 words) - 18:36, 5 September 2019
• VLSI Implementation Polar Decoder using High Level Synthesis
  [[Category:Processor]]
  3 KB (392 words) - 14:17, 5 April 2022
• FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  ...ger part of the affected digital baseband processing is mapped to a RISC-V processor, most of the work throughout the project requires embedded C coding, with s [[Category:Processor]]
  3 KB (462 words) - 13:54, 13 November 2020
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
  [[Category:Processor]]
  4 KB (467 words) - 13:38, 10 November 2020
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
  ...-power devices such as the PULP chips we develop at IIS. However, a vector processor shares many similarities with custom-designed HW accelerators that we have [[Category:Processor]]
  6 KB (916 words) - 15:50, 7 December 2018
• A computational memory unit using phase-change memory devices
  [[Category:Processor]]
  4 KB (546 words) - 11:33, 17 April 2020
• Deep Learning for Brain-Computer Interface
  [[Category:Processor]]
  3 KB (372 words) - 20:22, 1 April 2019
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
  ...project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient controller based on principles of HD computing, an [[Category:Processor]]
  3 KB (401 words) - 19:08, 29 January 2021
• Trace Debugger for custom RISC-V Core
  ...it should not have any impact on the maximum achievable clock speed of the processor. Another challenge in designing a trace debugger is the fact that on-chip R * Basic knowledge of computer architecture/processor design as thought in the Energy-Efficient Parallel Computing Systems for Da
  5 KB (729 words) - 11:27, 11 December 2018
• Efficient Search Design for Hyperdimensional Computing
  [[Category:Processor]]
  3 KB (366 words) - 15:39, 10 November 2020
• Smart Virtual Memory Sharing
  architectures, where a powerful host processor is coupled to massively pushing for an architectural model where the host processor and the
  6 KB (865 words) - 12:16, 17 November 2017
• Hyper Meccano: Acceleration of Hyperdimensional Computing
  [[Category:Processor]]
  3 KB (409 words) - 13:58, 9 November 2017
• IoT Turbo Decoder
  ...ea footprint. One way to reduce the area is the sharing of memory with the processor cluster. The final design can either be mapped to an FPGA, or an ASIC.
  3 KB (427 words) - 09:37, 14 September 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  [[Category:Processor]]
  4 KB (460 words) - 21:42, 30 January 2018
• Wireless Communication Systems for the IoT
  ...ront ends, RF-transceiver, digital baseband processing, and an application processor. Such a RF System-on-Chip (RF-SoC) is mandatory to achieve minimal manufact
  3 KB (344 words) - 01:45, 10 February 2021
• Satellite Internet of Things
  [[Category:Processor]]
  3 KB (393 words) - 13:53, 13 November 2020
• Neural Networks Framwork for Embedded Plattforms
  ...n a general purpose microcontroller platform and on our own PULP multicore processor platforms. But as applications and research is changing fast, these impleme
  3 KB (317 words) - 14:40, 14 April 2021
• Heterogeneous SoCs
  HERO combines an ARM Cortex-A host processor with a scalable, configurable, and extensible FPGA implementation of a prog
  3 KB (421 words) - 18:41, 28 October 2020
• Embedded Systems and autonomous UAVs
  ...e-core microcontrollers (i.e. Arm-Cortex-M family) or MultiCore (i.e. PULP Processor designed in IIS)
  5 KB (625 words) - 16:59, 10 November 2020
• Aliasing-Free Wavetable Music Synthesizer
  ...sy reconfigurability of the oscillator with an external microcontroller or processor, while having outputs based on the I2S protocol that directly connect with [[Category:Processor]]
  5 KB (621 words) - 18:09, 9 October 2022
• Modular Frequency-Modulation (FM) Music Synthesizer
  [[Category:Processor]]
  5 KB (549 words) - 12:35, 28 November 2022
• Hyperdimensional Computing
  ==Extremely Resilient HD Processor== ...project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient controller based on principles of HD computing, an
  10 KB (1,341 words) - 10:46, 25 April 2018
• CMOS power amplifier for field measurements in MRI systems
  [[Category:Processor]]
  3 KB (354 words) - 16:06, 6 May 2019
• Real-Time Implementation of Quantum State Identification using an FPGA
  [[Category:Processor]]
  5 KB (599 words) - 09:03, 21 December 2017
• Inductive Charging Circuit for Implantable Devices
  [[Category:Processor]]
  3 KB (329 words) - 11:43, 20 August 2021
• Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
  ...d system architecture will be developed around an Ultra low power parallel processor developed at IIS to show to be ideally suited to interface
  4 KB (518 words) - 11:40, 2 February 2018
• Biomedical Systems on Chip
  ...e exploring deep integration of analog precision circuits with the digital processor of the PULP family, both workforce and expertise converge on the VivoSoC pr
  2 KB (327 words) - 19:55, 22 February 2018
• Real-Time ECG Contractions Classification
  [[Category:Processor]]
  4 KB (597 words) - 19:15, 9 March 2020
• Extend the RI5CY core with priviledge extensions
  [[Category:Processor]]
  4 KB (661 words) - 08:38, 20 January 2021
• Wearables for Sports and Life Enhancement
  [[Category:Processor]]
  3 KB (381 words) - 14:17, 28 January 2023
• Brunn test
  ...sed measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recor
  2 KB (311 words) - 12:02, 5 December 2018
• OTDOA Positioning for LTE Cat-M
  [[Category:Processor]]
  4 KB (566 words) - 15:50, 9 February 2021
• Optimal System Duty Cycling for a Mobile Health Platform
  [[Category:Processor]]
  4 KB (597 words) - 16:57, 12 July 2022
• Design and Implementation of a multi-mode multi-master I2C peripheral
  [[Category:Processor]]
  2 KB (240 words) - 16:57, 12 July 2022
• Enabling Standalone Operation for a Mobile Health Platform
  [[Category:Processor]]
  2 KB (268 words) - 16:57, 12 July 2022
• Embedded Artificial Intelligence:Systems And Applications
  ...e-core microcontrollers (i.e. Arm-Cortex-M family) or MultiCore (i.e. PULP Processor designed in IIS)
  4 KB (609 words) - 13:52, 12 June 2018
• Physics is looking for PULP
  ...spective users can develop their programs, and transfer them to the RISC-V processor, as well as establish connections to basic peripherals. It is planned to ma [[Category:Processor]]
  4 KB (497 words) - 16:50, 21 June 2018
• Design of Scalable Event-driven Neural-Recording Digital Interface
  ...converters (ADCs) and a digital part that streams the signals to a digital processor. This part is usually implemented with standard protocols like SPI or USB. ...text of action potentials, a neural recording system can send to a digital processor only the spikes and do not send anything when the only content of the signa
  8 KB (1,269 words) - 18:40, 5 September 2019
• Human Intranet
  =Extremely Resilient Hyperdimensional Processor= ...project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient controller based on principles of HD computing, an
  17 KB (2,419 words) - 20:09, 10 March 2024
• Elliptic Curve Accelerator for zkSNARKs
  [[Category:Processor]]
  5 KB (614 words) - 15:02, 4 March 2019
• Design of combined Ultrasound and Electromyography systems
  ...mW 8-Channel Advanced Brain–Computer Interface Platform With a Nine-Core Processor and BLE Connectivity
  3 KB (437 words) - 19:03, 6 December 2023
• Multisensory system for performance analysis in ski jumping (M/1-2S/B)
  [[Category:Processor]]
  6 KB (820 words) - 12:13, 23 July 2023
• Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
  [[Category:Processor]]
  5 KB (644 words) - 18:18, 21 July 2023
• NAND Flash Open Research Platform
  [[Category:Processor]]
  4 KB (551 words) - 11:06, 11 July 2019
• Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  [[Category:Processor]]
  4 KB (517 words) - 17:09, 16 September 2021
• NVDLA meets PULP
  * compares against Ara, a vector processor based on the RISC-V Vector extension ...8] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018
  6 KB (799 words) - 13:42, 10 November 2020
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  [[Category:Processor]]
  7 KB (1,030 words) - 19:05, 29 January 2021
• Timing Channel Mitigations for RISC-V Cores
  ...thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical ax ...tigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during
  6 KB (915 words) - 18:16, 20 May 2020
• Developing a small portable neutron detector for detecting smuggled nuclear material
  [[Category:Processor]]
  5 KB (623 words) - 10:32, 5 November 2019
• ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
  [[Category:Processor]]
  6 KB (735 words) - 12:12, 23 July 2023
• Floating-Point Divide & Square Root Unit for Transprecision
  ...Laboratory (IIS) we have been working for several years on ultra-low-power processor cores in the context of the ''PULP'' (Parallel Ultra-Low Power) project. PU In order for FP arithmetic being fast and energy-efficient in a processor core, a dedicated floating-point unit (FPU) in hardware is needed. RISC-V d
  8 KB (1,135 words) - 17:09, 29 July 2020
• FPGA Testbed Implementation for Bluetooth Indoor Positioning
  .... The previously developed digital baseband receiver block integrated in a processor system shall be used as a starting point. As a first step you will identify
  3 KB (431 words) - 21:47, 18 November 2019
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
  [[Category:Processor]]
  4 KB (589 words) - 19:19, 29 January 2021
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
  ...le Modular Redundancy (TMR), to ensure a reliability level. For example, a processor core is replicated an odd number of times, and a voting mechanism is used t ...be used in combination with the [https://www.github.com/lowRISC/ibex Ibex] processor core. Similar to RI5CY, Ibex implements the RV32IMC instruction set archite
  6 KB (980 words) - 14:46, 2 June 2021
• Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
  ...d with low power consumption in mind and leveraging a the energy efficient processor. A whole working demostrator is planned to be achieved by the student. This
  4 KB (519 words) - 15:41, 10 November 2020
• Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
  ...rtfolio that comes from over 20 years of experience in mixed-signal neural processor design, advanced neural routing architectures, and neural algorithms. ...and master projects in the field of neuromorphic intelligence using their processor to build a whole working embedded system. The student will deal with both h
  5 KB (692 words) - 15:45, 10 November 2020
• Manycore System on FPGA (M/S/G)
  ...i, <span>“Snitch: A 10 <span class="nocase">kGE</span> pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloa
  8 KB (1,319 words) - 10:41, 6 July 2021
• Hardware Acceleration
  ...e the backbone of big data and scientific computing. While general-purpose processor architectures such as Intel's x86 provide good performance across a wide va ...and real-world performance as communication and data exchange between the processor and accelerator become major bottlenecks.
  7 KB (917 words) - 17:04, 24 November 2023
• Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
  [[Category:Processor]]
  5 KB (584 words) - 12:09, 29 October 2020
• Event-Driven Convolutional Neural Network Modular Accelerator
  [1] M. Davies et al., "Loihi: A Neuromorphic Manycore Processor with On-Chip Learning," in IEEE Micro, vol. 38, no. 1, pp. 82-99, January/F
  4 KB (651 words) - 19:10, 29 January 2021
• Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
  ...ery effectively, providing better energy efficiency than a general purpose processor for applications that fit its execution model. ...ner, Luca Benini. Ara: A 1GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22nm FD-SOI. [https://doi.or
  4 KB (627 words) - 14:42, 29 October 2020
• Semi-Custom Digital VLSI for Processing-in-Memory
  Recently, we have proposed PPAC (Parallel Processor in Associative Content-Addressable Memory) [1], a PIM architecture that is [[Category:Processor]]
  7 KB (882 words) - 14:33, 28 July 2021
• Mapping Networks on Reconfigurable Binary Engine Accelerator
  ...ile is handled in a single job, helped by HWPE uloop (tiny microcoded loop processor)
  6 KB (814 words) - 09:55, 8 March 2023
• Accurate deep learning inference using computational memory
  [[Category:Processor]]
  5 KB (628 words) - 12:51, 17 April 2020
• ASIC Implementation of Jammer Mitigation
  [[Category:Processor]]
  5 KB (662 words) - 13:31, 10 May 2023
• Real-Time Motor-Imagery Classification Using Neuromorphic Processor
  ...classes motor-imagery and often they are not implemented in a neuromorphic processor, and none of them are presenting a whole system from the data acquisition t
  6 KB (815 words) - 20:02, 10 March 2024
• High Performance SoCs
  ...hms and kernels and hardware that can be efficiently programmed for use in processor-based systems.
  11 KB (1,337 words) - 10:54, 25 January 2024
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  Heterogeneous systems combine a general-purpose host processor with domain-specific Programmable Many-Core Accelerators (PMCAs). Such systems are highly versatile, due to their host processor capabilities, while having high performance and energy efficiency through t
  5 KB (737 words) - 17:26, 2 November 2020
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
  ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  11 KB (1,675 words) - 15:40, 15 March 2021
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
  ...us Systems on Chip (HESoCs) often couple a high-performance versatile host processor, capable of handling fully-fledged operating systems running standard softw ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  11 KB (1,617 words) - 23:59, 6 February 2021
• Peak-to-average power Reduction
  [[Category:Processor]]
  4 KB (513 words) - 14:16, 24 November 2021
• DaCe on Snitch (M/1-3S)
  ...ways of leveraging the DaCe framework to generate code for ETH’s Snitch processor system.
  2 KB (333 words) - 20:05, 15 February 2021
• VLSI Implementation of a 5G Ciphering Accelerator
  [[Category:Processor]]
  3 KB (404 words) - 10:05, 9 February 2021
• Multi issue OoO Ariane Backend (M)
  ...g frequency in a modern 12nm process with IPCs expected from that class of processor [6].
  3 KB (474 words) - 15:50, 17 November 2021
• Nils Wistoff
  * Processor Design
  578 bytes (56 words) - 18:59, 30 October 2020
• Event-Driven Vision on an embedded platform
  ...mera by FBK will be deployed and characterized in conjunction with a GAP 8 processor to enable energy-proportional image recognition on embedded platforms. Depe
  3 KB (449 words) - 08:41, 17 February 2021
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
  IBM recently contributed their A2O processor core to the open-source community. The A2O is a 2-way multithreaded out-of- ...nm technology node. It was created as an application-grade, Linux-capable processor to be integrated in large SoCs primarily targeting applications like artifi
  3 KB (405 words) - 15:19, 9 July 2021
• Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
  ...points (AP) distributed over a large area, communicating via a centralized processor. Having access to the extreme amount of measurements at the distributed APs [[Category:Processor]]
  8 KB (931 words) - 17:27, 23 November 2021
• MemPool on HERO (1S)
  ...Accelerators (PMCAs). Such systems are highly versatile due to their host processor capabilities while having high performance and energy efficiency through th ...ores [3]. It is a 32-bit in-order RISC-V instruction set architecture(ISA) processor with four pipeline stages, extended with signal processing instructions. PU
  6 KB (902 words) - 19:07, 20 January 2021
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
  ...e higher-level tasks (like DRAM refresh) in firmware on a dedicated RISC-V processor  &#91;[[#ref-snitch|5]]] . ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  8 KB (1,214 words) - 15:18, 9 July 2021
• ISA extensions in the Snitch Processor for Signal Processing (M)
  ...nally, it can support he ‘M’ and ‘F’ extension through a custom co-processor interface. However, currently, there is no support for domain-specific inst ...the OpenHW Group [<nowiki/>[[#ref-CV32E40P|7]]]. It is a 32-bit in-order processor with 4 pipeline stages. In contrast to Snitch, it features custom DSP instr
  9 KB (1,311 words) - 00:08, 13 March 2021
• Cell-Free mmWave Massive MIMO Communication
  [[Category:Processor]]
  7 KB (882 words) - 21:34, 13 July 2022
• Practical Reconfigurable Intelligent Surfaces (RIS)
  [[Category:Processor]]
  8 KB (1,011 words) - 12:25, 16 November 2023
• Quest for the smallest Turing-complete core (2-3G)
  ...complex enough and frankly just boring whereas fully-developed IPs, like a processor core, consists of tens to hundreds of thousands gates. Even our smallest co
  2 KB (248 words) - 20:02, 15 February 2021
• Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
  [[Category:Processor]]
  5 KB (653 words) - 11:08, 12 November 2020
• Low-Resolution 5G Beamforming Codebook Design
  [[Category:Processor]]
  6 KB (829 words) - 11:37, 12 November 2020
• Deep Unfolding of Iterative Optimization Algorithms
  [[Category:Processor]]
  6 KB (748 words) - 13:57, 12 November 2020
• ASIC Development of 5G-NR LDPC Decoder
  [[Category:Processor]]
  3 KB (389 words) - 01:43, 10 February 2021
• Evaluating memory access pattern specializations in OoO, server-grade cores (M)
  ...earch [1], we explored the opportunity of adding streaming semantic to the processor memory architecture. This was done in in-order ...imulator [3], on top of an existing model of an ARM server-grade multicore processor. The project will be comentored by researchers from Huawei's Zurich Researc
  7 KB (1,003 words) - 13:25, 10 August 2021
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  .... Benini, <span>“<span class="nocase">Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  11 KB (1,602 words) - 15:19, 9 July 2021
• Efficient Synchronization of Manycore Systems (M/1S)
  .... Benini, <span>“<span class="nocase">Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  12 KB (1,864 words) - 12:08, 29 August 2022
• RVfplib
  ...are, exploiting a dedicated Floating-Point Unit (FPU). This means that the processor uses a circuit that was specifically designed to compute FP operations. Thi ...FP operation with a specific function that uses only integer numbers. The processor executes this function on the FP input numbers, and, after many integer ins
  4 KB (536 words) - 13:25, 12 August 2022
• Transforming MemPool into a CGRA (M)
  ...i, <span>“Snitch: A 10 <span class="nocase">kGE</span> pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloa
  13 KB (1,887 words) - 15:51, 17 November 2021
• Physical Implementation of Ara, PULP's Vector Machine (1-2S)
  ...ery effectively, providing better energy efficiency than a general-purpose processor for applications that fit its execution model (e.g., machine learning, and ...ner, Luca Benini. Ara: A 1GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22nm FD-SOI. [https://doi.or
  6 KB (916 words) - 15:25, 9 July 2021
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  8 KB (1,220 words) - 15:18, 9 July 2021
• Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
  A interesting field suitable to both domains is ''processor design'': the rising popularity and widespread adoption of the open RISC-V ...uiki, T. Hoefler, and L. Benini, <span>“Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloa
  10 KB (1,521 words) - 15:21, 9 July 2021
• LLVM and DaCe for Snitch (1-2S)
  ...uiki, T. Hoefler, and L. Benini, <span>“Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloa
  11 KB (1,519 words) - 15:20, 9 July 2021
• Huawei Research
  ...a vector processor for full compliance of the RVV 1.0 Vector standard || Processor Design || digital VLSI design || [[:User:Mperotti | Matteo Perotti]] (ETH),
  6 KB (799 words) - 11:11, 1 August 2022
• Ibex: Tightly-Coupled Accelerators and ISA Extensions
  ...e to implement custom co-processors and ISA extensions for existing RISC-V processor cores. Just like Ibex [1], the work for this extension interface has been s ...ng unit (VPU), or the development of a new accelerator such as a string co-processor. The project can be done in the context of a single-core or multi-core syst
  6 KB (835 words) - 12:52, 27 April 2021
• Ultrasound Low power WiFi with IMX7
  The goal of the mini-project is to explore a processor i.MX 7ULP from NXP) for low-power ultrasound data streaming through WiFi.
  2 KB (240 words) - 16:56, 16 September 2022
• Fast Simulation of Manycore Systems (1S)
  ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  10 KB (1,434 words) - 17:20, 2 August 2021
• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  We can take inspiration on Ara, a RISC-V-based vector processor developed by our group. ...F. Schuiki, T. Hoefler, and L. Benini, "Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  11 KB (1,609 words) - 10:00, 30 June 2022
• EEG artifact detection for epilepsy monitoring
  ...and the BioWolf wearable ExG device, which has the PULP Mr. Wolf multicore processor on board. The project’s goal is to design a system capable of detecting v
  2 KB (313 words) - 15:25, 23 October 2023
• Novel Methods for Jammer Mitigation
  [[Category:Processor]]
  6 KB (687 words) - 13:32, 10 May 2023
• Probing the limits of fake-quantised neural networks
  [[Category:Processor]]
  5 KB (659 words) - 14:08, 15 February 2024
• VLSI Design of an Asynchronous LDPC Decoder
  ...ynchronous VLSI designs; right: automatically-generated layout of a simple processor implemented using ACT and fabricated in 65nm CMOS. ]] [[Category:Processor]]
  6 KB (725 words) - 17:36, 20 October 2021
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  * Our vector processor Ara [5]
  3 KB (431 words) - 16:13, 6 November 2022
• XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
  Recently, we have proposed PPAC (Parallel Processor in Associative Content-Addressable Memory) [1], a PIM architecture that is [[Category:Processor]]
  7 KB (933 words) - 19:29, 21 November 2021
• Robert Balas
  * Processor Design
  931 bytes (108 words) - 10:30, 22 November 2021
• Integrating Hardware Accelerators into Snitch (1S)
  ...ps://ieeexplore.ieee.org/document/9216552 Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  4 KB (567 words) - 13:57, 7 September 2022
• Non-blocking Algorithms in Real-Time Operating Systems
  ...e hardware-level, you can make sure that they can quickly propagate to the processor by moving parts that are slow such as the handshaking into hardware and pro
  4 KB (508 words) - 18:59, 10 January 2022
• Implementing DSP Instructions in Banshee (1S)
  .... Benini, <span>“<span class="nocase">Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa ...ne">S. Mazzola, <span>“<span class="nocase">ISA extensions in the Snitch Processor for Signal Processing</span>,”</span> Apr. 2021.</span>
  10 KB (1,428 words) - 13:31, 27 October 2022
• Streaming Integer Extensions for Snitch (M/1-2S)
  ...ps://ieeexplore.ieee.org/document/9216552 Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa ...he_Snitch_Processor_for_Signal_Processing_(M) ISA extensions in the Snitch Processor for Signal Processing (M)] (Previous Master thesis project)
  6 KB (770 words) - 14:19, 15 September 2022
• Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
  PPAC (Parallel Processor in Associative Content-Addressable Memory) [1] is a hardware accelerator th ...benchmarking, the student will also integrate PPAC together with a RISC-V processor.
  7 KB (804 words) - 19:45, 21 November 2021
• SCMI Support for Power Controller Subsystem
  In ARM based SoCs the PCS (System Control Processor, SCP) interacts with the OS via the System Control and Management Interface
  3 KB (467 words) - 13:55, 12 October 2022
• Low Resolution Neural Networks
  [[Category:Processor]]
  4 KB (520 words) - 14:52, 24 November 2021
• Serverless Benchmarks on RISC-V (M)
  ...to compare the performance of a broad set of functions running on various processor architectures (e.g. Intel/AMD x86, ARMv8, RISC-V) in order to gain insight ...Ideally, we would also run the same set of benchmarks on an Intel/AMD x86 processor (possibly via Cloudlab), and an ARMv8 such as the ThunderX1 found in Enzian
  6 KB (905 words) - 21:41, 6 December 2021
• Watchdog Timer for PULP
  Goal of this project is to implement a Watchdog Timer (WDT) for a PULP processor core. While a preliminary specification from RISC-V is available, a few add
  2 KB (337 words) - 08:49, 21 June 2022
• Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
  ...and require an immensely large circuit area. Ara [1], our in-house vector Processor (RISC-V Vector Extension Version 0.10) e.g. has a complexity of multiple MG
  3 KB (384 words) - 12:13, 21 June 2022
• Wireless EEG Acquisition and Processing
  ...and the BioWolf wearable ExG device, which has the PULP Mr. Wolf multicore processor on board. The project’s goal is to design a system capable of acquiring r ...mW 8-Channel Advanced Brain–Computer Interface Platform With a Nine-Core Processor and BLE Connectivity
  3 KB (369 words) - 15:04, 20 July 2023
• PULP’s CLIC extensions for fast interrupt handling
  ...ng HW has to guarantee fast propagation of the interrupt lines towards the processor, with a per-interrupt, fine-grained control over each line, and support int
  4 KB (515 words) - 15:06, 5 August 2022
• Fast Accelerator Context Switch for PULP
  ...ically adjusting the operating point of a High Performance Computing (HPC) processor to meet energy, power, and thermal constraints. [3] https://www.european-processor-initiative.eu/
  6 KB (835 words) - 16:27, 7 July 2023
• Development of a fingertip blood pressure sensor
  [[Category:Processor]]
  4 KB (535 words) - 16:56, 12 July 2022
• Triple-Core PULPissimo
  ...gate level to ensure reliability, other schemes replicate entire blocks or processor cores, or only add Error Correcting Codes (ECC) to data stored in memory.
  2 KB (311 words) - 08:49, 21 June 2022
• New RVV 1.0 Vector Instructions for Ara
  ...“FUGAKU”, the most performant supercomputer in the world, is a vector processor! What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a pro
  4 KB (580 words) - 11:37, 3 November 2023
• Passive Radar for UAV Detection using Machine Learning
  [[Category:Processor]]
  5 KB (564 words) - 16:12, 9 February 2022
• Through Wall Radar Imaging using Machine Learning
  [[Category:Processor]]
  5 KB (586 words) - 16:15, 9 February 2022
• Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
  ...yflie featuring both a UWB module as well as an ultra low-power multi-core processor, GAP8. Your task will include porting the driver for the array ToF sensor t
  3 KB (507 words) - 15:09, 11 February 2022
• Bridging QuantLab with LPDNN
  [[Category:Processor]]
  7 KB (831 words) - 19:36, 12 January 2023
• Exploring NAS spaces with C-BRED
  [[Category:Processor]]
  6 KB (839 words) - 14:08, 15 February 2024
• Development of statistics and contention monitoring unit for PULP
  The unit should take advantage of the existing PMCs in the processor, introduce new ones if needed and implement the necessary logic to monitor
  6 KB (869 words) - 14:47, 7 July 2023
• Low-Complexity MIMO Detection
  [[Category:Processor]]
  4 KB (503 words) - 13:54, 30 May 2022
• Forward error-correction ASIC using GRAND
  [[Category:Processor]]
  4 KB (470 words) - 18:16, 27 May 2022
• Low-power time synchronization for IoT applications
  [[Category:Processor]]
  4 KB (492 words) - 10:55, 16 June 2022
• Weak-strong massive MIMO communication with low-resolution ADCs
  [[Category:Processor]]
  5 KB (662 words) - 13:33, 10 May 2023
• Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
  [[Category:Processor]]
  5 KB (586 words) - 15:34, 11 July 2022
• Event-based navigation on autonomous nano-drones
  ...unity to design a new DL-based algorithm to run on a novel ultra-low-power processor, such as the PULP Kraken [3,4] System-on-Chip (SoC). At the same time, the
  4 KB (505 words) - 18:25, 26 July 2022
• Implementing Configurable Dual-Core Redundancy
  ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  4 KB (497 words) - 14:15, 29 June 2023
• Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
  ...a energy-efficient general-purpose vector processor, and extend the vector processor to cope with the new challenges to run efficiently transformer models. ...ent has already experience in programming and developing on the Ara vector processor from his previous semester thesis.
  4 KB (549 words) - 11:35, 3 November 2023
• Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
  ...quence of elements from a high-bandwidth scratchpad memory directly into a processor register as it is being used by an instruction, enabling very high FPU util
  3 KB (431 words) - 22:29, 19 January 2023
• Alias-Free Oscillator Synchronization for Arbitrary Waveforms
  [[Category:Processor]]
  5 KB (577 words) - 09:48, 5 October 2022
• Extended Verification for Ara
  ...“FUGAKU”, the most performant supercomputer in the world, is a vector processor! What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a pro
  5 KB (665 words) - 14:19, 18 October 2022
• Virtual Memory Ara
  ...“FUGAKU”, the most performant supercomputer in the world, is a vector processor! What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a pro
  5 KB (769 words) - 11:38, 3 November 2023
• Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
  [5] [https://arxiv.org/pdf/2002.10143.pdf Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  7 KB (944 words) - 10:47, 25 January 2024
• GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
  ...ing the design before it can be delivered for tapeout. For general purpose processor designs, verifying the functionality involves running some code on the core If your processor has a debugging interface (exposed e.g. over JTAG) and can be implemented o
  8 KB (1,186 words) - 11:49, 13 March 2024
• Big Data Analytics Benchmarks for Ara
  ...cores. ETH is at the forefront of this race with its agile in-order vector processor Ara, fresh from an update from the unripe specifications RVV 0.5. ...enchmarks based on open-source vector ISA RVV 0.5, evaluate them on vector processor Ara, and try to achieve their best performance.
  3 KB (470 words) - 11:34, 3 November 2023
• Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
  ...So far our DMA engine works on physical memory only, requiring either the processor to do the PM/VM translation or relying on an external IOMMU (IO Memory Mana
  2 KB (249 words) - 09:36, 3 November 2023
• Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
  ...IoT processor which features a 32-bit RISC-V ISA. The resulting resilient processor and design will be compared again state-of-the-art to assess benefits, impr
  5 KB (752 words) - 13:23, 24 October 2023
• Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
  <!-- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) --> The aim of this project is to design a reconfigurable vector processor cluster for area-optimized, yet compute and energy-efficient, radar signal
  5 KB (651 words) - 20:42, 22 November 2022
• Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
  This project aims to extend the I/O peripherals of a Linux-capable RISC-V SoC processor with a novel designed CAN interface. This project aims to extend the I/O peripherals of a Linux-capable RISC-V SoC processor with a novel designed CAN interface.
  4 KB (554 words) - 09:28, 3 November 2023
• Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
  ...ble-precision DivSqrt unit included in the open-source T-head OpenC910 [3] processor and integrate it into CVFPU.
  2 KB (307 words) - 15:40, 15 February 2024
• Artificial Reverberation for Embedded Systems
  [[Category:Processor]]
  5 KB (578 words) - 12:39, 14 June 2023
• A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
  [[Category:Processor]]
  6 KB (720 words) - 16:27, 27 September 2023
• Wireless In Action Data Streaming in Ski Jumping (1 B/S)
  [[Category:Processor]]
  6 KB (688 words) - 12:15, 23 July 2023
• Cycle-Accurate Event-Based Simulation of Snitch Core
  * [2] Zaruba, Florian, et al. "Snitch: A tiny pseudo-dual-issue processor for area and energy efficient execution of floating-point intensive workloa [[Category:Processor]]
  14 KB (2,018 words) - 22:54, 23 November 2023
• Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
  [[Category:Processor]]
  6 KB (735 words) - 12:15, 23 July 2023
• Skin coupling media characterization for fitnesstracker applications (1 B/S)
  [[Category:Processor]]
  5 KB (631 words) - 12:43, 23 July 2023
• Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
  [[Category:Processor]]
  7 KB (903 words) - 10:04, 24 July 2023
• Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
  [[Category:Processor]]
  5 KB (631 words) - 10:07, 24 July 2023
• A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
  ...Carlo applications on Snitch, a pseudo dual-issue energy-efficient RISC-V processor for floating-point computations [1, 2]. Snitch features an integer core and ...ations on Snitch. Unfortunately, pseudo dual-issue execution in the Snitch processor is only possible when the integer and floating-point threads are independen
  7 KB (962 words) - 12:53, 7 March 2024
• Transformer Deployment on Heterogeneous Many-Core Systems
  MemPool is an image signal processor (ISP) designed at ETH. Originally, it boasts 256 lightweight 32-bit Snitch
  6 KB (858 words) - 14:52, 23 October 2023
• Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
  ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  3 KB (374 words) - 10:24, 3 November 2023
• Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
  ...ps://ieeexplore.ieee.org/document/9216552 Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  6 KB (850 words) - 15:51, 17 October 2023
• Learning at the Edge with Hardware-Aware Algorithms
  ...the kernels of PULP-TrainLib~[[#ref-pulptrainlib|&#91;4&#93;]] on the edge processor GAP9 for different input sizes such that you will be able to estimate the e
  7 KB (942 words) - 13:59, 15 February 2024
• An Ultra-Low-Power Neuromorphic Spiking Neuron Design
  ...Kim and H. -J. Yoo, "Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital–Analog Networks," in IEEE Jour
  2 KB (279 words) - 17:01, 4 March 2024
• Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
  ...do not need to execute very quickly. Therefore, existing hardware within a processor can be leveraged for reliability. In this project, the goal is to modify a simple embedded RISC-V processor, such as Ibex [1]. The Ibex core supports both the riscv32i and the riscv32
  2 KB (259 words) - 11:55, 18 December 2023
• NeuroSoC RISC-V Component (M/1-2S)
  [2] [https://arxiv.org/abs/2002.10143 Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa
  3 KB (482 words) - 17:26, 10 January 2024
• EEG earbud
  ...ossettini and L. Benini, "BioGAP: a 10-Core FP-capable Ultra-Low Power IoT Processor, with Medical-Grade AFE and BLE Connectivity for Wearable Biosignal Process
  3 KB (401 words) - 19:01, 6 December 2023
• In-ear EEG signal acquisition
  ...ossettini and L. Benini, "BioGAP: a 10-Core FP-capable Ultra-Low Power IoT Processor, with Medical-Grade AFE and BLE Connectivity for Wearable Biosignal Process
  4 KB (461 words) - 19:01, 6 December 2023
• EEG-based drowsiness detection
  ...ossettini and L. Benini, "BioGAP: a 10-Core FP-capable Ultra-Low Power IoT Processor, with Medical-Grade AFE and BLE Connectivity for Wearable Biosignal Process
  3 KB (375 words) - 19:03, 6 December 2023
• Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
  [2] Ariane, RISC-V application processor: https://ieeexplore.ieee.org/abstract/document/8777130
  5 KB (775 words) - 17:17, 18 December 2023
• Low Precision Ara for ML
  ...“FUGAKU”, the most performant supercomputer in the world, is a vector processor! What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a pro
  4 KB (524 words) - 12:36, 29 January 2024
• Writing a Hero runtime for EPAC (1-3S/B)
  EPAC is one of the chip resulting from the European Processor Initiative (EPI) consortium, in which ETH Zurich is involved. The EPAC and ''Source: [https://www.european-processor-initiative.eu/accelerator/]''
  4 KB (501 words) - 15:27, 15 February 2024
• A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
  ...ovement, by featuring a comparably large register file. On an out-of-order processor we could execute the original version of the program and still expect the p ...Snitch core developed in our group. Snitch is a pseudo dual-issue in-order processor, targeting energy-efficient floating-point computations. Snitch-based accel
  7 KB (1,153 words) - 18:58, 21 April 2024
• Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
  ...es (each containing 5 RISC-V processors, a tensor accelerator, a vector co-processor and up to 1.5MB of SRAM). The Grayskull card comes with two open source SDK
  3 KB (459 words) - 13:24, 12 April 2024

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