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Showing below up to 250 results in range #251 to #500.
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- Michael Rogenmoser (9 revisions)
- DC-DC Buck converter in 65nm CMOS (9 revisions)
- Energy Efficient SoCs (9 revisions)
- Configurable Ultra Low Power LDO (9 revisions)
- Gomeza old project2 (9 revisions)
- Time and Frequency Synchronization in LTE Cat-0 Devices (9 revisions)
- Minimal Cost RISC-V core (9 revisions)
- A Multiview Synthesis Core in 65 nm CMOS (9 revisions)
- Improved State Estimation on PULP-based Nano-UAVs (9 revisions)
- Freedom from Interference in Heterogeneous COTS SoCs (9 revisions)
- Next Generation Synchronization Signals (9 revisions)
- Hardware Accelerated Derivative Pricing (9 revisions)
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging (9 revisions)
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication (9 revisions)
- Gomeza old project4 (9 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- Weekly Reports (8 revisions)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (8 revisions)
- Pirmin Vogel (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- A Unified Compute Kernel Library for Snitch (1-2S) (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (8 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (8 revisions)
- Learning at the Edge with Hardware-Aware Algorithms (8 revisions)
- Evaluating SoA Post-Training Quantization Algorithms (8 revisions)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications (8 revisions)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs (8 revisions)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 revisions)
- (M/1-2S): A Snitch-based Compute Accelerator for HERO (8 revisions - redirect page)
- Multi issue OoO Ariane Backend (M) (8 revisions)
- PREM Runtime Scheduling Policies (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- An FPGA-Based Evaluation Platform for Mobile Communications (8 revisions)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (8 revisions)
- Flexible Electronic Systems and Epidermal Devices (8 revisions - redirect page)
- Manycore System on FPGA (M/S/G) (8 revisions)
- Streaming Layer Normalization in ITA (M/1-2S) (8 revisions)
- Implementing Hibernation on the ARM Cortex M0 (8 revisions)
- Wireless EEG Acquisition and Processing (8 revisions)
- Evaluating the RiscV Architecture (8 revisions)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (8 revisions)
- SCMI Support for Power Controller Subsystem (8 revisions)
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC (8 revisions)
- BCI-controlled Drone (8 revisions)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) (8 revisions)
- Modular Distributed Data Collection Platform (8 revisions)
- Fast Wakeup From Deep Sleep State (8 revisions)
- Physical Implementation of ITA (2S) (8 revisions)
- Hypervisor Extension for Ariane (M) (8 revisions)
- Development of a fingertip blood pressure sensor (8 revisions)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (8 revisions)
- Linux Driver for fine-grain and low overhead access to on-chip performance counters (8 revisions)
- Deep Convolutional Autoencoder for iEEG Signals (8 revisions)
- OTDOA Positioning for LTE Cat-M (8 revisions)
- Hardware/software co-programming on the Parallella platform (8 revisions)
- Resource Partitioning of RPC DRAM (8 revisions)
- Fault-Tolerant Floating-Point Units (M) (8 revisions)
- ASIC Implementation of Jammer Mitigation (8 revisions)
- Object Detection and Tracking on the Edge (8 revisions)
- NVDLA meets PULP (8 revisions)
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format (8 revisions)
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications (8 revisions)
- A Trustworthy Three-Factor Authentication System (8 revisions)
- Sandro Belfanti (8 revisions)
- Ultra Low-Power Oscillator (8 revisions)
- A computational memory unit using phase-change memory devices (8 revisions)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 revisions)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- EEG earbud (7 revisions)
- Development of statistics and contention monitoring unit for PULP (7 revisions)
- Predictable Execution (7 revisions)
- Satellite Internet of Things (7 revisions)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S) (7 revisions)
- Gomeza old project5 (7 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (7 revisions)
- Charging System for Implantable Electronics (7 revisions)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (7 revisions)
- Outdoor Precision Object Tracking for Rockfall Experiments (7 revisions)
- Mauro Salomon (7 revisions)
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients (7 revisions)
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT (7 revisions)
- FFT HDL Code Generator for Multi-Antenna mmWave Communication (7 revisions)
- Spiking Neural Network for Autonomous Navigation (7 revisions)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (7 revisions)
- Bateryless Heart Rate Monitoring (7 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (1M) (7 revisions)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (7 revisions)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (7 revisions)
- Make Cellular Internet of Things Receivers Smart (7 revisions)
- Compressed Sensing for Wireless Biosignal Monitoring (7 revisions)
- Streaming Integer Extensions for Snitch (M/1-2S) (7 revisions)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (7 revisions)
- RazorEDGE: An Evolved EDGE DBB ASIC (7 revisions)
- Battery indifferent wearable Ultrasound (7 revisions)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (7 revisions)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (7 revisions)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities (7 revisions)
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (7 revisions)
- Ibex: FPGA Optimizations (7 revisions)
- Digital Audio Interface for Smart Intensive Computing Triggering (7 revisions)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (7 revisions)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (7 revisions)
- Development of a Rockfall Sensor Node (7 revisions)
- Indoor Positioning with Bluetooth (7 revisions)
- Efficient NB-IoT Uplink Design (7 revisions)
- Ultra-low power processor design (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (7 revisions)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (7 revisions)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (7 revisions)
- Efficient Search Design for Hyperdimensional Computing (7 revisions)
- LTE IoT Network Synchronization (7 revisions)
- Ultrasound Low power WiFi with IMX7 (7 revisions)
- EEG artifact detection for epilepsy monitoring (7 revisions)
- IoT Turbo Decoder (7 revisions)
- SW/HW Predictability and Security (7 revisions)
- Fault Tolerance (7 revisions)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (7 revisions)
- Characterization techniques for silicon photonics-Lumiphase (7 revisions)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver (7 revisions)
- Zephyr RTOS on PULP (7 revisions)
- RVfplib (7 revisions)
- Internet of Things Network Synchronizer (7 revisions)
- Transforming MemPool into a CGRA (M) (7 revisions)
- Development of an implantable Force sensor for orthopedic applications (7 revisions)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (7 revisions)
- Putting Together What Fits Together - GrÆStl (7 revisions)
- Autonomous Sensing For Trains In The IoT Era (7 revisions)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (7 revisions)
- Android Software Design (6 revisions)
- FPGA mapping of RPC DRAM (6 revisions)
- Moritz Schneider (6 revisions)
- Design of a Low Power Smart Sensing Multi-modal Vision Platform (6 revisions)
- Learning Image Decompression with Convolutional Networks (6 revisions)
- System Emulation for AR and VR devices (6 revisions)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (6 revisions)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) (6 revisions)
- Graph neural networks for epileptic seizure detection (6 revisions)
- Enabling Efficient Systolic Execution on MemPool (M) (6 revisions)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S) (6 revisions)
- LightProbe - Ultracompact Power Supply PCB (6 revisions)
- Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening (6 revisions)
- Channel Estimation for 3GPP TD-SCDMA (6 revisions)
- Implementing Configurable Dual-Core Redundancy (6 revisions)
- Autonomous Smart Watches: Hardware and Software Desing (6 revisions)
- Creating a HDMI Video Interface for PULP (6 revisions)
- New RVV 1.0 Vector Instructions for Ara (6 revisions)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (6 revisions)
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets (6 revisions)
- MemPool on HERO (1S) (6 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache (6 revisions)
- Implementing DSP Instructions in Banshee (1S) (6 revisions)
- CMOS power amplifier for field measurements in MRI systems (6 revisions)
- Ultra-Efficient Visual Classification on Movidius Myriad2 (6 revisions)
- Low-power Temperature-insensitive Timer (6 revisions)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (6 revisions)
- Switched Capacitor Based Bandgap-Reference (6 revisions)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (6 revisions)
- Bluetooth Low Energy receiver in 65nm CMOS (6 revisions)
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing (6 revisions)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich) (6 revisions)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA (6 revisions)
- Novel Metastability Mitigation Technique (6 revisions)
- Improved Collision Avoidance for Nano-drones (6 revisions)
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things (6 revisions)
- Floating-Point Divide & Square Root Unit for Transprecision (6 revisions)
- A Recurrent Neural Network Speech Recognition Chip (6 revisions)
- Beat Cadence (6 revisions)
- Exploring Algorithms for Early Seizure Detection (6 revisions)
- Compression of iEEG Data (6 revisions)
- Novel Methods for Jammer Mitigation (6 revisions)
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA (6 revisions)
- VLSI Design of an Asynchronous LDPC Decoder (6 revisions)
- FPGA Optimizations of Dense Binary Hyperdimensional Computing (6 revisions)
- Exploring NAS spaces with C-BRED (6 revisions)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (6 revisions)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M) (6 revisions)
- Writing a Hero runtime for EPAC (1-3S/B) (6 revisions)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (6 revisions)
- Next Generation Channel Decoder (6 revisions)
- Efficient Synchronization of Manycore Systems (M/1S) (6 revisions)
- Self Aware Epilepsy Monitoring (6 revisions)
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors (6 revisions)
- Towards Self Sustainable UAVs (6 revisions)
- VLSI Implementation of a 5G Ciphering Accelerator (6 revisions)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) (6 revisions)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (6 revisions)
- IBM Research–Zurich (6 revisions)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) (6 revisions)
- Change-based Evaluation of Convolutional Neural Networks (6 revisions)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (6 revisions)
- Ultrasound image data recycler (6 revisions)
- Internet of Things SoC Characterization (5 revisions)
- Noise Figure Measurement for Cryogenic System (5 revisions)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography (5 revisions)
- Toward Superposition of Brain-Computer Interface Models (5 revisions)
- Ultra Low Power Conversion Circuit For Batteryless Applications (5 revisions)
- Embedded Systems and autonomous UAVs (5 revisions)
- LightProbe - Thermal-Power aware on-head Beamforming (5 revisions)
- Data Augmentation Techniques in Biosignal Classification (5 revisions)
- IP-Based SoC Generation and Configuration (1-3S/B) (5 revisions)
- Predictable Execution on GPU Caches (5 revisions)
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration (5 revisions)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (5 revisions)
- Ultra Low Power Wake Up Radio for Wireless Sensor Network (5 revisions)
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor (5 revisions)
- Hardware Accelerator for Model Predictive Controller (5 revisions)
- Ultrasound signal processing acceleration with CUDA (5 revisions)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing (5 revisions)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf (5 revisions)
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring (5 revisions)
- Engineering For Kids (5 revisions)
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device (5 revisions)
- Towards Autonomous Navigation for Nano-Blimps (5 revisions)
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA) (5 revisions)
- TCNs vs. LSTMs for Embedded Platforms (5 revisions)
- ASIC Design Projects (5 revisions)
- A Wearable System To Control Phone And Electronic Device Without Hands (5 revisions)
- Low-power Clock Generation Solutions for 65nm Technology (5 revisions)
- Federico Villani (5 revisions)
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path (5 revisions)
- Ultrafast Medical Ultrasound imaging on a GPU (5 revisions)
- Phase-change memory devices for emerging computing paradigms (5 revisions)
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) (5 revisions)
- Design and Implementation of ultra low power vision system (5 revisions)
- Universal Stream Semantic Registers for Snitch (1S) (5 revisions - redirect page)
- Fast Simulation of Manycore Systems (1S) (5 revisions)
- Snitch meets iCE40 (1-2S/B) (5 revisions - redirect page)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich) (5 revisions)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea (5 revisions)
- Compression of Ultrasound data on FPGA (5 revisions)
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET (5 revisions)
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap (5 revisions)
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC (5 revisions)
- Final Presentation (5 revisions)
- Artificial Reverberation for Embedded Systems (5 revisions)
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers (5 revisions)
- Implementation of a NB-IoT Positioning System (5 revisions)
- LLVM and DaCe for Snitch (1-2S) (5 revisions)
- Channel Shortening Prefilter (5 revisions - redirect page)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S) (5 revisions)
- Adding Linux Support to our DMA Engine (1-2S/B) (5 revisions)
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces (5 revisions)
- Resource Partitioning of Caches (5 revisions)
- State-Saving @ NXP (5 revisions)
- Indoor Smart Tracking of Hospital instrumentation (5 revisions)
- Beat DigRF (5 revisions)
