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Showing below up to 304 results in range #601 to #904.
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- NVDLA meets PULP
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Near-Memory Training of Neural Networks
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- Network-off-Chip (M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Neural Processing
- Neural Recording Interface and Signal Processing
- Neural Recording Interface and Spike Sorting Algorithm
- NeuroSoC RISC-V Component (M/1-2S)
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- New RVV 1.0 Vector Instructions for Ara
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
- NextGenChannelDec
- Next Generation Channel Decoder
- Next Generation Synchronization Signals
- Nils Wistoff
- Noise Figure Measurement for Cryogenic System
- Non-binary LDPC Decoder for Deep-Space Optical Communications
- Non-blocking Algorithms in Real-Time Operating Systems
- Norbert Felber
- Novel Metastability Mitigation Technique
- Novel Methods for Jammer Mitigation
- OTDOA Positioning for LTE Cat-M
- Object Detection and Tracking on the Edge
- On-Board Software for PULP on a Satellite
- On-Device Federated Continual Learning on Nano-Drone Swarms
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
- On-chip clock synthesizer design and porting
- On - Device Continual Learning for Seizure Detection on GAP9
- Online Learning of User Features (1S)
- OpenRISC SoC for Sensor Applications
- Open Power-On Chip Controller Study and Integration
- Open Source Baseband Firmware for 2G Cellular Networks
- Optimal System Duty Cycling
- Optimal System Duty Cycling for a Mobile Health Platform
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- Outdoor Precision Object Tracking for Rockfall Experiments
- PREM Intervals and Loop Tiling
- PREM Runtime Scheduling Policies
- PREM on PULP
- PULP
- PULP-Shield for Autonomous UAV
- PULP Freertos with LLVM
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULPonFPGA: Hardware L2 Cache
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
- PULP’s CLIC extensions for fast interrupt handling
- PVT Dynamic Adaptation in PULPv3
- Palm size chip NMR
- Pascal Hager
- Passive Radar for UAV Detection using Machine Learning
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- Peak-to-average power Reduction
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Phase-change memory devices for emerging computing paradigms
- Philipp Schönle
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of ITA (2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
- Physics is looking for PULP
- Pirmin Vogel
- Positioning for the cellular Internet of Things
- Positioning with Wireless Signals
- Power Optimization in Multipliers
- Power Saver Mode for Cellular Internet of Things Receivers
- Practical Reconfigurable Intelligent Surfaces (RIS)
- Prasadar
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
- Precise Ultra-low-power Timer
- Predict eye movement through brain activity
- Predictable Execution
- Predictable Execution on GPU Caches
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Probabilistic training algorithms for quantized neural networks
- Probing the limits of fake-quantised neural networks
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
- Project Meetings
- Project Plan
- Pulse Oximetry Fachpraktikum
- Putting Together What Fits Together - GrÆStl
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Quantum Transport Modeling of Interband Cascade Lasers (ICL)
- Quantum transport in 2D heterostructures
- RISC-V base ISA for ultra-low-area cores (2-3G)
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- RVfplib
- Radiation Testing of a PULP ASIC
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- RazorEDGE: An Evolved EDGE DBB ASIC
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time Embedded Systems
- Real-Time Implementation of Quantum State Identification using an FPGA
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor
- Real-Time Optical Flow Using Neural Networks
- Real-Time Optimization
- Real-Time Pedestrian Detection For Privacy Enhancement
- Real-Time Stereo to Multiview Conversion
- Real-time Linux on RISC-V
- Real-time View Synthesis using Image Domain Warping
- Real-time eye movement analysis on a tablet computer
- Realtime Gaze Tracking on Siracusa
- Receiver design for the DigRF 4G high speed serial link
- Reconfigurability of SHA-3 candidates
- Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication
- RedCap-5G for IOT application on prototype taped-out silicon
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- Research
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Resource Partitioning of Caches
- Resource Partitioning of RPC DRAM
- Rethinking our Convolutional Network Accelerator Architecture
- Robert Balas
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Running Rust on PULP
- Runtime partitioning of L1 memory in Mempool (M)
- SCMI Support for Power Controller Subsystem
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- SSR combined with FREP in LLVM/Clang
- SW/HW Predictability and Security
- Sandro Belfanti
- Satellite Internet of Things
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Scattering Networks for Scene Labeling
- Securing Block Ciphers against SCA and SIFA
- Self-Learning Drones based on Neural Networks
- Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
- Self Aware Epilepsy Monitoring
- Semi-Custom Digital VLSI for Processing-in-Memory
- Sensor Fusion for Rockfall Sensor Node
- Serverless Benchmarks on RISC-V (M)
- Shared Correlation Accelerator for an RF SoC
- Short Range Radars For Biomedical Application
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
- Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
- Signal to Noise Ratio Estimation for 3G standards
- Simulation of 2D artificial cilia metasurface in COMSOL
- Simulation of Li-ion batteries and comparison with experimental data
- Simulation of Negative Capacitance Ferroelectric Transistor
- Simultaneous Sensing and Communication
- Single-Bit-Synapse Spiking Neural System-on-Chip
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Skin coupling media characterization for fitnesstracker applications (1 B/S)
- SmartRing
- Smart Agriculture System (1-2S)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S)
- Smart Meters
- Smart Patch For Heath Care And Rehabilitation
- Smart Virtual Memory Sharing
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Smart e-glasses for concealed recording of EEG signals
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- Softmax for Transformers (M/1-2S)
- Software
- Software-Defined Paging in the Snitch Cluster (2-3S)
- Sound-Based Vehicle Classification and Counting (1-2S)
- Spatio-Temporal Video Filtering
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Spectrometry for Environmental Monitoring (1-2S/M)
- Spiking Neural Network for Autonomous Navigation
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Stand-Alone Edge Computing with GAP8
- Standard Cell Compatible Memory Array Design
- State-Saving @ NXP
- Stefan Lippuner
- Stefan Mach
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Streaming Integer Extensions for Snitch (M/1-2S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Structural Health Monitoring (SHM) System (1-2S/M)
- Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets
- Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub-Noise Floor Channel Tracking
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Subject specific embeddings for transfer learning in brain-computer interfaces
- Successive Approximation Register (SAR) ADC
- Successive Interference Cancellation for 3G Downlink
- Super Resolution Radar/Imaging at mm-Wave frequencies
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Switched Capacitor Based Bandgap-Reference
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- System Emulation for AR and VR devices
- TCNs vs. LSTMs for Embedded Platforms
- Taimir Aguacil
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- Tbenz
- Telecommunications
- Template
- Ternary Neural Networks for Face Recognition
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Test page
- Test project
- Testbed Design for Self-sustainable IoT Sensors
- Theory, Algorithms, and Hardware for Beyond 5G
- Thermal Control of Mobile Devices
- Through Wall Radar Imaging using Machine Learning
- Time Gain Compensation for Ultrasound Imaging
- Time Synchronization for 3G Mobile Communications
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Timing Channel Mitigations for RISC-V Cores
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Toward Superposition of Brain-Computer Interface Models
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Towards Autonomous Navigation for Nano-Blimps
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards Online Training of CNNs: Hebbian-Based Deep Learning
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards Self Sustainable UAVs
- Towards The Integration of E-skin into Prosthetic Devices
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards global Brain-Computer Interfaces
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Trace Debugger for custom RISC-V Core
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Decoder Design for High Code Rates
- Turbo Equalization for Cellular IoT
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Ultra-low power processor design
- Ultra-low power sampling front-end for acquisition of physiological signals
- Ultra-low power transceiver for implantable devices
- Ultra-wideband Concurrent Ranging
- Ultra Low-Power Oscillator
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Ultra low power wearable ultrasound probe
- Ultrafast Medical Ultrasound imaging on a GPU
- Ultrasound
- Ultrasound-EMG combined hand gesture recognition
- Ultrasound Doppler system development
- Ultrasound High Speed Microbubble Tracking
- Ultrasound Low power WiFi with IMX7
- Ultrasound based hand gesture recognition
- Ultrasound image data recycler
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- Ultrasound signal processing acceleration with CUDA
- Unconventional phase change memory device concepts for in-memory and neuromorphic computin
- Using Motion Sensors to Support Indoor Localization
- VLSI Design of an Asynchronous LDPC Decoder
- VLSI Implementation Polar Decoder using High Level Synthesis
- VLSI Implementation of a 5G Ciphering Accelerator
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM
- Variability Tolerant Ultra Low Power Cluster
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- Vector Processor for In-Memory Computing
- Versatile HW SW Digital PHY for inter chip communication
- Virtual Memory Ara
- Visualization of Neural Architecture Search Spaces
- Visualizing Functional Microbubbles using Ultrasound Imaging
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- Wake Up Radio For Energy Efficient Communication System and IC Design
- Watchdog Timer for PULP
- Waterflow Monitoring with Doppler Ultrasound (1S)
- Weak-strong massive MIMO communication with low-resolution ADCs
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Wearable Ultrasound for Artery monitoring
- Wearables for Sports and Fitness Tracking
- Wearables for Sports and Life Enhancement
- Wearables in Fashion
- Weekly Reports
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
- Wireless Biomedical Signal Acquisition Device
- Wireless Communication Systems for the IoT
- Wireless EEG Acquisition and Processing
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- Wireless Sensing With Long Range Comminication (LoRa)
- Writing a Hero runtime for EPAC (1-3S/B)
- XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
- Zephyr RTOS on PULP
- Zero Power Touch Sensor and Reciever For Body Communication
