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- ...iM accelerator and integrate the accelerator into a modern microcontroller system. 4. Verify functionality of the system3 KB (352 words) - 18:02, 16 December 2022
- [[Category:System Design]] [[Category:System on Chips for IoTs]]5 KB (614 words) - 15:02, 4 March 2019
- ...ch mode as well as the non-critical application should allow to reduce the system complexity significant and facilitates, therefore, a higher integration and ...erization of a discrete small size low power RF transmitter in an embedded system: prototype development, verification of the prototype's characteristics w.r5 KB (729 words) - 10:02, 22 February 2021
- [[Category:System Design]]5 KB (714 words) - 08:37, 23 November 2022
- ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with ...ign a dedicated casing to facilitate the usage of the probe and making the system a real product.3 KB (361 words) - 19:02, 6 December 2023
- ...ion and the classifier are meant to be implemented on a low-power embedded system. Given the constrained conditions under which we operate, i.e. implantable : Embedded system programming5 KB (634 words) - 19:20, 9 March 2020
- ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with [[Category:System Design]]3 KB (337 words) - 18:42, 6 December 2023
- ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with ....org/document/9630034] UStEMG: an Ultrasound Transparent Tattoo-based sEMG System for Unobtrusive Parallel Acquisitions of Muscle Electro-mechanics3 KB (437 words) - 19:03, 6 December 2023
- Motivation to build and test a real system3 KB (363 words) - 14:38, 14 April 2021
- ...roject focusses on the development of an unobtrusive multisensory embedded system to assist coaches to better quantify jumping trajectories of athletes. With ...perceptible to the athlete so as not to disturb his/her sensitive jumping system.6 KB (820 words) - 12:13, 23 July 2023
- Our project is designed to provide a reliable and efficient communication system that is optimized for IoT applications. Our project incorporates advanced p2 KB (243 words) - 11:44, 14 February 2023
- ...d data compression. The project will require simulation and testing of the system to verify its performance, power consumption, and compatibility with differ * Experience with System Verilog or Verilog, VLSI 12 KB (250 words) - 18:21, 20 February 2023
- ...are, we can guarantee a high flexibility of the setup. This means that the system can be adapted in operation for a wide variety of transducer types and setu The main goal of this work is to develop a modular system for the characterization and tuning of ultrasonic transducers both in hard-5 KB (644 words) - 18:18, 21 July 2023
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]4 KB (551 words) - 11:06, 11 July 2019
- ...A, configuration of the SDR, and the evaluation in Matlab. Eventually, the system has to be tested thoroughly. ...plore.ieee.org/document/8351613] A. Moin et al, An EMG Gesture Recognition System with Flexible High-Density Sensors and Brain-Inspired High-Dimensional Clas5 KB (731 words) - 16:42, 27 August 2019
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]4 KB (517 words) - 17:09, 16 September 2021
- [[File:nvdla_memory.png|right|NVDLA Memory System and High-Level Architecture]] ...hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data An6 KB (799 words) - 13:42, 10 November 2020
- ...propose to build the next OPEN-SOURCE RISC-V programmable smart-peripheral system for the Ariane Core. ...ct the PULPissimo microcontroller to the Ariane coreplex and map the whole system to the FPGA. Note that Ariane has already been mapped to the FPGA and it is7 KB (1,030 words) - 19:05, 29 January 2021
- Now we would like to upgrade the system by adding advanced machine learning capabilities for sensor fusion and repl ...age and frequency scaling (ADVFS) within the chip. In the end, upgrade the system with your energy harvesting solution.4 KB (522 words) - 10:45, 31 January 2023
- ...is thesis, you will design a novel heterogeneous interconnect for the PULP system to connect high-throughput hardware accelerators to ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended7 KB (961 words) - 21:21, 29 January 2019
- ...act''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - ' ...hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data An6 KB (915 words) - 18:16, 20 May 2020
- [[Category:System Design]] [[Category:System on Chips for IoTs]]5 KB (623 words) - 10:32, 5 November 2019
- ...ectrometer may be used in combination with different devices, the designed system should be easily adaptable to different use cases.4 KB (506 words) - 18:26, 5 November 2019
- ...ct the way biomechanical measurements are performed today, as the proposed system should be easy and quick to use (e.g., time is key for testing patients in [[Category:System on Chips for IoTs]]6 KB (735 words) - 12:12, 23 July 2023
- Now, we want to equip the system with a 192 element sensor to achieve better image quality (resolution, cont ...and electrical constraints to be properly be intergated with the existing system.2 KB (263 words) - 20:47, 12 November 2020
- ...ly. In contrast to approximate computing where the precision of the entire system is reduced - often incurring loss in result quality - transprecision comput * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx8 KB (1,135 words) - 17:09, 29 July 2020
- * Simulation of the ultrasound imaging system to evaluate the idea (feasibility & performance) * Implement the idea on our system (only in case of a Master Thesis)2 KB (220 words) - 20:46, 12 November 2020
- ...t fading channels is thus needed to improve the performance of the current system in such scenarios.3 KB (415 words) - 18:54, 29 October 2020
- ...iously developed digital baseband receiver block integrated in a processor system shall be used as a starting point. As a first step you will identify the in3 KB (431 words) - 21:47, 18 November 2019
- ...he occurrence of ionization events due to cosmic radiation. The monitoring system has to acquire the frequency of the ionizing events and the amount of the c : • Design the monitoring system4 KB (493 words) - 16:31, 5 June 2019
- **system: ***src: Top-level and auxiliary files for the core-v-mcu system.9 KB (1,314 words) - 00:01, 7 February 2021
- ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...memory system at one point in time. To avoid stalling the program when the system is not permitting memory accesses from the program in question, the memory4 KB (531 words) - 18:00, 19 June 2019
- ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...memory system at one point in time. To avoid stalling the program when the system is not permitting memory accesses from the program in question, the memory3 KB (466 words) - 18:20, 19 June 2019
- ...E capacitive sensing: pass information across an air gap. Design analogous system to perform a measurement task. For reference: https://www.st.com/en/solutio 5: Consumable ID: Design a new data frame of credit card reader/writer style system. Current format is 12mm in length, 8mm length required.5 KB (645 words) - 15:41, 10 November 2020
- ...pikes due to cosmic rays being captured by sequential elements, taking the system into a faulty state.6 KB (980 words) - 14:46, 2 June 2021
- #REDIRECT [[PULP in space - Fault Tolerant PULP System for Critical Space Applications]]88 bytes (13 words) - 13:10, 9 August 2019
- [[Category:System Design]]2 KB (305 words) - 15:28, 23 October 2023
- * Motivation to build and test a real system [[Category:System Design]]4 KB (519 words) - 15:41, 10 November 2020
- ...ortant component in sevral cyber-physical systems. Among other, the vision system of a self-driving takes advantage of DNNs to better recognize pedestrians, * Motivation to build and test a real system4 KB (509 words) - 15:41, 10 November 2020
- ...rphic intelligence using their processor to build a whole working embedded system. The student will deal with both hardware and software building a prototype * Motivation to build and test a real system5 KB (692 words) - 15:45, 10 November 2020
- ...ock diagram, which involves both the programming of a Low power FPGA and a System on Chip with ARM cortex-M4F and Bluetooth low energy 5.0. The project is qu * Motivation to build and test a real system4 KB (526 words) - 15:48, 10 November 2020
- * Motivation to build and test a real system [[Category:System Design]]4 KB (500 words) - 15:48, 10 November 2020
- <!-- Manycore System on FPGA --> At ETH, we are developing our own many-core system called MemPool [1]. It boasts 256 lightweight 32-bit Snitch cores developed8 KB (1,319 words) - 10:41, 6 July 2021
- ...essors. This ''separation of compute acceleration and control'' limits the system's flexibility and real-world performance as communication and data exchange7 KB (917 words) - 17:04, 24 November 2023
- : 80% System Development [[Category:System on Chips for IoTs]]5 KB (584 words) - 12:09, 29 October 2020
- 4. test and assess system level functionality, and provide post layout power/performance estimations4 KB (651 words) - 19:10, 29 January 2021
- ...performing one, the student will proceed with embedded implementation and system integration in order to demonstrate a real-life application using sensor ac2 KB (317 words) - 11:10, 21 July 2020
- ...as a basis for prototyping the BirdGuard algorithms and the deterrence sub-system. Swiss research institutes are at the forefront of researching birds and ap The BirdGuard system aims to complement existing passive approaches by providing an easy-to-use5 KB (647 words) - 08:32, 23 February 2023
- ...ly transmitting, easy to install and cost-effective for wind turbines. The system will integrate novel embedded signal processing solutions, including artifi ...classification accuracy, and energy efficiency and to further optimize the system. Energy Harvesting can be also employed to design the sensor node, and this5 KB (737 words) - 15:48, 10 November 2020
- 4. Quantize and deploy the network on a PULP system equipped with modular SNN accelerator, and evaluate the accuracy loss cause4 KB (644 words) - 19:10, 29 January 2021
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]7 KB (882 words) - 14:33, 28 July 2021
- * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx5 KB (759 words) - 09:18, 16 September 2021
- ...ulation, data pre-processing, wireless power and data transfer and overall system control. Data is generally processed inside the implant in the digital doma3 KB (381 words) - 11:22, 21 July 2020
- [[Category:System Design]]5 KB (628 words) - 12:51, 17 April 2020
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (662 words) - 13:31, 10 May 2023
- ...ented in a neuromorphic processor, and none of them are presenting a whole system from the data acquisition to the processing. ...of the present project is to investigate and develop a novel neuromorphic system for Brain–computer interfaces, trained for multi-class motor-imagery, th6 KB (815 words) - 20:02, 10 March 2024
- ...isfy electrical constraints to be properly be intergated with the existing system.5 KB (620 words) - 07:56, 26 May 2020
- ...detection and location of such seizures. When aiming a low power implanted system the large amount of data has to be efficiently reduced. iEEG signals are sp5 KB (636 words) - 20:01, 10 March 2024
- : Embedded system programming5 KB (619 words) - 19:58, 10 March 2024
- ...ehicles. There are several embodiments of the PULP paradigm, one of them a system-on-chip (SoC) called ''Mr.Wolf''[5]. This SoC features 9 cores, divided int8 KB (1,117 words) - 22:17, 26 January 2022
- [[File:GL_dpalossi.png|thumb|right|1000px|Overview of the cyber-physical system.]] ...tiple workloads thanks to a parallel ultra-low power octa-core (PULP) GAP8 System-on-Chip [6].4 KB (571 words) - 12:11, 27 January 2022
- ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx7 KB (1,032 words) - 15:31, 16 November 2020
- ...oncept.png|thumb|350px|Concept art for ''Manticore'', a Snitch-based 22 nm system with 4096 cores on multiple chiplets and with HBM2 memory.]] ...ing chips with industry-grade automated test equipment (ATE) and design of system-level demonstrator boards.11 KB (1,337 words) - 10:54, 25 January 2024
- ...s is to have Halide programmed image processing kernels running on an HERO system implemented on an FPGA.5 KB (737 words) - 17:26, 2 November 2020
- <!-- (M): A Flexible Peripheral System for High-Performance Systems on Chip --> One of the most tedious and error-prone steps is assembling a peripheral system with the required and desired IO; this usually involves adapting existing p11 KB (1,675 words) - 15:40, 15 March 2021
- ...0px|alt=A HERO system with a Zynq MPSoC coupled to a Snitch cluster|A HERO system with a Zynq MPSoC coupled to a Snitch cluster]] ...onents are meant to be exchangeable. HERO features a shared virtual memory system between host and accelerator and provides a heterogeneous compiler toolchai11 KB (1,617 words) - 23:59, 6 February 2021
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]4 KB (513 words) - 14:16, 24 November 2021
- * 25% System programming4 KB (563 words) - 20:08, 15 February 2021
- ...everaging the DaCe framework to generate code for ETH’s Snitch processor system.2 KB (333 words) - 20:05, 15 February 2021
- [[Category:System Design]]3 KB (404 words) - 10:05, 9 February 2021
- Modern heterogeneous System-on-Chips (SoCs) are cost-efficient and feature the processing power requir2 KB (313 words) - 11:47, 2 November 2020
- ...n technique is to combine multiple instances of a core to a ''multi-core'' system. This technique introduces a new challenge: Each core keeps its own copy of * a coherent memory system must be able to invalidate or update specific cache lines, and to request s3 KB (395 words) - 16:32, 15 November 2022
- ...l work with Ultrasound Images acquired with a high-end Ultrasound research system, to build ML algorithms for the extraction of such physiological features. [[Category:System Design]]2 KB (258 words) - 15:28, 23 October 2023
- [[Category:System Design]]3 KB (378 words) - 16:57, 16 September 2022
- The [[LightProbe]] system is designed to acquire ultrasound data for many different applications (e.g ...of LightProbe, you will identify the approach to use to include TCG in the system, and, once implemented, you will perform ultrasound test measurements on ph2 KB (318 words) - 16:58, 16 September 2022
- The students will work on a Smart Meter, an IoT system based on: The system will periodically wake up, take a picture, process the image extracting the3 KB (396 words) - 10:14, 23 August 2023
- ...novel solutions to reducing the energy consumption of such devices on the system-level are required. One of the key ideas in event-driven computing is the r * Basic knowledge of the System Verilog or VHDL language and circuit design (VLSI 1)3 KB (449 words) - 08:41, 17 February 2021
- ...IPs is the norm, but becomes more difficult and error-prone the larger the system becomes. ...simply a loose collection of scripts and templates shipped with the Snitch system [https://github.com/pulp-platform/snitch]. You will4 KB (617 words) - 10:19, 3 November 2023
- #REDIRECT [[Implementation of a Heterogeneous System for Image Processing on an FPGA (S)]]90 bytes (13 words) - 17:26, 2 November 2020
- ...s private memory banks---this, however, impacts the programmability of the system. ...eved through a cache hierarchy, which impacts the energy efficiency of the system through its non-negligible power consumption.8 KB (1,196 words) - 10:41, 6 July 2021
- ...ature extraction, and since it has been showed that the performance of the system can be largely influenced by this choice, the aim of this project is to do ...representation of the signal to the actual response of the human auditory system. The derivation techniques are described in detail in [[#ref-lyonmfcc|[13 KB (1,815 words) - 13:31, 15 February 2024
- #REDIRECT [[Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)]]82 bytes (11 words) - 17:40, 2 November 2020
- : 80% System Development [[Category:System on Chips for IoTs]]8 KB (931 words) - 17:27, 23 November 2021
- * Computer and System Architectures1 KB (120 words) - 15:52, 9 August 2023
- ...ure 1 shows the block diagram of HERO. It features a shared virtual memory system between host and accelerator and provides a heterogeneous compiler toolchai ...ftware to interact with a PMCA, such as MemPool. In this step, the MemPool system will be integrated and connected to HERO’s accelerator interface.6 KB (902 words) - 19:07, 20 January 2021
- * Synthesize your controller and the surrounding system; create area and timing reports. * Implement your system on an ASIC and tape it out.8 KB (1,214 words) - 15:18, 9 July 2021
- # Design and verify a ternary compression algorithm in System Verilog or VHDL * Basic knowledge of System Verilog or VHDL and digital circuit design (VLSI 1)3 KB (438 words) - 08:41, 17 February 2021
- .../>[[#ref-RISCV_P|8]]]. The set of instructions that should be added to the system is not fixed, but the student should implement and evaluate different image9 KB (1,311 words) - 00:08, 13 March 2021
- A cell-free system is a network formed by distributed access points (APs) over a large area co ...tudied in [3]. Last, to solve the lack of usage of all APs in this type of system, [4] presents an energy efficient AP sleep mode-technique that is able to d7 KB (882 words) - 21:34, 13 July 2022
- [[File:Image_RIS.png|400px|thumb|RIS aided wireless system.]] In [1], a RIS is used in the downlink of a MIMO system to investigate the improvement provided by these devices in terms of energy8 KB (1,011 words) - 12:25, 16 November 2023
- ...ch topics are actively ongoing around the human body, from chip design, to system development, to algorithmic investigations in various application scenarios [[File:ustemg.jpg|thumb|left|120px| Ultrasound Transparent EMG System]]9 KB (1,292 words) - 19:16, 23 March 2024
- * How much power does a Snitch system consume, what is the minimum power required, and can we compete with a micr * Familiarize yourselves with the Snitch system2 KB (365 words) - 20:03, 15 February 2021
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (653 words) - 11:08, 12 November 2020
- ...the signals transmitted by the individual antenna elements, providing the system with the capability to “beamform,” that is, to control the direction an : 70% System development6 KB (829 words) - 11:37, 12 November 2020
- ...the project is to then implement Deep Unfolding on a resource-constrained system, like a Raspberry Pi. This project requires familiarity with calculus and p : 20% Software implementation in resource-constrained system6 KB (748 words) - 13:57, 12 November 2020
- [[Category:System Design]]3 KB (389 words) - 01:43, 10 February 2021
- ...as complete autonomous drones. The students will follow the full flow from system design to firmware implementation and they can also deal with machine learn * A complete hardware and software prototype of drones and smart sensor system, which includes all the subsystems (sensor acquisition, preprocessing, and5 KB (646 words) - 11:39, 30 November 2020
- ...a team, they will learn how to structure problems and identify solutions, system analysis, and simulation, as well as presentation and documentation techniq * Motivation to build and test a real system and acquiring field data7 KB (1,033 words) - 16:24, 30 November 2020
- * Computer and System Architecture890 bytes (104 words) - 18:33, 8 December 2020
- ...goal of the present project is to investigate and develop a novel embedded system for acquiring and processing short range data with machine learning. Accord ...ncrease the response time of the detection, aiming to achieve an always-on system.5 KB (692 words) - 12:46, 17 December 2021
- ...onnecting 4 Baikonur ASICs through their serial links, creating a 104-core system with both application- and HPC-grade cores. ...onality. However, a lot of work still needs to be done to ''bring up'' the system so we can turn use it as an impressive evaluation and demonstration platfor11 KB (1,602 words) - 15:19, 9 July 2021
- ...is equipped with a wireless link, which is the main power consumer of the system. [[Category:System Design]]2 KB (273 words) - 16:57, 16 September 2022
- ...ulation, data pre-processing, wireless power and data transfer and overall system control. Data is generally processed inside the implant in the digital doma3 KB (388 words) - 09:25, 16 September 2021
- ...his coordination can limit the potential speedup offered by the multi-core system according to Amdahl’s law [[#ref-Hennessy2017|[1]]]. Efficient m ...uch an instruction requires the support of the interconnect and the memory system. We recently developed and published ATomic UNit (ATUN) [[#ref-Kurth2020|&12 KB (1,864 words) - 12:08, 29 August 2022
- ...the reference oscillator responsible for delivering the main clock of the system. The latter will be more challenging with adjustable input and output volta2 KB (257 words) - 11:38, 20 August 2021
- ...ool’s flexibility by having a duality of modes. The result is a flexible system that achieves a very high throughput for systolic workloads. ...y. Therefore, you drastically reduce the power consumption and improve the system’s efficiency. Again, the impact of this network has to be analyzed in Mem13 KB (1,887 words) - 15:51, 17 November 2021
- ...f this project is to take a step towards a fully-featured autonomous Linux system based on Ariane with extensive user interaction support. To this end, you w ...his project, you will learn to work with and extend an advanced processing system all the way from the RTL/hardware level to the Linux kernel and userspace l7 KB (1,122 words) - 15:21, 9 July 2021
- ...CB for the iCE40 family to facilitate measurements and/or demonstrate your system in action. Can we compete with a microcontroller in terms of performance an8 KB (1,220 words) - 15:18, 9 July 2021
- * Extending DaCe to generate efficient code for a Snitch system from SDFGs, ideally for the existing Snitch-HERO platform. ...isting C++ DaCe backend to emit LLVM-compilable code for a manycore Snitch system like Snitch-HERO. Validate your implementation on simple kernels or selecte11 KB (1,519 words) - 15:20, 9 July 2021
- * Basic knowledge of the C language and embedded system programming2 KB (366 words) - 15:53, 11 October 2021
- ...pport for sub-byte arithmetic operations (e.g., 16x2b MAC) and construct a system around the improved core, which will be taped out. You get to build your ow5 KB (768 words) - 15:14, 4 August 2022
- [[Category:System Design]]3 KB (463 words) - 08:38, 23 November 2022
- ...e user’s characteristics can considerably improve the performance of the system. We want to explore how the user-specific features can be exploited in orde ...ility of those features belonging to a certain class. A schematic of a KWS system can be seen in Figure 1.11 KB (1,610 words) - 11:00, 14 November 2022
- ...A countermeasure on top of the existing design, and 3) drive the resulting system through an ASIC tapeout process. : 60% VHDL/System Verilog, ASIC Design6 KB (849 words) - 18:43, 23 November 2021
- *General interest in Deep Learning and memory/system design ...p-digital-ic-design-engineer HW Design and Enhancement for ML Acceleration System] || AI Acceleration || digital VLSI design || [mailto:renzo.andri@huawei.c6 KB (799 words) - 11:11, 1 August 2022
- ...sor. The project can be done in the context of a single-core or multi-core system such as PULP where the accelerator is shared by multiple Ibex cores.6 KB (835 words) - 12:52, 27 April 2021
- * Test the throughput of the system and corresponding power consumption. [[Category:System Design]]2 KB (240 words) - 16:56, 16 September 2022
- ...Thus, wireless transmission of non-relevant information makes the overall system inefficient. ...result in power saving, and thus increased operation time of the wearable system.3 KB (364 words) - 18:42, 6 December 2023
- ...work on the development of hardware and software for a complete biomedical system.797 bytes (90 words) - 16:37, 23 February 2022
- Modern system-on-a-chip is usually an integration of heterogeneous building blocks. Such2 KB (203 words) - 18:03, 16 December 2022
- ...while reducing the damage caused by the implantation [1][2]. However, such system also poses stringent constraints on the power consumption and area. 2. Get familiar with the dataset and the system4 KB (519 words) - 16:16, 9 January 2023
- 2. Get familiar with the dataset, the system, and the deep learning framework5 KB (662 words) - 20:05, 10 March 2024
- ...ully applied to the problem to increase the energy efficiency of the final system. One such class of networks are ternary neural networks (TNNs), where all w3 KB (404 words) - 09:54, 8 March 2023
- At ETH, we are developing our own many-core system called MemPool [[#ref-Cavalcante2020|[1]]], [[#ref-Riedel2021|[ ...y rely on cycle-accurate RTL simulation. However, simulation of such a big system is slow, even on the latest commercial simulators. This limits the complexi10 KB (1,434 words) - 17:20, 2 August 2021
- At ETH, we are developing our own many-core system called MemPool. It boasts 256 lightweight 32-bit Snitch cores. They impleme This manycore system with vector support is to be analyzed in terms of the performance improveme11 KB (1,609 words) - 10:00, 30 June 2022
- ...an hardware design at the circuit level of time-encoded SNNs to high-level system simulations in a high-performance computing framework. It also involves int3 KB (360 words) - 10:54, 31 August 2021
- ...This means that their definition could be propagated throughout the memory system to further hide latency, minimize traffic, and improve memory management (p ...ergy, and timing impact of these extensions on a minimal end-to-end memory system (extended core, memory, and any adapters needed) running simple application4 KB (557 words) - 16:14, 6 November 2022
- ...d within a single layer. In order to utilize these results in a real-world system, we need to map the resulting mixed-precision network to an appropriate rep3 KB (497 words) - 22:15, 23 November 2022
- Epilepsy is a central nervous system disorder in which brain activity becomes abnormal, causing seizures or peri ...Mr. Wolf multicore processor on board. The project’s goal is to design a system capable of detecting various artifacts and then indicate to the user that a2 KB (313 words) - 15:25, 23 October 2023
- ...uous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt ...oped in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics a6 KB (687 words) - 13:32, 10 May 2023
- Epilepsy is a central nervous system disorder in which brain activity becomes abnormal, causing seizures or peri4 KB (561 words) - 15:25, 23 October 2023
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (659 words) - 14:08, 15 February 2024
- ...ature extraction, and since it has been showed that the performance of the system can be largely influenced by this choice, the aim of this project is to do ...representation of the signal to the actual response of the human auditory system. The derivation techniques are described in detail in [[#ref-lyonmfcc|[12 KB (1,688 words) - 11:00, 14 November 2022
- ...ware-constrained devices, expanding the capabilities of a keyword spotting system. ...pervised information. This is possible due to the prior knowledge that the system has over the nature of the data that it is presented with, and it is a spec12 KB (1,869 words) - 17:37, 1 September 2023
- ...e:motivation_sensor.png|200px|thumb|right|Example of remote controlled DAQ system]] ...to remote control the local data acquisition. Regarding energy supply, the system should be designed as a hybrid solution. It will incorporate a battery-powe4 KB (467 words) - 12:58, 20 July 2023
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]6 KB (725 words) - 17:36, 20 October 2021
- ...ltrasound data acquisition from a reduced number of channels. The proposed system architecture is based on an MSP430 MCU, which is equipped with an Ultrasoun [[Category:System Design]]3 KB (381 words) - 19:03, 6 December 2023
- ...magined by the user by means of BCI devices. Once fully functional, such a system would be of immeasurable value in the design of, e.g., motorized prostheses8 KB (1,101 words) - 20:04, 10 March 2024
- ...ttern information such as loop bounds and strides) ''throughout the memory system''. To this end, we are currently extending the AXI4 [3] memory protocol, us A simple demonstrator system building on your extended IPs could also be built.3 KB (431 words) - 16:13, 6 November 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]7 KB (933 words) - 19:29, 21 November 2021
- ...mbedded systems going through the full stack of hardware design, operating system and hacking the compiler. I'm an avid free software contributor, GNU/Linux931 bytes (108 words) - 10:30, 22 November 2021
- ...ludes them from being used in a portable system. Furthermore, surveillance system typically do not come with any localized intelligence, so their recorded da In this project, a novel, distributed and energy-efficient surveillance system will be brought up and optimized by the student.3 KB (433 words) - 15:36, 4 August 2022
- ...] and the floating-point repetition (FREP) hardware loop, which allows the system to achieve FPU utilization above 90%. ...ave been historically integrated into the PULP cluster, but a Snitch-based system would greatly benefit by supporting these hardware modules.4 KB (567 words) - 13:57, 7 September 2022
- ...out a slightly smaller version of Manticore, called Occamy, a two-chiplet system in the near future. Snitch-based architectures are built around the minimal4 KB (613 words) - 10:13, 2 November 2022
- ...ct the activity of the individual functional units and therefore the whole system. They are usually employed to profile applications performance and resource ...xplore.ieee.org/abstract/document/845896 A survey of design techniques for system-level dynamic power management]</div>5 KB (688 words) - 13:51, 27 October 2022
- ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with : 30% system development3 KB (336 words) - 19:03, 6 December 2023
- ...on primitives used in FreeRTOS [4] [5], an open-source real-time operating system (RTOS) used by Amazon, and determine how they use critical sections. Turn t4 KB (508 words) - 18:59, 10 January 2022
- * '''Research''': Investigate how Linux interacts with a system-level DMA and collect a set of minimal requirements for the hardware.2 KB (244 words) - 12:12, 21 June 2022
- ...ical instant''' at which these results are produced. In fact, a real-time system changes its state as a function of physical time. ...controlled object'' (the ''controlled cluster''), the ''real-time computer system'' (the ''computational cluster'') and the ''human operator'' (the ''operato4 KB (518 words) - 09:54, 10 January 2022
- ...Evaluate the performance of your kernels''' in RTL simulations of a Snitch system4 KB (554 words) - 09:49, 17 August 2022
- ...ly. For all of these purposes, we heavily use ''Git'' as a version control system at IIS. If you have no previous experience with Git, we ''strongly'' advise10 KB (1,428 words) - 13:31, 27 October 2022
- ...to fit our needs, and evaluate their performance benefits of the resulting system. A main goal of this thesis is to create a Snitch-based system which is suitable for the type of embedded/edge applications targeted by th6 KB (770 words) - 14:19, 15 September 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]7 KB (804 words) - 19:45, 21 November 2021
- ...ower domain, voltage, clock and sensor management through a shared mailbox system with the PCS. [1] [https://developer.arm.com/documentation/den0056/latest Arm System Control and Management Interface]3 KB (467 words) - 13:55, 12 October 2022
- <!-- Peripheral Event Linking System For Real-Time Capable Energy-Efficient SoCs (M/1-2S) --> ...unities are limited due to the necessity to retain major parts of the main system memory due to the use of static random access memory (SRAM) for code execut8 KB (1,127 words) - 19:54, 1 March 2023
- [[File:Mcs.png|thumb|350px| A Mixed Criticality System (MCS).]] ...-time computer system is a computer system in which the correctness of the system behavior depends not only on the '''logical results''' of the computations,5 KB (614 words) - 09:49, 15 January 2024
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]4 KB (520 words) - 14:52, 24 November 2021
- ...ists of an analog front-end, a data converter, a wireless communication system and a wireless power receiver. ...ze the noise efficiency of the LNA and reduce the power consumption of the system. At the same time, novel wireless power receiver structures should be explo3 KB (381 words) - 19:19, 25 November 2021
- ...tware malfunction, the WDT will not be properly serviced, resulting in the system returning to its original state.2 KB (337 words) - 08:49, 21 June 2022
- Epilepsy is a central nervous system disorder in which brain activity becomes abnormal, causing seizures or peri ...implementing a self-aware machine learning model to be used in a wearable system for real-time detection of epileptic seizures.2 KB (298 words) - 15:25, 23 October 2023
- ...Mr. Wolf multicore processor on board. The project’s goal is to design a system capable of acquiring reliable EEG signals during motion, transmitting them3 KB (369 words) - 15:04, 20 July 2023
- ...ding environment, for example external master devices interacting with the system through I/O peripheral interfaces. This means that the underlying HW has to4 KB (515 words) - 15:06, 5 August 2022
- ...ization capabilities to the cluster of ControlPULP, allowing the operating system to schedule several accelerator tasks and let them run concurrently. This a * Evaluate the resulting system in RTL simulation and/or on the FPGA, for which a mature implementation of6 KB (835 words) - 16:27, 7 July 2023
- [[Category:Biomedical System on Chips]]4 KB (535 words) - 16:56, 12 July 2022
- : 25% System assembly design : 25% embedded system programming3 KB (410 words) - 19:02, 6 December 2023
- : 25% System assembly design : 25% embedded system programming3 KB (420 words) - 19:01, 6 December 2023
- ...with the obstacles. Furthermore, to further extend the capabilities of the system, you will have to implement a path planning solution that optimally drives4 KB (604 words) - 14:07, 10 March 2022
- ...ability of signal spikes being captured by sequential elements, taking the system into a faulty state. While some fault tolerance schemes utilize Triple Modu2 KB (311 words) - 08:49, 21 June 2022
- ...t. This new approach will be simulated in MATLAB for a mmWave massive MIMO system and the optimal number format parameters are chosen. Then, a matrix-vector The ideas of this project can be extended to other system blocks such as the beamspace FFT, so that these blocks generate their outpu5 KB (662 words) - 17:14, 26 September 2023
- ...li. The project also includes MATLAB simulations for a mmWave massive MIMO system with channels generated by QuadRiGa [8] or from a commercial raytracing cha5 KB (771 words) - 16:32, 8 February 2022
- ...y QuadRiGa [8] or from a commercial ray-tracing simulator, we will explore system-level aspects such as the possibility of reusing the equalization matrix ac6 KB (843 words) - 17:16, 26 September 2023
- ...with the goal of verifying the effectiveness and practicability of such a system, which will answer the question of whether reliable UAV detection is indeed : 20% System-level simulation5 KB (564 words) - 16:12, 9 February 2022
- : 20% System-level simulation [[Category:System on Chips for IoTs]]5 KB (586 words) - 16:15, 9 February 2022
- [[File:ToFDrone_dpalossi.png|thumb|right|500px|Overview of the cyber-physical system.]] ...latform is the Bitcraze Crazyflie 2.1 [4] extended by a powerful multicore System-on-Chip (SoC), the parallel ultra-low power (PULP) GAP8 [5] aboard the AI-d4 KB (550 words) - 21:25, 15 February 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]7 KB (831 words) - 19:36, 12 January 2023
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]6 KB (839 words) - 14:08, 15 February 2024
- '''Multiprocessor System-on-Chip (MPSoCs)''' are getting more popular in the domain of '''Critical R ...g CPU overload with respect to single-core applications, improving overall system’s performance [2].6 KB (869 words) - 14:47, 7 July 2023
- ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. The velocity of liquid flows (as for arteries and veins) can be measured b Preliminary results of custom syringe pump system:3 KB (363 words) - 17:18, 3 May 2024
- : 50% Asynchronous VLSI design with System Verilog1 KB (138 words) - 13:34, 25 May 2022
- ...n efficient hardware architecture. The HDL implementation can be done with System Verilog. Then a synthesis must be carried out as well as the backend routin990 bytes (143 words) - 14:36, 25 May 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]4 KB (503 words) - 13:54, 30 May 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]4 KB (470 words) - 18:16, 27 May 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]4 KB (492 words) - 10:55, 16 June 2022
- ...is to simulate interband cascade lasers based on the InAs-GaInSb material system with an in-house quantum transport solver called OMEN and to determine thei3 KB (365 words) - 10:19, 31 May 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (662 words) - 13:33, 10 May 2023
- ...ept of the existing ULP probe, we aim to replace the BLE link with a Spark system. To this end, the student will start working with evaluation boards, replac3 KB (366 words) - 15:10, 23 October 2023
- The power consumption of a system usually is the most difficult figure of merit to acquire, as it usually has2 KB (282 words) - 09:27, 3 November 2023
- .... So far we have verified the unit's correctness using a simple file-based System-Verilog testbench. * Simulates a more realistic memory system (multiple memories, complex latency pattern, reordering, ...)2 KB (226 words) - 14:22, 27 February 2024
- At ETH, we developed our own many-core system called MemPool. It boasts 256 lightweight 32-bit Snitch cores. They impleme ...d to integrate an FLL, a boot ROM, and a JTAG to access and initialize the system. While there are many IPs and know-how at IIS for that, this is also highly8 KB (1,239 words) - 12:36, 29 January 2024
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (586 words) - 15:34, 11 July 2022
- ...to run on a novel ultra-low-power processor, such as the PULP Kraken [3,4] System-on-Chip (SoC). At the same time, the candidate will also work on the hardwa4 KB (505 words) - 18:25, 26 July 2022
- .... So far we have verified the unit's correctness using a simple file-based System-Verilog testbench.2 KB (272 words) - 10:21, 3 November 2023
- ...osition unit that transposes matrices while they are copied throughout the system. The accelerator should work of full-precision integer and floating point f2 KB (214 words) - 09:39, 23 August 2023
- ...l). Among these, Zephyr OS [1] is a promising scalable real-time operating system with small memory footprint designed for resource-constrained systems follo ...required to be able to track and set the operating point of the controlled system in a workload-aware manner.3 KB (483 words) - 15:28, 19 February 2024
- ...required to be able to track and set the operating point of the controlled system in a workload-aware manner. Currently, we support FreeRTOS [5] in ControlPULP as real-time operating system using our custom compiler toolchain based on GCC [3] which supports various3 KB (438 words) - 16:51, 5 August 2022
- [https://www.rust-lang.org/ Rust] is a new, system-level general-purpose programming language fully compatible with C, incorpo * Interest in low-level programming of a manycore system2 KB (311 words) - 14:14, 29 June 2023
- At ETH, we are developing our own many-core system called MemPool [[#ref-Cavalcante2020|[2]]], [[#ref-Riedel2021|[4 KB (497 words) - 14:15, 29 June 2023
- WP3: System Development and HW Extension (8 weeks, November-December) System and method for an optimized Winograd convolution accelerator4 KB (549 words) - 11:35, 3 November 2023
- [[Category:Computer and System Architecture]] ...controller called x-heep, which shares most of the IPs with the ETH's PULP system.8 KB (1,304 words) - 14:44, 23 October 2023
- * Strong interest system design and hardware/software interaction3 KB (416 words) - 10:49, 25 January 2024
- * Experience with the System Verilog language, VLSI 12 KB (308 words) - 14:30, 8 March 2023
- ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. Recent research trends include the development of wearable US probes, with [[Category:System Design]]3 KB (354 words) - 19:02, 6 December 2023
- ...ed Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1M) --> ...ople.ee.ethz.ch/~janniss/projects/Maddness_system_integration.pdf Maddness System Intergration]6 KB (846 words) - 16:50, 3 November 2022
- ...ed Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1M) -->6 KB (823 words) - 16:32, 3 November 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (577 words) - 09:48, 5 October 2022
- * Empirically, by running more complex benchmarks and programs on the Ara system.5 KB (665 words) - 14:19, 18 October 2022
- ...e runs only in bare-metal mode and is not designed to support an Operating System. This is a shame since the scalar RV64GC core CVA6 does support it! ...s for easy porting of many external programs and drastically increases the system's usability.5 KB (769 words) - 11:38, 3 November 2023
- ...er(s) with the transcript of their respective speech. Lastly, the proposed system must abide by the TinyML[[#ref-reddi2020|[5]]] constraints consider11 KB (1,467 words) - 14:15, 1 March 2024
- Occamy is a massively-parallel multiprocessor system-on-chip (MPSoC) designed for energy-efficient high-performance computing (H7 KB (944 words) - 10:47, 25 January 2024
- ...L1 data-memory. Leveraging its hierarchical architecture, we can scale the system to TeraPool, a cluster of 1024 Snitch cores, having 4096 banks of shared me3 KB (490 words) - 10:38, 2 November 2023
- ...ame room. As access to the room will be limited during the experiment, the system should be designed to allow us to sample as much data as possible during th * 30% System design3 KB (454 words) - 14:59, 25 October 2023
- * to have a synthesizable fully configurable memory system. * to monitor key figures of merit online and in-system.2 KB (335 words) - 13:58, 27 October 2022
- <!-- AXI-based Network on Chip (NoC) system --> ...ould be to build a system with a mesh NoC and a couple of cores and do the system integration for a potential tapeout. For the verification, low-level softwa2 KB (252 words) - 14:43, 23 October 2023
- ...L1 data-memory. Leveraging its hierarchical architecture, we can scale the system to TeraPool, a cluster of 1024 Snitch cores, having 4096 banks of shared me3 KB (460 words) - 18:54, 9 November 2022
- ...chmark, optimize, and improve your testbenches simulating a large manycore system running real machine learning workloads (or booting Linux!). * 20% Benchmark and optimize the simulation speed of a large manycore system.2 KB (290 words) - 09:38, 3 November 2023
- * 30% Verification and evaluation OOC and in-system2 KB (249 words) - 09:36, 3 November 2023
- ...ce the model's memory footprint and open new opportunities to increase the system's energy efficiency.2 KB (307 words) - 18:20, 3 November 2023
- ...ostructure and its influence on the (quantum) transport properties of this system2 KB (302 words) - 18:47, 10 November 2022
- ...d Spatz on the TeraPool architecture as our hardware platform, a scaled-up system from MemPool [[#ref-Cavalcante2020|[2]]], which has 1024 Snitch cor ...r utilization, aiming to extract the maximum possible performance from the system.6 KB (775 words) - 11:57, 31 October 2023
- ...ler to improve predicatability of memory accesses. For example, Arm Memory System Resource Partitioning and Monitoring (MPAM)[5] is a recent example of such <div> [5] “Arm Memory System Resource Partitioning and Monitoring (MPAM)” https://developer.arm.com/do3 KB (379 words) - 09:32, 15 January 2024
- ...last-level cache (LLC) [4]. The strategy we are using is to make the whole system more predictable is resource partitioning. Specifically, partitioning the c3 KB (347 words) - 14:07, 4 March 2024
- ...n technique is to combine multiple instances of a core to a ''multi-core'' system. This technique introduces a new challenge: Each core keeps its own copy of ...ane cores. Throughout this project, the feasibility and performance of the system shall be evaluated.2 KB (260 words) - 16:41, 15 November 2022
- ...the voter detects discrepancy in the results, it alerts the system that a system failure happened and recovery or reset procedures must be initiated.5 KB (752 words) - 13:23, 24 October 2023
- ...reconfigurable vector processor cluster to optimize area footprint of the system; * Benchmark the system on the previously identified application and perform additional optimizatio5 KB (651 words) - 20:42, 22 November 2022
- * Integrate the IP into a full SoC system through an AXI-based DMA controller; * Interest in deepening system I/O communication topics5 KB (631 words) - 09:28, 3 November 2023
- * Integrate the peripheral into a full SoC system; * Interest in deepening system I/O communication topics4 KB (554 words) - 09:28, 3 November 2023
- ...es attracts more attentions. A better understanding of the brain and neuro system is needed. Since the number of electrophysiological signals generated by ne3 KB (466 words) - 10:26, 21 February 2024
- Voice activity detection (VAD) is a hot topic in nowadays IoT system that can be used for keyword spotting, speech recognition and audio recordi1 KB (191 words) - 17:04, 24 January 2023
- ...including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GH ...sumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with t3 KB (369 words) - 14:29, 25 January 2023
- ...Qubits will be read-out at the same time. For discrete Qubits, the readout system usually works at the sub-1 GHz frequency range. However, for a compact foot2 KB (372 words) - 10:32, 14 February 2023
- ...and drive the theoretical approach of using phased array as a super radar system. Also, based on the candidate progress, the project will involve validation2 KB (326 words) - 11:44, 14 February 2023
- This project explores the CTSD ADC from system level up to layout to be able to reach ENOB >= 10 bits with small power and2 KB (223 words) - 11:29, 14 February 2023
- ...s of 5G/6G communications and sensing through high performance circuit and system designs. We are particularly interested in systems with wide bandwidth, hi1 KB (145 words) - 16:26, 27 September 2023
- Epilepsy is a central nervous system disorder characterized by abnormal brain activity, causing seizures or peri ...ilst not forgetting the properties of previous users that might re-use the system; thus, our model must mitigate the "catastrophic forgetting" phenomenon.8 KB (1,271 words) - 15:04, 20 July 2023
- ...er(s) with the transcript of their respective speech. Lastly, the proposed system must abide by the TinyML[[#ref-reddi2020|[5]]] constraints consider9 KB (1,283 words) - 17:44, 1 September 2023
- ...ticast support directly into the interconnect of a shared-memory many-core system called Occamy [4]. In Occamy, 216+1 cores and their tightly-coupled data me [4] [https://pulp-platform.org/occamy/ Occamy many-core chiplet system] <br />8 KB (1,177 words) - 11:45, 13 March 2024
- ...ed.png|450px|thumb|right|The envisioned high-performance multimodal vision system]] ...s of new possibilities for AI and tinyML. We are creating a completely new system, with an autonomous base station and distributed smart sensor nodes to run4 KB (572 words) - 11:07, 5 December 2023
- ...s of new possibilities for AI and tinyML. We are creating a completely new system, with an autonomous base station and distributed smart sensor nodes to run ...ng Projects]] [[Category:EmbeddedAI]] [[Category:SmartSensors]] [[Category:System Design]] [[Category:2023]] [[Category:Semester Thesis]] [[Category:Master T4 KB (553 words) - 11:02, 5 December 2023
- ...s of new possibilities for AI and tinyML. We are creating a completely new system, with an autonomous base station and distributed smart sensor nodes to run ...ng Projects]] [[Category:EmbeddedAI]] [[Category:SmartSensors]] [[Category:System Design]] [[Category:2023]] [[Category:Semester Thesis]] [[Category:Master T4 KB (523 words) - 10:55, 5 December 2023
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (578 words) - 12:39, 14 June 2023
- * 10% System design3 KB (383 words) - 14:29, 18 February 2024
- ...t needs to be accessed and monitored calls for a high-speed FPGA/GPU based system with a compact, and incubator-compatible hardware design. [[Image:Hangxing FPGA.png|800px| System Overview]]6 KB (720 words) - 16:27, 27 September 2023
- ...e that is non-preemptible'' which translates directly into a more reactive system. The core algorithms and data structures that are changed are the timer, in3 KB (460 words) - 15:29, 19 February 2024
- ...ta. To improve modern feedback methods in ski jumping, we aim to develop a system that collects athlete performance data with a body-worn sensor node and tra ...with real ski jumpers) shall demonstrate the performance of the developed system. According to the level of the student and the chosen thesis type (BT/ST) t6 KB (688 words) - 12:15, 23 July 2023
- ...ly. For all of these purposes, we heavily use ''Git'' as a version control system at IIS. If you have no previous experience with Git, we ''strongly'' advise [[Category:System on Chips for IoTs]]14 KB (2,018 words) - 22:54, 23 November 2023
- ...l motor control during action is difficult. Therefore, we aim to develop a system that translates sensor data into simple, motor-transferable information onl [[Category:System on Chips for IoTs]]6 KB (735 words) - 12:15, 23 July 2023
- * 34% System design and implementation ...ng Projects]] [[Category:EmbeddedAI]] [[Category:SmartSensors]] [[Category:System Design]] [[Category:2023]] [[Category:Semester Thesis]] [[Category:Bachelor5 KB (574 words) - 13:06, 20 July 2023
- ...ng Projects]] [[Category:EmbeddedAI]] [[Category:SmartSensors]] [[Category:System Design]] [[Category:2023]] [[Category:Semester Thesis]] [[Category:Bachelor3 KB (356 words) - 13:03, 20 July 2023
- Epilepsy, a central nervous system disorder, is characterized by abnormal brain activity resulting in seizures ...user without forgetting the properties of prior users who might reuse the system. This necessitates mitigating the "catastrophic forgetting" phenomenon in o9 KB (1,326 words) - 11:16, 12 October 2023
- ...s the model's memory footprint and opens new opportunities to increase the system's energy efficiency. For these reasons, many commercial platforms already p2 KB (341 words) - 15:54, 15 February 2024