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Showing below up to 250 results in range #101 to #350.
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- Zephyr RTOS on PULP (10 categories)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (10 categories)
- Streaming Layer Normalization in ITA (M/1-2S) (10 categories)
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings (10 categories)
- Extend the RI5CY core with priviledge extensions (10 categories)
- Big Data Analytics Benchmarks for Ara (10 categories)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (10 categories)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (10 categories)
- Next Generation Synchronization Signals (10 categories)
- Multi-Modal Environmental Sensing With GAP9 (1-2S) (10 categories)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (10 categories)
- Smart Meters (10 categories)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S) (10 categories)
- Fast Simulation of Manycore Systems (1S) (10 categories)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) (10 categories)
- Multi issue OoO Ariane Backend (M) (10 categories)
- Heroino: Design of the next CORE-V Microcontroller (10 categories)
- Shared Correlation Accelerator for an RF SoC (10 categories)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S) (10 categories)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M) (10 categories)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (10 categories)
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory (10 categories)
- BirdGuard (10 categories)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems (10 categories)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S) (10 categories)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) (10 categories)
- Improving datarate and efficiency of ultra low power wearable ultrasound (10 categories)
- Efficient TNN Inference on PULP Systems (10 categories)
- ASR-Waveformer (10 categories)
- Accelerator for Spatio-Temporal Video Filtering (10 categories)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (10 categories)
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache (10 categories)
- GUI-developement for an action-cam-based eye tracking device (10 categories)
- Implementing Configurable Dual-Core Redundancy (10 categories)
- Timing Channel Mitigations for RISC-V Cores (10 categories)
- PULP’s CLIC extensions for fast interrupt handling (10 categories)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (10 categories)
- Wireless Communication Systems for the IoT (10 categories)
- Data Augmentation Techniques in Biosignal Classification (10 categories)
- Taping a Safer Silicon Implementation of Snitch (M/2-3S) (10 categories)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (10 categories)
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex (10 categories)
- IP-Based SoC Generation and Configuration (1-3S/B) (10 categories)
- Creating A Boundry Scan Generator (1-3S/B/2-3G) (10 categories)
- Bridging QuantLab with LPDNN (10 categories)
- Improved Collision Avoidance for Nano-drones (10 categories)
- IoT Turbo Decoder (10 categories)
- ISA extensions in the Snitch Processor for Signal Processing (M) (10 categories)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (10 categories)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B) (10 categories)
- PULP Freertos with LLVM (10 categories)
- Floating-Point Divide & Square Root Unit for Transprecision (10 categories)
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications (10 categories)
- Machine Learning for extracting Muscle features from Ultrasound raw data (10 categories)
- Ultrasound Low power WiFi with IMX7 (10 categories)
- Softmax for Transformers (M/1-2S) (10 categories)
- Watchdog Timer for PULP (10 categories)
- Writing a Hero runtime for EPAC (1-3S/B) (9 categories)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (9 categories)
- Self Aware Epilepsy Monitoring (9 categories)
- Level Crossing ADC For a Many Channels Neural Recording Interface (9 categories)
- Probing the limits of fake-quantised neural networks (9 categories)
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) (9 categories)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S) (9 categories)
- LightProbe - WIFI extension (PCB) (9 categories)
- A Multiview Synthesis Core in 65 nm CMOS (9 categories)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (9 categories)
- Advanced 5G Repetition Combining (9 categories)
- Improving Cold-Start in Batteryless And Energy Harvesting Systems (9 categories)
- Hardware Constrained Neural Architechture Search (9 categories)
- Machine Learning for extracting Muscle features using Ultrasound 2 (9 categories)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M) (9 categories)
- Implementation of an Accelerator for Retentive Networks (1-2S) (9 categories)
- Internet of Things Network Synchronizer (9 categories)
- On-Device Federated Continual Learning on Nano-Drone Swarms (9 categories)
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection (9 categories)
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels (9 categories)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S) (9 categories)
- On-Device Learnable Embeddings for Acoustic Environments (9 categories)
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients (9 categories)
- Design and Implementation of an Approximate Floating Point Unit (9 categories)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) (9 categories)
- Knowledge Distillation for Embedded Machine Learning (9 categories)
- Outdoor Precision Object Tracking for Rockfall Experiments (9 categories)
- Cycle-Accurate Event-Based Simulation of Snitch Core (9 categories)
- Integrating Hardware Accelerators into Snitch (1S) (9 categories)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (9 categories)
- Ultrasound signal processing acceleration with CUDA (9 categories)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (9 categories)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) (9 categories)
- HERO: TLB Invalidation (9 categories)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (9 categories)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (9 categories)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications (9 categories)
- Deep neural networks for seizure detection (9 categories)
- EEG artifact detection for epilepsy monitoring (9 categories)
- On - Device Continual Learning for Seizure Detection on GAP9 (9 categories)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (9 categories)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (9 categories)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (9 categories)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B) (9 categories)
- Investigation of Quantization Strategies for Retentive Networks (1S) (9 categories)
- EEG artifact detection with machine learning (9 categories)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S) (9 categories)
- AXI-based Network on Chip (NoC) system (9 categories)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (9 categories)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (9 categories)
- BLISS - Battery-Less Identification System for Security (9 categories)
- Hardware/software codesign neural decoding algorithm for “neural dust” (9 categories)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (9 categories)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (9 categories)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (9 categories)
- Flexfloat DL Training Framework (9 categories)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (9 categories)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (9 categories)
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B) (9 categories)
- NVDLA meets PULP (9 categories)
- Wireless EEG Acquisition and Processing (9 categories)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (9 categories)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (9 categories)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S) (9 categories)
- Active-Set QP Solver on FPGA (9 categories)
- NeuroSoC RISC-V Component (M/1-2S) (9 categories)
- Ternary Neural Networks for Face Recognition (9 categories)
- Physics is looking for PULP (9 categories)
- Learning Image Decompression with Convolutional Networks (9 categories)
- Exploring NAS spaces with C-BRED (9 categories)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S) (9 categories)
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET (9 categories)
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B) (9 categories)
- Extreme-Edge Experience Replay for Keyword Spotting (9 categories)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M) (9 categories)
- An Efficient Compiler Backend for Snitch (1S/B) (9 categories)
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor (9 categories)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (9 categories)
- Learning at the Edge with Hardware-Aware Algorithms (9 categories)
- ASIC Development of 5G-NR LDPC Decoder (9 categories)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications (9 categories)
- Trace Debugger for custom RISC-V Core (9 categories)
- MemPool on HERO (1S) (9 categories)
- Adding Linux Support to our DMA Engine (1-2S/B) (9 categories)
- Improved State Estimation on PULP-based Nano-UAVs (9 categories)
- Monocular Vision-based Object Following on Nano-size Robotic Blimp (9 categories)
- Event-Driven Convolutional Neural Network Modular Accelerator (9 categories)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (8 categories)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (8 categories)
- Ibex: FPGA Optimizations (8 categories)
- Embedded Gesture Recognition Using Novel Mini Radar Sensors (8 categories)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (8 categories)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (8 categories)
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems (8 categories)
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices (8 categories)
- Thermal Control of Mobile Devices (8 categories)
- Ultra-wideband Concurrent Ranging (8 categories)
- Event-Driven Vision on an embedded platform (8 categories)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing (8 categories)
- Ultrasound image data recycler (8 categories)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (8 categories)
- SmartRing (8 categories)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (8 categories)
- Digital Transmitter for Mobile Communications (8 categories)
- Transformer Deployment on Heterogeneous Many-Core Systems (8 categories)
- RVfplib (8 categories)
- 3D Matrix Multiplication Unit for ITA (1S) (8 categories)
- Efficient NB-IoT Uplink Design (8 categories)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments (8 categories)
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion (8 categories)
- Hardware Exploration of Shared-Exponent MiniFloats (M) (8 categories)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) (8 categories)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (8 categories)
- High-throughput Embedded System For Neurotechnology in collaboration with INI (8 categories)
- Deep Learning for Brain-Computer Interface (8 categories)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M) (8 categories)
- Radiation Testing of a PULP ASIC (8 categories)
- Designing a Power Management Unit for PULP SoCs (8 categories)
- A Wearable System To Control Phone And Electronic Device Without Hands (8 categories)
- Zero Power Touch Sensor and Reciever For Body Communication (8 categories)
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) (8 categories)
- Extended Verification for Ara (8 categories)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) (8 categories)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M) (8 categories)
- Triple-Core PULPissimo (8 categories)
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores (8 categories)
- Spiking Neural Network for Autonomous Navigation (8 categories)
- Time Synchronization for 3G Mobile Communications (8 categories)
- Wearables in Fashion (8 categories)
- Android reliability governor (8 categories)
- PREM Intervals and Loop Tiling (8 categories)
- Real-time View Synthesis using Image Domain Warping (8 categories)
- DC-DC Buck converter in 65nm CMOS (8 categories)
- Accelerator for Boosted Binary Features (8 categories)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (8 categories)
- FPGA-Based Digital Frontend for 3G Receivers (8 categories)
- Compiler Profiling and Optimizing (8 categories)
- Smart Patch For Heath Care And Rehabilitation (8 categories)
- System Emulation for AR and VR devices (8 categories)
- Low-Dropout Regulators for Magnetic Resonance Imaging (8 categories)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 categories)
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras (8 categories)
- Vector Processor for In-Memory Computing (8 categories)
- RazorEDGE: An Evolved EDGE DBB ASIC (8 categories)
- Low Precision Ara for ML (8 categories)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (8 categories)
- Precise Ultra-low-power Timer (8 categories)
- Real-time eye movement analysis on a tablet computer (8 categories)
- DMA Streaming Co-processor (8 categories)
- Short Range Radars For Biomedical Application (8 categories)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 categories)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (8 categories)
- LightProbe - CNN-Based-Image-Reconstruction (8 categories)
- Mapping Networks on Reconfigurable Binary Engine Accelerator (8 categories)
- Energy Efficient AXI Interface to Serial Link Physical Layer (8 categories)
- Using Motion Sensors to Support Indoor Localization (8 categories)
- Extending our FPU with Internal High-Precision Accumulation (M) (8 categories)
- TCNs vs. LSTMs for Embedded Platforms (8 categories)
- Physical Implementation of ITA (2S) (8 categories)
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE (8 categories)
- Efficient TNN compression (8 categories)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (8 categories)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 categories)
- Integration Of A Smart Vision System (8 categories)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning (8 categories)
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles (8 categories)
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning (8 categories)
- Standard Cell Compatible Memory Array Design (8 categories)
- Efficient collective communications in FlooNoC (1M) (8 categories)
- A Wireless Sensor Network for a Smart Building Monitor and Control (8 categories)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) (8 categories)
- Predictable Execution on GPU Caches (8 categories)
- LightProbe - Frontend Firmware and Control Side Channel (8 categories)
- Extending the RISCV backend of LLVM to support PULP Extensions (8 categories)
- PVT Dynamic Adaptation in PULPv3 (8 categories)
- Bluetooth Low Energy receiver in 65nm CMOS (8 categories)
- Edge Computing for Long-Term Wearable Biomedical Systems (8 categories)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (8 categories)
- All the flavours of FFT on MemPool (1-2S/B) (8 categories)
- Novel Metastability Mitigation Technique (8 categories)
- Open Power-On Chip Controller Study and Integration (8 categories)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S) (8 categories)
- Securing Block Ciphers against SCA and SIFA (8 categories)
- Indoor Positioning with Bluetooth (8 categories)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 categories)
- PULP-Shield for Autonomous UAV (8 categories)
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring (8 categories)
- LightProbe - Implementation of compressed-sensing algorithms (8 categories)
- Towards global Brain-Computer Interfaces (8 categories)
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration (8 categories)
- VLSI Implementation of a 5G Ciphering Accelerator (8 categories)
- FPGA System Design for Computer Vision with Convolutional Neural Networks (8 categories)
- Runtime partitioning of L1 memory in Mempool (M) (8 categories)
