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Showing below up to 339 results in range #501 to #839.
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- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces (5 revisions)
- Adding Linux Support to our DMA Engine (1-2S/B) (5 revisions)
- Indoor Smart Tracking of Hospital instrumentation (5 revisions)
- Beat DigRF (5 revisions)
- A Wireless Sensor Network for a Smart Building Monitor and Control (5 revisions)
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC (5 revisions)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) (5 revisions)
- IBM A2O Core (5 revisions)
- Designing a Power Management Unit for PULP SoCs (5 revisions)
- Inductive Charging Circuit for Implantable Devices (5 revisions)
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control (5 revisions)
- Image Sensor Interface and Pre-processing (5 revisions)
- An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications (5 revisions)
- Embedded Artificial Intelligence:Systems And Applications (5 revisions)
- Low Latency Brain-Machine Interfaces (5 revisions)
- Hardware/software codesign neural decoding algorithm for “neural dust” (5 revisions)
- Resource Partitioning of Caches (5 revisions)
- FPGA Testbed Implementation for Bluetooth Indoor Positioning (5 revisions)
- State-Saving @ NXP (5 revisions)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) (5 revisions)
- Low-Complexity MIMO Detection (5 revisions)
- Design of a Fused Multiply Add Floating Point Unit (5 revisions)
- Development of an efficient algorithm for quantum transport codes (5 revisions)
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams (5 revisions)
- Eye tracking (5 revisions)
- Open Power-On Chip Controller Study and Integration (5 revisions)
- Andreas Kurth (5 revisions)
- LightProbe - Frontend Firmware and Control Side Channel (5 revisions)
- Simulation of 2D artificial cilia metasurface in COMSOL (5 revisions)
- Machine Learning for extracting Muscle features from Ultrasound raw data (5 revisions)
- 5G Cellular RF Front-end Design in 22nm CMOS Technology (5 revisions)
- Ultra-low power transceiver for implantable devices (5 revisions)
- Learning Image Compression with Convolutional Networks (5 revisions)
- Software-Defined Paging in the Snitch Cluster (2-3S) (5 revisions)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (5 revisions)
- Improving Resiliency of Hyperdimensional Computing (4 revisions)
- Every individual on the planet should have a real chance to obtain personalized medical therapy (4 revisions)
- Stefan Mach (4 revisions)
- IP-Based SoC Generation and Configuration (1-3S) (4 revisions)
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM. (4 revisions)
- Energy Neutral Multi Sensors Wearable Device (4 revisions)
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems (4 revisions)
- Evaluating An Ultra low Power Vision Node (4 revisions)
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications (4 revisions)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (4 revisions)
- Edge Computing for Long-Term Wearable Biomedical Systems (4 revisions)
- Android reliability governor (4 revisions)
- Fabian Schuiki (4 revisions)
- GPT on the edge (4 revisions)
- AMZ Driverless Competition Embedded Systems Projects (4 revisions)
- ASR-Waveformer (4 revisions)
- AnalogInt (4 revisions)
- Low Power Neural Network For Multi Sensors Wearable Devices (4 revisions)
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks (4 revisions)
- Routing 1000s of wires in Network-on-Chips (1-2S/M) (4 revisions)
- Design of State Retentive Flip-Flops (4 revisions)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments (4 revisions)
- DigitalUltrasoundHead (4 revisions)
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor (4 revisions)
- Low-Power Time Synchronization for IoT Applications (4 revisions)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (4 revisions)
- Guillaume Mocquard (4 revisions)
- Digital Transmitter for Cellular IoT (4 revisions)
- Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication (4 revisions)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (4 revisions)
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node (4 revisions)
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator (4 revisions)
- Design of low-offset dynamic comparators (4 revisions)
- Non-binary LDPC Decoder for Deep-Space Optical Communications (4 revisions)
- VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM (4 revisions)
- Near-Memory Training of Neural Networks (4 revisions)
- Intelligent Power Management Unit (iPMU) (4 revisions)
- Positioning for the cellular Internet of Things (4 revisions)
- Improving our Smart Camera System (4 revisions)
- Ibex: Bit-Manipulation Extension (4 revisions)
- Variability Tolerant Ultra Low Power Cluster (4 revisions)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers (4 revisions)
- Enhancing our DMA Engine with Fault Tolerance (4 revisions)
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning (4 revisions)
- Super Resolution Radar/Imaging at mm-Wave frequencies (4 revisions)
- Wireless Biomedical Signal Acquisition Device (4 revisions)
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications (4 revisions)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (4 revisions)
- Hardware Exploration of Shared-Exponent MiniFloats (M) (4 revisions)
- In-ear EEG signal acquisition (4 revisions)
- CPS Software-Configurable State-Machine (4 revisions)
- Theory, Algorithms, and Hardware for Beyond 5G (4 revisions)
- ASIC Design of a Sigma Point Processor (4 revisions)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (4 revisions)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (4 revisions)
- Smart e-glasses for concealed recording of EEG signals (4 revisions)
- Accelerating Applications Relying on Matrix-Vector-Product-Like Operations (4 revisions)
- Power Optimization in Multipliers (4 revisions)
- Low-power chip-to-chip communication network (4 revisions)
- Final Report (4 revisions)
- High performance continous-time Delta-Sigma ADC for biomedical applications (4 revisions)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (4 revisions - redirect page)
- Forward error-correction ASIC using GRAND (4 revisions)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (4 revisions)
- Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets (4 revisions)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (4 revisions)
- Adding Linux Support to our DMA engine (1-2S/B) (4 revisions - redirect page)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3 (4 revisions)
- Eye movements (4 revisions)
- Palm size chip NMR (4 revisions)
- Implementation of an AES Hardware Processing Engine (B/S) (4 revisions)
- Telecommunications (4 revisions)
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM (4 revisions)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) (4 revisions)
- NAND Flash Open Research Platform (4 revisions)
- Ultra-low power sampling front-end for acquisition of physiological signals (4 revisions)
- Finite element modeling of electrochemical random access memory (4 revisions)
- Ultrasound High Speed Microbubble Tracking (4 revisions)
- EEG artifact detection with machine learning (4 revisions)
- Stefan Lippuner (4 revisions)
- Advanced Data Movers for Modern Neural Networks (4 revisions)
- Virtual Memory Ara (4 revisions)
- Efficient TNN compression (4 revisions)
- Jammer-Resilient Synchronization for Wireless Communications (4 revisions)
- SSR combined with FREP in LLVM/Clang (M/1-3S) (4 revisions - redirect page)
- Sub-Noise Floor Channel Tracking (4 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core (4 revisions)
- Pascal Hager (4 revisions)
- Build the Fastest 2G Modem Ever (3 revisions)
- DaCe on Snitch (M/1-3S) (3 revisions - redirect page)
- Ambient RF Energy harvesting for Wireless Sensor Network (3 revisions)
- Jammer Mitigation Meets Machine Learning (3 revisions)
- Channel Decoding for TD-HSPA (3 revisions)
- Matthias Korb (3 revisions)
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection (3 revisions)
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications (3 revisions)
- Receiver design for the DigRF 4G high speed serial link (3 revisions)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (3 revisions)
- Towards The Integration of E-skin into Prosthetic Devices (3 revisions)
- Simulation of Negative Capacitance Ferroelectric Transistor (3 revisions)
- Infrared Wake Up Radio (3 revisions)
- Extended Verification for Ara (3 revisions)
- Mattia (3 revisions)
- Implementing A Low-Power Sensor Node Network (3 revisions)
- (M): A Flexible Peripheral System for High-Performance Systems on Chip (3 revisions)
- Neural Recording Interface and Spike Sorting Algorithm (3 revisions)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (3 revisions)
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations (3 revisions)
- Radiation Testing Board (3 revisions - redirect page)
- Developing a small portable neutron detector for detecting smuggled nuclear material (3 revisions)
- Integrated Devices, Electronics, And Systems (3 revisions)
- Successive Approximation Register (SAR) ADC (3 revisions)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) (3 revisions)
- NeuroSoC RISC-V Component (M/1-2S) (3 revisions)
- Improving datarate and efficiency of ultra low power wearable ultrasound (3 revisions)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M) (3 revisions)
- Running Rust on PULP (3 revisions)
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels (3 revisions)
- MemPool on HERO (3 revisions)
- Enabling Standalone Operation for a Mobile Health Platform (3 revisions)
- RedCap-5G for IOT application on prototype taped-out silicon (3 revisions)
- Bluetooth Low Energy network with optimized data throughput (3 revisions)
- Serverless Benchmarks on RISC-V (M) (3 revisions)
- 3D Matrix Multiplication Unit for ITA (1S) (3 revisions)
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX (3 revisions)
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications (3 revisions)
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (3 revisions)
- Multi issue OoO Ariane Backend (3 revisions - redirect page)
- Turbo Decoder Design for High Code Rates (3 revisions)
- Channel Estimation for TD-HSPA (3 revisions)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) (3 revisions)
- Digitally-Controlled Analog Subtractive Sound Synthesis (3 revisions)
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) (3 revisions)
- Unconventional phase change memory device concepts for in-memory and neuromorphic computin (3 revisions)
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras (3 revisions)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development (3 revisions)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S) (3 revisions)
- Glitches Reduce Listening Time of Your iPod (3 revisions)
- Thermal Control of Mobile Devices (3 revisions)
- Watchdog Timer for PULP (3 revisions)
- An Industrial-grade Bluetooth LE Mesh Network Solution (3 revisions)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning (3 revisions)
- Towards Formal Verification of the iDMA Engine (1-3S/B) (3 revisions)
- EECIS (3 revisions)
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC (3 revisions)
- Bringing XNOR-nets (ConvNets) to Silicon (3 revisions)
- Taping a Safer Silicon Implementation of Snitch (M/2-3S) (3 revisions)
- NextGenChannelDec (3 revisions)
- Design and implementation of the front-end for a portable ionizing radiation detector (3 revisions)
- Aliasing-Free Wavetable Music Synthesizer (3 revisions)
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration (3 revisions)
- Design of a D-Band Variable Gain Amplifier for 6G Communication (3 revisions)
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip (3 revisions)
- Integrating Hardware Accelerators into Snitch (1S) (3 revisions)
- Low-power time synchronization for IoT applications (3 revisions)
- Michael Muehlberghuber (3 revisions)
- EEG-based drowsiness detection (3 revisions)
- Interference Cancellation for the cellular Internet of Things (3 revisions)
- Standard Cell Compatible Memory Array Design (3 revisions)
- 3D Ultrasound Bubble Tracking (3 revisions)
- Investigation of the source starvation effect in III-V MOSFET (3 revisions)
- Development of a syringe label reader for the neurocritical care unit (3 revisions)
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors (3 revisions)
- Softmax for Transformers (M/1-2S) (3 revisions)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems (3 revisions)
- Bandwidth Efficient NEureka (3 revisions)
- LightProbe - Design of a High-Speed Optical Link (3 revisions)
- Signal to Noise Ratio Estimation for 3G standards (3 revisions)
- Machine Learning Assisted Direct Synthesis of Passive Networks (3 revisions)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers (3 revisions)
- Efficient TNN Inference on PULP Systems (3 revisions)
- Study and Development of Intelligent Capability for Small-Size UAVs (3 revisions)
- Digital Control of a DC/DC Buck Converter (3 revisions)
- Low Power Embedded Systems (3 revisions)
- Software (3 revisions)
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation (3 revisions)
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs) (3 revisions)
- Design of MEMs Sensor Interface (3 revisions)
- Audio DAC Conversion Jitter Measurement System (3 revisions)
- High-throughput Embedded System For Neurotechnology in collaboration with INI (3 revisions)
- Embedded Gesture Recognition Using Novel Mini Radar Sensors (3 revisions)
- Low Power Embedded Systems and Wireless Sensors Networks (3 revisions)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) (3 revisions)
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors (3 revisions)
- XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory (2 revisions)
- Simulation of Li-ion batteries and comparison with experimental data (2 revisions)
- Transformer Deployment on Heterogeneous Many-Core Systems (2 revisions)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (2 revisions)
- High Performance Cellular Receivers in Very Advanced CMOS (2 revisions)
- Implementation of a 2-D model for Li-ion batteries (2 revisions)
- Wearables for Sports and Life Enhancement (2 revisions)
- A Post-Simulation Trace-Based RISC-V GDB Debugging Server (2 revisions)
- Accelerators for object detection and tracking (2 revisions)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (2 revisions)
- An Efficient Compiler Backend for Snitch (1S/B) (2 revisions)
- Deep Unfolding of Iterative Optimization Algorithms (2 revisions)
- Autonomous Smart Sensors for IoT (2 revisions - redirect page)
- Reconfigurability of SHA-3 candidates (2 revisions)
- BirdGuard (2 revisions)
- Accurate deep learning inference using computational memory (2 revisions)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (2 revisions)
- Data Mapping for Unreliable Memories (2 revisions)
- High-Resolution, Calibrated Folding ADCs (2 revisions)
- Audio Visual Speech Recognition (1S/1M) (2 revisions)
- Kinetic Energy Harvesting For Autonomous Smart Watches (2 revisions)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) (2 revisions)
- Smart Patch For Heath Care And Rehabilitation (2 revisions)
- AXI-based Network on Chip (NoC) system (2 revisions)
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) (2 revisions)
- Christoph Leitner (2 revisions)
- Mixed Signal IC Design (2 revisions)
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings (2 revisions)
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon (2 revisions)
- Multi-Modal Environmental Sensing With GAP9 (1-2S) (2 revisions)
- Test project (2 revisions)
- Triple-Core PULPissimo (2 revisions)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (2 revisions - redirect page)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (2 revisions)
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP (2 revisions)
- Successive Interference Cancellation for 3G Downlink (2 revisions)
- A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks (2 revisions)
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (2 revisions)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B) (2 revisions)
- Ab-initio Simulation of Strained Thermoelectric Materials (2 revisions)
- Quantum Transport Modeling of Interband Cascade Lasers (ICL) (2 revisions)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M) (2 revisions)
- Low Precision Ara for ML (2 revisions)
- System on Chips for IoTs (2 revisions - redirect page)
- Optimal System Duty Cycling (2 revisions)
- Design of low mismatch DAC used for VAD (2 revisions)
- Adaptively Controlled Hysteresis Curve Tracer For Polymer Piezoelectrics (1 S/B) (2 revisions - redirect page)
- PREM Intervals and Loop Tiling (2 revisions)
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA (2 revisions)
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles (2 revisions)
- Analog Layout Engine (2 revisions)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (2 revisions)
- Low Resolution Neural Networks (2 revisions)
- Flexible Front-End Circuit for Biomedical Data Acquisition (2 revisions)
- RazorEDGE (2 revisions - redirect page)
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications (2 revisions)
- Wake Up Radio For Energy Efficient Communication System and IC Design (2 revisions)
- Network-off-Chip (M) (2 revisions)
- Design Review (2 revisions)
- Towards Flexible and Printable Wearables (2 revisions)
- High Throughput Turbo Decoder Design (2 revisions)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) (2 revisions)
- Research (2 revisions)
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) (2 revisions)
- Short Range Radars For Biomedical Application (2 revisions)
- Coding Guidelines (2 revisions)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) (2 revisions)
- Cryptography (2 revisions)
- Hardware Support for IDE in Multicore Environment (2 revisions)
- Design study of tunneling transistors based on a core/shell nanowire structures (2 revisions)
- Alias-Free Oscillator Synchronization for Arbitrary Waveforms (2 revisions)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S) (2 revisions)
- Norbert Felber (2 revisions)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M) (2 revisions)
- Network-on-Chip for coherent and non-coherent traffic (M) (2 revisions)
- A Flexible Peripheral System for High-Performance Systems on Chip (M) (2 revisions)
- On - Device Continual Learning for Seizure Detection on GAP9 (2 revisions)
- Ultrasound (2 revisions)
- Using Motion Sensors to Support Indoor Localization (2 revisions)
- Power Saver Mode for Cellular Internet of Things Receivers (2 revisions)
- Assessment of novel photovoltaic architectures by circuit simulation (2 revisions)
- Computation of Phonon Bandstructure in III-V Nanostructures (2 revisions)
- Weak-strong massive MIMO communication with low-resolution ADCs (2 revisions)
- Securing Block Ciphers against SCA and SIFA (2 revisions)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (2 revisions)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction (2 revisions)
- LightProbe - CNN-Based-Image-Reconstruction (2 revisions)
- Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs (2 revisions)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M) (2 revisions)
- Frank K. Gürkaynak (2 revisions)
- Herschmi (2 revisions)
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion (2 revisions)
- Integrating Hardware Accelerators into Snitch 1S (2 revisions - redirect page)
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC (2 revisions)
- Creating A Boundry Scan Generator (1-3S/B/2-3G) (2 revisions)
- Towards Self-Sustainable Unmanned Aerial Vehicles (2 revisions)
- Wireless Sensing With Long Range Comminication (LoRa) (2 revisions)
- RISC-V base ISA for ultra-low-area cores (2-3G) (2 revisions)
- Event-based navigation on autonomous nano-drones (2 revisions)
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision (2 revisions)
- Heterogeneous Acceleration Systems (2 revisions - redirect page)
- A Snitch-based Compute Accelerator for HERO (M/1-2S) (2 revisions)
- Prasadar (2 revisions)
- SSR combined with FREP in LLVM/Clang (2 revisions)
- Time Synchronization for 3G Mobile Communications (2 revisions)
- PULP Freertos with LLVM (2 revisions)
- Project Meetings (2 revisions)
- Neural Networks Framwork for Embedded Plattforms (2 revisions)
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance (2 revisions)
- Improving Cold-Start in Batteryless And Energy Harvesting Systems (2 revisions)
- DaCe on Snitch (2 revisions)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing (2 revisions)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy (2 revisions)
- VLSI Implementation Polar Decoder using High Level Synthesis (2 revisions)
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices (2 revisions)
- NORX - an AEAD algorithm for the CAESAR competition (2 revisions)
- Project Plan (2 revisions)
- Realtime Gaze Tracking on Siracusa (2 revisions)
- Neural Processing (2 revisions)
- High resolution, low power Sigma Delta ADC (2 revisions)
