Category:Semester Thesis
From iis-projects
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Semester thesis at the IIS is for 1-3 students for a duration of 14 weeks and should take 50% of the time of the students. The available projects in this category are meant primarily for a semester thesis. However if you are interested in the topic, you can discuss with the supervisor, in most cases the content of the project can be expanded to fit a master thesis as well.
Available Projects
- Model Complexity of Electromagnetic Systems
- Extending the HERO SDK to support asynchronous offloading (M/1-3S)
- Structural Health Monitoring (SHM) System (1-2S/M)
- Spectrometry for Environmental Monitoring (1-2S/M)
- Waterflow Monitoring with Doppler Ultrasound (1S)
- Sound-Based Vehicle Classification and Counting (1-2S)
- Multi-Modal Environmental Sensing With GAP9 (1-2S)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- On-Device Learnable Embeddings for Acoustic Environments
- Extreme-Edge Experience Replay for Keyword Spotting
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Low Precision Ara for ML
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- FPGA mapping of RPC DRAM
- GPT on the edge
- Modeling FlooNoC in GVSoC (S/M)
- Advanced Data Movers for Modern Neural Networks
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- EEG-based drowsiness detection
- In-ear EEG signal acquisition
- EEG earbud
- NeuroSoC RISC-V Component (M/1-2S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- Realtime Gaze Tracking on Siracusa
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- System Emulation for AR and VR devices
- Learning at the Edge with Hardware-Aware Algorithms
- Advanced EEG glasses
- Softmax for Transformers (M/1-2S)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Modular Distributed Data Collection Platform
- Cycle-Accurate Event-Based Simulation of Snitch Core
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- Object Detection and Tracking on the Edge
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Digital Control of a DC/DC Buck Converter
- Design of a D-Band Variable Gain Amplifier for 6G Communication
- Noise Figure Measurement for Cryogenic System
- Simulation of 2D artificial cilia metasurface in COMSOL
- An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
- Configurable Ultra Low Power LDO
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- BirdGuard
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Audio Visual Speech Separation and Recognition (1S/1M)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- Design of low mismatch DAC used for VAD
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Resource Partitioning of RPC DRAM
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- All the flavours of FFT on MemPool (1-2S/B)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Ultrasound image data recycler
- Extended Verification for Ara
- Design of combined Ultrasound and PPG systems
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- An Efficient Compiler Backend for Snitch (1S/B)
- PULP Freertos with LLVM
- Integration Of A Smart Vision System
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Event-based navigation on autonomous nano-drones
- Development of an implantable Force sensor for orthopedic applications
- Improving datarate and efficiency of ultra low power wearable ultrasound
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Battery indifferent wearable Ultrasound
- Wearable Ultrasound for Artery monitoring
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Improved Collision Avoidance for Nano-drones
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Ultra-wideband Concurrent Ranging
- Enhancing our DMA Engine with Fault Tolerance
- Visualization of Neural Architecture Search Spaces
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Non-blocking Algorithms in Real-Time Operating Systems
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Analog building blocks for mmWave manipulation
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- Bluetooth Low Energy network with optimized data throughput
- Fast Simulation of Manycore Systems (1S)
- Unconventional phase change memory device concepts for in-memory and neuromorphic computin
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Automatic unplugging detection for Ultrasound probes
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Huawei Research
- Securing Block Ciphers against SCA and SIFA
- RVfplib
- Short Range Radars For Biomedical Application
- Smart Patch For Heath Care And Rehabilitation
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- Machine Learning on Ultrasound Images
- IP-Based SoC Generation and Configuration (1-3S/B)
- PREM Runtime Scheduling Policies
- IBM Research
- BCI-controlled Drone
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Visualizing Functional Microbubbles using Ultrasound Imaging
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Extending the RISCV backend of LLVM to support PULP Extensions
- Compiler Profiling and Optimizing
- PREM Intervals and Loop Tiling
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Design and implementation of the front-end for a portable ionizing radiation detector
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- PREM on PULP
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Edge Computing for Long-Term Wearable Biomedical Systems
- AMZ Driverless Competition Embedded Systems Projects
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Wireless Sensing With Long Range Comminication (LoRa)
- Indoor Smart Tracking of Hospital instrumentation
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- Physics is looking for PULP
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- An Industrial-grade Bluetooth LE Mesh Network Solution
- BLISS - Battery-Less Identification System for Security
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- Zero Power Touch Sensor and Reciever For Body Communication
- Wake Up Radio For Energy Efficient Communication System and IC Design
- A Wireless Sensor Network for HPC monitoring
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Power Geolocalization And Indoor Localization
- Neural Networks Framwork for Embedded Plattforms
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Towards Online Training of CNNs: Hebbian-Based Deep Learning
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- 5G Cellular RF Front-end Design in 22nm CMOS Technology
- Development of a syringe label reader for the neurocritical care unit
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- OpenRISC SoC for Sensor Applications
- Design of Charge-Pump PLL in 22nm for 5G communication applications
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- PVT Dynamic Adaptation in PULPv3
- Linux Driver for fine-grain and low overhead access to on-chip performance counters
- Open Power-On Chip Controller Study and Integration
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Towards The Integration of E-skin into Prosthetic Devices
- Using Motion Sensors to Support Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomous Smart Watches: Hardware and Software Desing
- A Wireless Sensor Network for a Smart LED Lighting control
- Compressed Sensing vs JPEG
- Real-Time Pedestrian Detection For Privacy Enhancement
- Thermal Control of Mobile Devices
- Android reliability governor
- Infrared Wake Up Radio
- Ambient RF Energy harvesting for Wireless Sensor Network
- Hardware Support for IDE in Multicore Environment
- Audio DAC Conversion Jitter Measurement System
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
Active Projects
- On-Device Federated Continual Learning on Nano-Drone Swarms
- ASR-Waveformer
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Implementation of a Cache Reliability Mechanism (1S/M)
- On-Board Software for PULP on a Satellite
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Zephyr RTOS on PULP
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Physical Implementation of ITA (2S)
- 3D Matrix Multiplication Unit for ITA (1S)
- New RVV 1.0 Vector Instructions for Ara
- Big Data Analytics Benchmarks for Ara
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Radiation Testing of a PULP ASIC
- Ternary Neural Networks for Face Recognition
- Super Resolution Radar/Imaging at mm-Wave frequencies
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Efficient TNN compression
- Event-Driven Vision on an embedded platform
- ASIC Development of 5G-NR LDPC Decoder
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- Pulse Oximetry Fachpraktikum
Completed Projects
- Ultrasound Doppler system development
- Ultrasound-EMG combined hand gesture recognition
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Exploring NAS spaces with C-BRED
- Bandwidth Efficient NEureka
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Resource Partitioning of Caches
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Evaluating SoA Post-Training Quantization Algorithms
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Smart e-glasses for concealed recording of EEG signals
- Smart Meters
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Implementing Configurable Dual-Core Redundancy
- Running Rust on PULP
- Ultrasound based hand gesture recognition
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Bridging QuantLab with LPDNN
- Bluetooth Low Energy receiver in 65nm CMOS
- Precise Ultra-low-power Timer
- Novel Metastability Mitigation Technique
- Analog Compute-in-Memory Accelerator Interface and Integration
- Wearables in Fashion
- Outdoor Precision Object Tracking for Rockfall Experiments
- Autonomous Sensing For Trains In The IoT Era
- Flexfloat DL Training Framework
- Online Learning of User Features (1S)
- Feature Extraction for Speech Recognition (1S)
- SCMI Support for Power Controller Subsystem
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Implementing DSP Instructions in Banshee (1S)
- Efficient Synchronization of Manycore Systems (M/1S)
- Design of combined Ultrasound and Electromyography systems
- Designing a Power Management Unit for PULP SoCs
- PULP’s CLIC extensions for fast interrupt handling
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Triple-Core PULPissimo
- Watchdog Timer for PULP
- Hypervisor Extension for Ariane (M)
- Advanced 5G Repetition Combining
- Next Generation Synchronization Signals
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Low-power Temperature-insensitive Timer
- Improved State Estimation on PULP-based Nano-UAVs
- Ultra low power wearable ultrasound probe
- Machine Learning for extracting Muscle features using Ultrasound 2
- Hardware Constrained Neural Architechture Search
- Implementation of an AES Hardware Processing Engine (B/S)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Multi issue OoO Ariane Backend (M)
- Exploring schedules for incremental and annealing quantization algorithms
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Hyper-Dimensional Computing Based Predictive Maintenance
- Low Latency Brain-Machine Interfaces
- Ultrasound Low power WiFi with IMX7
- Ultrasound signal processing acceleration with CUDA
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Machine Learning for extracting Muscle features using Ultrasound
- Compression of Ultrasound data on FPGA
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Inductive Charging Circuit for Implantable Devices
- Ultra-low power transceiver for implantable devices
- Low-Dropout Regulators for Magnetic Resonance Imaging
- DC-DC Buck converter in 65nm CMOS
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- LLVM and DaCe for Snitch (1-2S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Manycore System on FPGA (M/S/G)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- Time Gain Compensation for Ultrasound Imaging
- Neural Networks Framwork for Embedded Plattforms
- Stand-Alone Edge Computing with GAP8
- Securing Block Ciphers against SCA and SIFA
- Design and Evaluation of a Small Size Avalanche Beacon
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- MemPool on HERO (1S)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- A Recurrent Neural Network Speech Recognition Chip
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- Deep Convolutional Autoencoder for iEEG Signals
- Ibex: FPGA Optimizations
- Ibex: Bit-Manipulation Extension
- Floating-Point Divide & Square Root Unit for Transprecision
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time ECG Contractions Classification
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- HERO: TLB Invalidation
- Indoor Positioning with Bluetooth
- Improving Resiliency of Hyperdimensional Computing
- Toward Superposition of Brain-Computer Interface Models
- Predictable Execution on GPU Caches
- Freedom from Interference in Heterogeneous COTS SoCs
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- Ultra-low power sampling front-end for acquisition of physiological signals
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Deep Learning for Brain-Computer Interface
- LightProbe - WIFI extension (PCB)
- Digital Audio Interface for Smart Intensive Computing Triggering
- Trace Debugger for custom RISC-V Core
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Shared Correlation Accelerator for an RF SoC
- IoT Turbo Decoder
- Development of a Rockfall Sensor Node
- Intelligent Power Management Unit (iPMU)
- Ultrafast Medical Ultrasound imaging on a GPU
- LightProbe - Implementation of compressed-sensing algorithms
- A Wireless Sensor Network for a Smart Building Monitor and Control
- Creating a HDMI Video Interface for PULP
- Standard Cell Compatible Memory Array Design
- Efficient NB-IoT Uplink Design
- Interference Cancellation for EC-GSM-IoT
- A Wireless Sensor Network for HPC monitoring
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards Autonomous Navigation for Nano-Blimps
- PULP-Shield for Autonomous UAV
- Self-Learning Drones based on Neural Networks
- BigPULP: Multicluster Synchronization Extensions
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
- Design of low-offset dynamic comparators
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Charging System for Implantable Electronics
- GUI-developement for an action-cam-based eye tracking device
- Ultra Low-Power Oscillator
- High-speed Scene Labeling on FPGA
- Learning Image Decompression with Convolutional Networks
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- Change-based Evaluation of Convolutional Neural Networks
- Implementing Hibernation on the ARM Cortex M0
- 3D Turbo Decoder ASIC Realization
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- Digital Transmitter for Mobile Communications
- Spatio-Temporal Video Filtering
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- FFT-based Convolutional Network Accelerator
- Real-Time Optical Flow Using Neural Networks
- Improving Scene Labeling with Hyperspectral Data
- Scattering Networks for Scene Labeling
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Design and Implementation of ultra low power vision system
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- Reconfigurability of SHA-3 candidates
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Ultra-low power processor design
Pages in category "Semester Thesis"
The following 27 pages are in this category, out of 524 total.
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A
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- A Recurrent Neural Network Speech Recognition Chip
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- A Wearable System To Control Phone And Electronic Device Without Hands
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for a Smart LED Lighting control
- A Wireless Sensor Network for HPC monitoring
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Accelerators for object detection and tracking
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced 5G Repetition Combining
- Advanced Data Movers for Modern Neural Networks
- Advanced EEG glasses