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- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration (20 revisions)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (20 revisions)
- Accelerator for Boosted Binary Features (20 revisions)
- Accelerator for Spatio-Temporal Video Filtering (20 revisions)
- FFT-based Convolutional Network Accelerator (19 revisions)
- Wireless Communication Systems for the IoT (19 revisions)
- Trace Debugger for custom RISC-V Core (19 revisions)
- PULP’s CLIC extensions for fast interrupt handling (19 revisions)
- 4th Generation Synchronization (19 revisions)
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE (18 revisions)
- Improving Scene Labeling with Hyperspectral Data (18 revisions)
- Flexfloat DL Training Framework (18 revisions)
- David J. Mack (18 revisions)
- Mapping Networks on Reconfigurable Binary Engine Accelerator (18 revisions)
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders (18 revisions)
- Baseband Meets CPU (17 revisions)
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs (17 revisions)
- Energy Efficient AXI Interface to Serial Link Physical Layer (17 revisions)
- Fast Accelerator Context Switch for PULP (17 revisions)
- Streaming Integer Extensions for Snitch (M) (17 revisions - redirect page)
- Energy Efficient Circuits and IoT Systems Group (17 revisions)
- Compressed Sensing vs JPEG (17 revisions)
- BLISS - Battery-Less Identification System for Security (17 revisions)
- A Snitch-based Compute Accelerator for HERO (17 revisions)
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (17 revisions)
- Heterogeneous SoCs (16 revisions)
- Optimal System Duty Cycling for a Mobile Health Platform (16 revisions)
- LightProbe (16 revisions)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S) (16 revisions)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications (16 revisions)
- 3D Turbo Decoder ASIC Realization (16 revisions)
- Rethinking our Convolutional Network Accelerator Architecture (16 revisions)
- Completed (15 revisions)
- Active-Set QP Solver on FPGA (15 revisions)
- Digital Transmitter for Mobile Communications (15 revisions)
- PULP-Shield for Autonomous UAV (15 revisions)
- Vector Processor for In-Memory Computing (15 revisions)
- Elliptic Curve Accelerator for zkSNARKs (15 revisions)
- Big Data Analytics Benchmarks for Ara (15 revisions)
- Digital Beamforming for Ultrasound Imaging (15 revisions)
- Advanced 5G Repetition Combining (15 revisions)
- DMA Streaming Co-processor (15 revisions)
- Design of an LTE Module for the Internet of Things (15 revisions)
- Application Specific Frequency Synthesizers (Analog/Digital PLLs) (14 revisions)
- Ultra low power wearable ultrasound probe (14 revisions)
- ASIC Design of a Gaussian Message Passing Processor (14 revisions)
- Beamspace processing for 5G mmWave massive MIMO on GPU (14 revisions)
- HW/SW Safety and Security (14 revisions)
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B) (14 revisions)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S) (14 revisions)
- Heroino: Design of the next CORE-V Microcontroller (14 revisions)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications (14 revisions)
- Finite Element Simulations of Transistors for Quantum Computing (14 revisions)
- High-speed Scene Labeling on FPGA (14 revisions)
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC (13 revisions)
- Efficient collective communications in FlooNoC (1M) (13 revisions)
- Deep Learning for Brain-Computer Interface (13 revisions)
- Towards global Brain-Computer Interfaces (13 revisions)
- CLIC for the CVA6 (13 revisions)
- Level Crossing ADC For a Many Channels Neural Recording Interface (13 revisions)
- Shared Correlation Accelerator for an RF SoC (13 revisions)
- Turbo Equalization for Cellular IoT (13 revisions)
- On-chip clock synthesizer design and porting (13 revisions)
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT (13 revisions)
- Integrated silicon photonic structures (13 revisions)
- LAPACK/BLAS for FPGA (13 revisions)
- GUI-developement for an action-cam-based eye tracking device (13 revisions)
- Online Learning of User Features (1S) (13 revisions)
- Cycle-Accurate Event-Based Simulation of Snitch Core (13 revisions)
- MatPHY: An Open-Source Physical Layer Development Framework (13 revisions)
- Gomeza old project1 (13 revisions)
- Acceleration and Transprecision (13 revisions)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (13 revisions)
- A Wireless Sensor Network for a Smart LED Lighting control (13 revisions)
- On-Board Software for PULP on a Satellite (13 revisions)
- Neural Recording Interface and Signal Processing (13 revisions)
- ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G (13 revisions)
- ASIC implementation of an interpolation-based wideband massive MIMO detector (12 revisions)
- Peak-to-average power Reduction (12 revisions)
- Sensor Fusion for Rockfall Sensor Node (12 revisions)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (12 revisions)
- Deep neural networks for seizure detection (12 revisions)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (12 revisions)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) (12 revisions)
- Investigation of Quantization Strategies for Retentive Networks (1S) (12 revisions)
- Digital Audio High Level Synthesis for FPGAs (12 revisions - redirect page)
- Scattering Networks for Scene Labeling (12 revisions)
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device (12 revisions)
- Stand-Alone Edge Computing with GAP8 (12 revisions)
- BigPULP: Multicluster Synchronization Extensions (12 revisions)
- Event-Driven Computing (12 revisions)
- Bridging QuantLab with LPDNN (12 revisions)
- Investigation of Redox Processes in CBRAM (12 revisions)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device (12 revisions)
- SmartRing (12 revisions)
- Ultrasound Doppler system development (12 revisions)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (12 revisions)
- Event-Driven Convolutional Neural Network Modular Accelerator (12 revisions)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture (12 revisions)
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex (12 revisions)
- PULPonFPGA: Hardware L2 Cache (12 revisions)
- Image and Video Processing (12 revisions)
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control (12 revisions)
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials (12 revisions)
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems (12 revisions)
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems (12 revisions)
- Spatio-Temporal Video Filtering (12 revisions)
- Advanced EEG glasses (11 revisions)
- Design of combined Ultrasound and Electromyography systems (11 revisions)
- Baseband Processor Development for 4G IoT (11 revisions)
- Evolved EDGE Physical Layer Incremental Redundancy Architecture (11 revisions)
- Channel Estimation and Equalization for LTE Advanced (11 revisions)
- Design of combined Ultrasound and PPG systems (11 revisions)
- Design and Implementation of a multi-mode multi-master I2C peripheral (11 revisions)
- Non-blocking Algorithms in Real-Time Operating Systems (11 revisions)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment (11 revisions)
- FPGA-Based Digital Frontend for 3G Receivers (11 revisions)
- Hardware Constrained Neural Architechture Search (11 revisions)
- LightProbe - WIFI extension (PCB) (11 revisions)
- Audio Visual Speech Separation and Recognition (1S/1M) (11 revisions)
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs) (11 revisions)
- Adaptively Controlled Hysteresis Curve Tracer For Polymer Ultrasonic Transducers (1 S/B) (11 revisions - redirect page)
- Energy-Efficient Brain-Inspired Hyperdimensional Computing (11 revisions)
- Real-time Linux on RISC-V (11 revisions)
- Towards Online Training of CNNs: Hebbian-Based Deep Learning (11 revisions)
- Interference Cancellation for EC-GSM-IoT (11 revisions)
- Self-Learning Drones based on Neural Networks (11 revisions)
- Design and Evaluation of a Small Size Avalanche Beacon (11 revisions)
- FPGA System Design for Computer Vision with Convolutional Neural Networks (11 revisions)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S) (11 revisions)
- Deep Learning-based Global Local Planner for Autonomous Nano-drones (11 revisions)
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications (11 revisions)
- Timing Channel Mitigations for RISC-V Cores (11 revisions)
- Pulse Oximetry Fachpraktikum (11 revisions)
- Minimum Variance Beamforming for Wearable Ultrasound Probes (11 revisions)
- FPGA acceleration of ultrasound computed tomography for in vivo tumor screening (11 revisions)
- Monocular Vision-based Object Following on Nano-size Robotic Blimp (11 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions (11 revisions)
- Hardware Acceleration (11 revisions)
- LightProbe - Implementation of compressed-sensing algorithms (10 revisions)
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools (10 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB (10 revisions)
- Radiation Testing of a PULP ASIC (10 revisions)
- Enabling Standalone Operation (10 revisions)
- Quest for the smallest Turing-complete core (2-3G) (10 revisions - redirect page)
- GSM Voice Capacity Evolution - VAMOS (10 revisions)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (10 revisions)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (10 revisions)
- A Wireless Sensor Network for HPC monitoring (10 revisions)
- Cell-Free mmWave Massive MIMO Communication (10 revisions)
- Time Gain Compensation for Ultrasound Imaging (10 revisions)
- Design of a VLIW processor architecture based on RISC-V (10 revisions)
- BigPULP: Shared Virtual Memory Multicluster Extensions (10 revisions)
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B) (10 revisions)
- Cell Measurements for the 5G Internet of Things (10 revisions)
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces (10 revisions)
- Wearable Ultrasound for Artery monitoring (10 revisions)
- Self-Supervised User Positioning in Cell-Free Massive MIMO Systems (10 revisions)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G) (10 revisions)
- Event-Driven Vision on an embedded platform (10 revisions)
- Design of Charge-Pump PLL in 22nm for 5G communication applications (10 revisions)
- Matteo Perotti (10 revisions)
- Gomeza old project3 (10 revisions)
- Ultrasound based hand gesture recognition (10 revisions)
- Implementation of an Accelerator for Retentive Networks (1-2S) (10 revisions)
- Open Source Basestation for Evolved EDGE (10 revisions - redirect page)
- Robert Balas (10 revisions)
- Machine Learning for extracting Muscle features using Ultrasound (10 revisions)
- Visualizing Functional Microbubbles using Ultrasound Imaging (10 revisions)
- All the flavours of FFT on MemPool (1-2S/B) (10 revisions)
- Wearables in Fashion (10 revisions)
- Machine Learning for extracting Muscle features using Ultrasound 2 (9 revisions)
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration (9 revisions)
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces (9 revisions)
- Karim Badawi (9 revisions)
- Feature Extraction for Speech Recognition (1S) (9 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory (9 revisions)
- Design and Implementation of an Approximate Floating Point Unit (9 revisions)
- Real-Time Pedestrian Detection For Privacy Enhancement (9 revisions)
- Knowledge Distillation for Embedded Machine Learning (9 revisions)
- Hyper-Dimensional Computing Based Predictive Maintenance (9 revisions)
- Efficient Implementation of an Active-Set QP Solver for FPGAs (9 revisions)
- Runtime partitioning of L1 memory in Mempool (M) (9 revisions)
- Deconvolution Accelerator for On-Chip Semi-Supervised Learning (9 revisions)
- HERO: TLB Invalidation (9 revisions)
- Hyper Meccano: Acceleration of Hyperdimensional Computing (9 revisions)
- Design of a 25 Gbps SerDes for optical chip-to-chip communication (9 revisions)
- Ultrasound-EMG combined hand gesture recognition (9 revisions)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (9 revisions)
- Practical Reconfigurable Intelligent Surfaces (RIS) (9 revisions)
- Integrating Hardware Accelerators into Snitch (9 revisions)
- Real-time View Synthesis using Image Domain Warping (9 revisions)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (9 revisions)
- Harald Kröll (9 revisions)
- OpenRISC SoC for Sensor Applications (9 revisions)
- Improved Reacquisition for the 5G Cellular IoT (9 revisions)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (9 revisions)
- Automatic unplugging detection for Ultrasound probes (9 revisions)
- Real-time eye movement analysis on a tablet computer (9 revisions)
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology (9 revisions)
- Michael Rogenmoser (9 revisions)
- DC-DC Buck converter in 65nm CMOS (9 revisions)
- Energy Efficient SoCs (9 revisions)
- Configurable Ultra Low Power LDO (9 revisions)
- Gomeza old project2 (9 revisions)
- Time and Frequency Synchronization in LTE Cat-0 Devices (9 revisions)
- Minimal Cost RISC-V core (9 revisions)
- A Multiview Synthesis Core in 65 nm CMOS (9 revisions)
- Improved State Estimation on PULP-based Nano-UAVs (9 revisions)
- Freedom from Interference in Heterogeneous COTS SoCs (9 revisions)
- Next Generation Synchronization Signals (9 revisions)
- Hardware Accelerated Derivative Pricing (9 revisions)
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging (9 revisions)
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication (9 revisions)
- Gomeza old project4 (9 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- Weekly Reports (8 revisions)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (8 revisions)
- Pirmin Vogel (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- A Unified Compute Kernel Library for Snitch (1-2S) (8 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (8 revisions)
- Learning at the Edge with Hardware-Aware Algorithms (8 revisions)
- Evaluating SoA Post-Training Quantization Algorithms (8 revisions)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications (8 revisions)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs (8 revisions)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 revisions)
- (M/1-2S): A Snitch-based Compute Accelerator for HERO (8 revisions - redirect page)
- PREM Runtime Scheduling Policies (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- Multi issue OoO Ariane Backend (M) (8 revisions)
- An FPGA-Based Evaluation Platform for Mobile Communications (8 revisions)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (8 revisions)
- Flexible Electronic Systems and Epidermal Devices (8 revisions - redirect page)
- Manycore System on FPGA (M/S/G) (8 revisions)
- Streaming Layer Normalization in ITA (M/1-2S) (8 revisions)
- Implementing Hibernation on the ARM Cortex M0 (8 revisions)
- Wireless EEG Acquisition and Processing (8 revisions)
- Evaluating the RiscV Architecture (8 revisions)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (8 revisions)
- SCMI Support for Power Controller Subsystem (8 revisions)
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC (8 revisions)
- BCI-controlled Drone (8 revisions)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) (8 revisions)
- Modular Distributed Data Collection Platform (8 revisions)
- Fast Wakeup From Deep Sleep State (8 revisions)
- Hypervisor Extension for Ariane (M) (8 revisions)
- Physical Implementation of ITA (2S) (8 revisions)
- Development of a fingertip blood pressure sensor (8 revisions)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (8 revisions)
- Linux Driver for fine-grain and low overhead access to on-chip performance counters (8 revisions)
- Deep Convolutional Autoencoder for iEEG Signals (8 revisions)
- OTDOA Positioning for LTE Cat-M (8 revisions)
- Hardware/software co-programming on the Parallella platform (8 revisions)
- Resource Partitioning of RPC DRAM (8 revisions)
- Fault-Tolerant Floating-Point Units (M) (8 revisions)
- ASIC Implementation of Jammer Mitigation (8 revisions)
- Object Detection and Tracking on the Edge (8 revisions)
- NVDLA meets PULP (8 revisions)
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format (8 revisions)
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications (8 revisions)
- A Trustworthy Three-Factor Authentication System (8 revisions)
- A computational memory unit using phase-change memory devices (8 revisions)
- Sandro Belfanti (8 revisions)
- Ultra Low-Power Oscillator (8 revisions)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 revisions)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- EEG earbud (7 revisions)
- Development of statistics and contention monitoring unit for PULP (7 revisions)
- Predictable Execution (7 revisions)
- Satellite Internet of Things (7 revisions)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S) (7 revisions)
- Gomeza old project5 (7 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (7 revisions)
- Charging System for Implantable Electronics (7 revisions)
- Outdoor Precision Object Tracking for Rockfall Experiments (7 revisions)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (7 revisions)
- Mauro Salomon (7 revisions)
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients (7 revisions)
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT (7 revisions)
- FFT HDL Code Generator for Multi-Antenna mmWave Communication (7 revisions)
- Spiking Neural Network for Autonomous Navigation (7 revisions)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (7 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (1M) (7 revisions)
- Bateryless Heart Rate Monitoring (7 revisions)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (7 revisions)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (7 revisions)
- Make Cellular Internet of Things Receivers Smart (7 revisions)
- Compressed Sensing for Wireless Biosignal Monitoring (7 revisions)
- Streaming Integer Extensions for Snitch (M/1-2S) (7 revisions)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (7 revisions)
- RazorEDGE: An Evolved EDGE DBB ASIC (7 revisions)
- Battery indifferent wearable Ultrasound (7 revisions)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (7 revisions)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (7 revisions)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities (7 revisions)
- Ibex: FPGA Optimizations (7 revisions)
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (7 revisions)
- Digital Audio Interface for Smart Intensive Computing Triggering (7 revisions)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (7 revisions)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (7 revisions)
- Development of a Rockfall Sensor Node (7 revisions)
- Indoor Positioning with Bluetooth (7 revisions)
- Efficient NB-IoT Uplink Design (7 revisions)
- Ultra-low power processor design (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (7 revisions)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (7 revisions)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (7 revisions)
- Efficient Search Design for Hyperdimensional Computing (7 revisions)
- Ultrasound Low power WiFi with IMX7 (7 revisions)
- LTE IoT Network Synchronization (7 revisions)
- EEG artifact detection for epilepsy monitoring (7 revisions)
- IoT Turbo Decoder (7 revisions)
- SW/HW Predictability and Security (7 revisions)
- Fault Tolerance (7 revisions)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (7 revisions)
- Characterization techniques for silicon photonics-Lumiphase (7 revisions)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver (7 revisions)
- Zephyr RTOS on PULP (7 revisions)
- RVfplib (7 revisions)
- Internet of Things Network Synchronizer (7 revisions)
- Transforming MemPool into a CGRA (M) (7 revisions)
- Development of an implantable Force sensor for orthopedic applications (7 revisions)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (7 revisions)
- Putting Together What Fits Together - GrÆStl (7 revisions)
- Autonomous Sensing For Trains In The IoT Era (7 revisions)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (7 revisions)
- Android Software Design (6 revisions)
- FPGA mapping of RPC DRAM (6 revisions)
- Moritz Schneider (6 revisions)
- Design of a Low Power Smart Sensing Multi-modal Vision Platform (6 revisions)
- Learning Image Decompression with Convolutional Networks (6 revisions)
- System Emulation for AR and VR devices (6 revisions)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (6 revisions)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) (6 revisions)
- Graph neural networks for epileptic seizure detection (6 revisions)
- Enabling Efficient Systolic Execution on MemPool (M) (6 revisions)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S) (6 revisions)
- LightProbe - Ultracompact Power Supply PCB (6 revisions)
- Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening (6 revisions)
- Channel Estimation for 3GPP TD-SCDMA (6 revisions)
- Implementing Configurable Dual-Core Redundancy (6 revisions)
- Autonomous Smart Watches: Hardware and Software Desing (6 revisions)
- Creating a HDMI Video Interface for PULP (6 revisions)
- New RVV 1.0 Vector Instructions for Ara (6 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache (6 revisions)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (6 revisions)
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets (6 revisions)
- MemPool on HERO (1S) (6 revisions)
- Implementing DSP Instructions in Banshee (1S) (6 revisions)
- CMOS power amplifier for field measurements in MRI systems (6 revisions)
- Ultra-Efficient Visual Classification on Movidius Myriad2 (6 revisions)
- Low-power Temperature-insensitive Timer (6 revisions)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (6 revisions)
- Switched Capacitor Based Bandgap-Reference (6 revisions)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (6 revisions)
- Bluetooth Low Energy receiver in 65nm CMOS (6 revisions)
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing (6 revisions)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich) (6 revisions)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA (6 revisions)
- Novel Metastability Mitigation Technique (6 revisions)
- Improved Collision Avoidance for Nano-drones (6 revisions)
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things (6 revisions)
- Floating-Point Divide & Square Root Unit for Transprecision (6 revisions)
- A Recurrent Neural Network Speech Recognition Chip (6 revisions)
- Beat Cadence (6 revisions)
- Exploring Algorithms for Early Seizure Detection (6 revisions)
- Compression of iEEG Data (6 revisions)
- Novel Methods for Jammer Mitigation (6 revisions)
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA (6 revisions)
- VLSI Design of an Asynchronous LDPC Decoder (6 revisions)
- FPGA Optimizations of Dense Binary Hyperdimensional Computing (6 revisions)
- Exploring NAS spaces with C-BRED (6 revisions)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (6 revisions)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M) (6 revisions)
- Writing a Hero runtime for EPAC (1-3S/B) (6 revisions)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (6 revisions)
- Next Generation Channel Decoder (6 revisions)
- Efficient Synchronization of Manycore Systems (M/1S) (6 revisions)
- Self Aware Epilepsy Monitoring (6 revisions)
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors (6 revisions)
- Towards Self Sustainable UAVs (6 revisions)
- VLSI Implementation of a 5G Ciphering Accelerator (6 revisions)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) (6 revisions)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (6 revisions)
- IBM Research–Zurich (6 revisions)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) (6 revisions)
- Change-based Evaluation of Convolutional Neural Networks (6 revisions)
- Ultrasound image data recycler (6 revisions)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (6 revisions)
- Internet of Things SoC Characterization (5 revisions)
- Noise Figure Measurement for Cryogenic System (5 revisions)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography (5 revisions)
- Ultra Low Power Conversion Circuit For Batteryless Applications (5 revisions)
- Toward Superposition of Brain-Computer Interface Models (5 revisions)
- Embedded Systems and autonomous UAVs (5 revisions)
- IP-Based SoC Generation and Configuration (1-3S/B) (5 revisions)
- LightProbe - Thermal-Power aware on-head Beamforming (5 revisions)
- Data Augmentation Techniques in Biosignal Classification (5 revisions)
- Ultra Low Power Wake Up Radio for Wireless Sensor Network (5 revisions)
- Predictable Execution on GPU Caches (5 revisions)
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration (5 revisions)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (5 revisions)
- Ultrasound signal processing acceleration with CUDA (5 revisions)
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor (5 revisions)
- Hardware Accelerator for Model Predictive Controller (5 revisions)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing (5 revisions)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf (5 revisions)
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring (5 revisions)
- Engineering For Kids (5 revisions)
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device (5 revisions)
- Towards Autonomous Navigation for Nano-Blimps (5 revisions)
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