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Showing below up to 500 results in range #101 to #600.

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  1. Heterogeneous Acceleration Systems‏‎ (2 revisions - redirect page)
  2. A Snitch-based Compute Accelerator for HERO (M/1-2S)‏‎ (2 revisions)
  3. Prasadar‏‎ (2 revisions)
  4. SSR combined with FREP in LLVM/Clang‏‎ (2 revisions)
  5. Time Synchronization for 3G Mobile Communications‏‎ (2 revisions)
  6. PULP Freertos with LLVM‏‎ (2 revisions)
  7. Project Meetings‏‎ (2 revisions)
  8. Neural Networks Framwork for Embedded Plattforms‏‎ (2 revisions)
  9. A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance‏‎ (2 revisions)
  10. Improving Cold-Start in Batteryless And Energy Harvesting Systems‏‎ (2 revisions)
  11. DaCe on Snitch‏‎ (2 revisions)
  12. Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing‏‎ (2 revisions)
  13. Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy‏‎ (2 revisions)
  14. VLSI Implementation Polar Decoder using High Level Synthesis‏‎ (2 revisions)
  15. Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices‏‎ (2 revisions)
  16. NORX - an AEAD algorithm for the CAESAR competition‏‎ (2 revisions)
  17. Project Plan‏‎ (2 revisions)
  18. Realtime Gaze Tracking on Siracusa‏‎ (2 revisions)
  19. Neural Processing‏‎ (2 revisions)
  20. High resolution, low power Sigma Delta ADC‏‎ (2 revisions)
  21. Build the Fastest 2G Modem Ever‏‎ (3 revisions)
  22. DaCe on Snitch (M/1-3S)‏‎ (3 revisions - redirect page)
  23. Ambient RF Energy harvesting for Wireless Sensor Network‏‎ (3 revisions)
  24. Jammer Mitigation Meets Machine Learning‏‎ (3 revisions)
  25. Channel Decoding for TD-HSPA‏‎ (3 revisions)
  26. Matthias Korb‏‎ (3 revisions)
  27. Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection‏‎ (3 revisions)
  28. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications‏‎ (3 revisions)
  29. Receiver design for the DigRF 4G high speed serial link‏‎ (3 revisions)
  30. Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)‏‎ (3 revisions)
  31. Towards The Integration of E-skin into Prosthetic Devices‏‎ (3 revisions)
  32. Simulation of Negative Capacitance Ferroelectric Transistor‏‎ (3 revisions)
  33. Infrared Wake Up Radio‏‎ (3 revisions)
  34. Extended Verification for Ara‏‎ (3 revisions)
  35. Mattia‏‎ (3 revisions)
  36. Implementing A Low-Power Sensor Node Network‏‎ (3 revisions)
  37. (M): A Flexible Peripheral System for High-Performance Systems on Chip‏‎ (3 revisions)
  38. Neural Recording Interface and Spike Sorting Algorithm‏‎ (3 revisions)
  39. Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)‏‎ (3 revisions)
  40. Efficient Banded Matrix Multiplication for Quantum Transport Simulations‏‎ (3 revisions)
  41. Radiation Testing Board‏‎ (3 revisions - redirect page)
  42. Developing a small portable neutron detector for detecting smuggled nuclear material‏‎ (3 revisions)
  43. Integrated Devices, Electronics, And Systems‏‎ (3 revisions)
  44. Successive Approximation Register (SAR) ADC‏‎ (3 revisions)
  45. Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)‏‎ (3 revisions)
  46. NeuroSoC RISC-V Component (M/1-2S)‏‎ (3 revisions)
  47. Improving datarate and efficiency of ultra low power wearable ultrasound‏‎ (3 revisions)
  48. Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)‏‎ (3 revisions)
  49. Running Rust on PULP‏‎ (3 revisions)
  50. Channel Estimation for 5G Cellular IoT and Fast Fading Channels‏‎ (3 revisions)
  51. MemPool on HERO‏‎ (3 revisions)
  52. Enabling Standalone Operation for a Mobile Health Platform‏‎ (3 revisions)
  53. RedCap-5G for IOT application on prototype taped-out silicon‏‎ (3 revisions)
  54. Bluetooth Low Energy network with optimized data throughput‏‎ (3 revisions)
  55. Serverless Benchmarks on RISC-V (M)‏‎ (3 revisions)
  56. 3D Matrix Multiplication Unit for ITA (1S)‏‎ (3 revisions)
  57. Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX‏‎ (3 revisions)
  58. Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications‏‎ (3 revisions)
  59. Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs‏‎ (3 revisions)
  60. Multi issue OoO Ariane Backend‏‎ (3 revisions - redirect page)
  61. Turbo Decoder Design for High Code Rates‏‎ (3 revisions)
  62. Channel Estimation for TD-HSPA‏‎ (3 revisions)
  63. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)‏‎ (3 revisions)
  64. Digitally-Controlled Analog Subtractive Sound Synthesis‏‎ (3 revisions)
  65. Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)‏‎ (3 revisions)
  66. Unconventional phase change memory device concepts for in-memory and neuromorphic computin‏‎ (3 revisions)
  67. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras‏‎ (3 revisions)
  68. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development‏‎ (3 revisions)
  69. Implementation of a Heterogeneous System for Image Processing on an FPGA (S)‏‎ (3 revisions)
  70. Glitches Reduce Listening Time of Your iPod‏‎ (3 revisions)
  71. Thermal Control of Mobile Devices‏‎ (3 revisions)
  72. Watchdog Timer for PULP‏‎ (3 revisions)
  73. An Industrial-grade Bluetooth LE Mesh Network Solution‏‎ (3 revisions)
  74. Autoencoder Accelerator for On-Chip Semi-Supervised Learning‏‎ (3 revisions)
  75. Towards Formal Verification of the iDMA Engine (1-3S/B)‏‎ (3 revisions)
  76. EECIS‏‎ (3 revisions)
  77. Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC‏‎ (3 revisions)
  78. Bringing XNOR-nets (ConvNets) to Silicon‏‎ (3 revisions)
  79. Taping a Safer Silicon Implementation of Snitch (M/2-3S)‏‎ (3 revisions)
  80. NextGenChannelDec‏‎ (3 revisions)
  81. Design and implementation of the front-end for a portable ionizing radiation detector‏‎ (3 revisions)
  82. Aliasing-Free Wavetable Music Synthesizer‏‎ (3 revisions)
  83. Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration‏‎ (3 revisions)
  84. Design of a D-Band Variable Gain Amplifier for 6G Communication‏‎ (3 revisions)
  85. Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip‏‎ (3 revisions)
  86. Integrating Hardware Accelerators into Snitch (1S)‏‎ (3 revisions)
  87. Low-power time synchronization for IoT applications‏‎ (3 revisions)
  88. Michael Muehlberghuber‏‎ (3 revisions)
  89. EEG-based drowsiness detection‏‎ (3 revisions)
  90. Interference Cancellation for the cellular Internet of Things‏‎ (3 revisions)
  91. Standard Cell Compatible Memory Array Design‏‎ (3 revisions)
  92. 3D Ultrasound Bubble Tracking‏‎ (3 revisions)
  93. Investigation of the source starvation effect in III-V MOSFET‏‎ (3 revisions)
  94. Development of a syringe label reader for the neurocritical care unit‏‎ (3 revisions)
  95. Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors‏‎ (3 revisions)
  96. Softmax for Transformers (M/1-2S)‏‎ (3 revisions)
  97. Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems‏‎ (3 revisions)
  98. Bandwidth Efficient NEureka‏‎ (3 revisions)
  99. LightProbe - Design of a High-Speed Optical Link‏‎ (3 revisions)
  100. Signal to Noise Ratio Estimation for 3G standards‏‎ (3 revisions)
  101. Machine Learning Assisted Direct Synthesis of Passive Networks‏‎ (3 revisions)
  102. Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers‏‎ (3 revisions)
  103. Efficient TNN Inference on PULP Systems‏‎ (3 revisions)
  104. Study and Development of Intelligent Capability for Small-Size UAVs‏‎ (3 revisions)
  105. Digital Control of a DC/DC Buck Converter‏‎ (3 revisions)
  106. Low Power Embedded Systems‏‎ (3 revisions)
  107. Software‏‎ (3 revisions)
  108. Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation‏‎ (3 revisions)
  109. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)‏‎ (3 revisions)
  110. Design of MEMs Sensor Interface‏‎ (3 revisions)
  111. Audio DAC Conversion Jitter Measurement System‏‎ (3 revisions)
  112. High-throughput Embedded System For Neurotechnology in collaboration with INI‏‎ (3 revisions)
  113. Embedded Gesture Recognition Using Novel Mini Radar Sensors‏‎ (3 revisions)
  114. Low Power Embedded Systems and Wireless Sensors Networks‏‎ (3 revisions)
  115. Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)‏‎ (3 revisions)
  116. Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors‏‎ (3 revisions)
  117. Improving Resiliency of Hyperdimensional Computing‏‎ (4 revisions)
  118. Every individual on the planet should have a real chance to obtain personalized medical therapy‏‎ (4 revisions)
  119. Stefan Mach‏‎ (4 revisions)
  120. IP-Based SoC Generation and Configuration (1-3S)‏‎ (4 revisions)
  121. Influence of the Initial Filament Geometry on the Forming Step in CBRAM.‏‎ (4 revisions)
  122. Energy Neutral Multi Sensors Wearable Device‏‎ (4 revisions)
  123. Autonomous Sensors For Underwater Monitoring In Smart Navy Systems‏‎ (4 revisions)
  124. Evaluating An Ultra low Power Vision Node‏‎ (4 revisions)
  125. Mixed-Precision Neural Networks for Brain-Computer Interface Applications‏‎ (4 revisions)
  126. Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)‏‎ (4 revisions)
  127. Edge Computing for Long-Term Wearable Biomedical Systems‏‎ (4 revisions)
  128. Android reliability governor‏‎ (4 revisions)
  129. Fabian Schuiki‏‎ (4 revisions)
  130. GPT on the edge‏‎ (4 revisions)
  131. AMZ Driverless Competition Embedded Systems Projects‏‎ (4 revisions)
  132. ASR-Waveformer‏‎ (4 revisions)
  133. AnalogInt‏‎ (4 revisions)
  134. Low Power Neural Network For Multi Sensors Wearable Devices‏‎ (4 revisions)
  135. Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks‏‎ (4 revisions)
  136. Routing 1000s of wires in Network-on-Chips (1-2S/M)‏‎ (4 revisions)
  137. Design of State Retentive Flip-Flops‏‎ (4 revisions)
  138. A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments‏‎ (4 revisions)
  139. DigitalUltrasoundHead‏‎ (4 revisions)
  140. Real-Time Motor-Imagery Classification Using Neuromorphic Processor‏‎ (4 revisions)
  141. Low-Power Time Synchronization for IoT Applications‏‎ (4 revisions)
  142. Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)‏‎ (4 revisions)
  143. Guillaume Mocquard‏‎ (4 revisions)
  144. Digital Transmitter for Cellular IoT‏‎ (4 revisions)
  145. Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication‏‎ (4 revisions)
  146. Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)‏‎ (4 revisions)
  147. Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node‏‎ (4 revisions)
  148. Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator‏‎ (4 revisions)
  149. Design of low-offset dynamic comparators‏‎ (4 revisions)
  150. Non-binary LDPC Decoder for Deep-Space Optical Communications‏‎ (4 revisions)
  151. VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM‏‎ (4 revisions)
  152. Near-Memory Training of Neural Networks‏‎ (4 revisions)
  153. Intelligent Power Management Unit (iPMU)‏‎ (4 revisions)
  154. Positioning for the cellular Internet of Things‏‎ (4 revisions)
  155. Improving our Smart Camera System‏‎ (4 revisions)
  156. Ibex: Bit-Manipulation Extension‏‎ (4 revisions)
  157. Variability Tolerant Ultra Low Power Cluster‏‎ (4 revisions)
  158. An FPGA-Based Testbed for 3G Mobile Communications Receivers‏‎ (4 revisions)
  159. Enhancing our DMA Engine with Fault Tolerance‏‎ (4 revisions)
  160. Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning‏‎ (4 revisions)
  161. Super Resolution Radar/Imaging at mm-Wave frequencies‏‎ (4 revisions)
  162. Wireless Biomedical Signal Acquisition Device‏‎ (4 revisions)
  163. FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications‏‎ (4 revisions)
  164. Spiking Neural Network for Motor Function Decoding Based on Neural Dust‏‎ (4 revisions)
  165. Hardware Exploration of Shared-Exponent MiniFloats (M)‏‎ (4 revisions)
  166. In-ear EEG signal acquisition‏‎ (4 revisions)
  167. CPS Software-Configurable State-Machine‏‎ (4 revisions)
  168. Theory, Algorithms, and Hardware for Beyond 5G‏‎ (4 revisions)
  169. ASIC Design of a Sigma Point Processor‏‎ (4 revisions)
  170. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications‏‎ (4 revisions)
  171. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)‏‎ (4 revisions)
  172. Smart e-glasses for concealed recording of EEG signals‏‎ (4 revisions)
  173. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations‏‎ (4 revisions)
  174. Power Optimization in Multipliers‏‎ (4 revisions)
  175. Low-power chip-to-chip communication network‏‎ (4 revisions)
  176. Final Report‏‎ (4 revisions)
  177. High performance continous-time Delta-Sigma ADC for biomedical applications‏‎ (4 revisions)
  178. Coherence-Capable Write-Back L1 Data Cache for Ariane‏‎ (4 revisions - redirect page)
  179. Forward error-correction ASIC using GRAND‏‎ (4 revisions)
  180. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)‏‎ (4 revisions)
  181. Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets‏‎ (4 revisions)
  182. Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)‏‎ (4 revisions)
  183. Adding Linux Support to our DMA engine (1-2S/B)‏‎ (4 revisions - redirect page)
  184. SHAre - An application Specific Instruction Set Processor for SHA-2/3‏‎ (4 revisions)
  185. Eye movements‏‎ (4 revisions)
  186. Palm size chip NMR‏‎ (4 revisions)
  187. Implementation of an AES Hardware Processing Engine (B/S)‏‎ (4 revisions)
  188. Telecommunications‏‎ (4 revisions)
  189. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM‏‎ (4 revisions)
  190. Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S)‏‎ (4 revisions)
  191. NAND Flash Open Research Platform‏‎ (4 revisions)
  192. Ultra-low power sampling front-end for acquisition of physiological signals‏‎ (4 revisions)
  193. Finite element modeling of electrochemical random access memory‏‎ (4 revisions)
  194. Ultrasound High Speed Microbubble Tracking‏‎ (4 revisions)
  195. EEG artifact detection with machine learning‏‎ (4 revisions)
  196. Stefan Lippuner‏‎ (4 revisions)
  197. Advanced Data Movers for Modern Neural Networks‏‎ (4 revisions)
  198. Virtual Memory Ara‏‎ (4 revisions)
  199. Efficient TNN compression‏‎ (4 revisions)
  200. Jammer-Resilient Synchronization for Wireless Communications‏‎ (4 revisions)
  201. SSR combined with FREP in LLVM/Clang (M/1-3S)‏‎ (4 revisions - redirect page)
  202. Sub-Noise Floor Channel Tracking‏‎ (4 revisions)
  203. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core‏‎ (4 revisions)
  204. Pascal Hager‏‎ (4 revisions)
  205. RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB‏‎ (5 revisions)
  206. Internet of Things SoC Characterization‏‎ (5 revisions)
  207. Ternary Neural Networks for Face Recognition‏‎ (5 revisions)
  208. A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography‏‎ (5 revisions)
  209. Precise Ultra-low-power Timer‏‎ (5 revisions)
  210. Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S)‏‎ (5 revisions)
  211. Embedded Systems and autonomous UAVs‏‎ (5 revisions)
  212. LightProbe - Thermal-Power aware on-head Beamforming‏‎ (5 revisions)
  213. Data Augmentation Techniques in Biosignal Classification‏‎ (5 revisions)
  214. IP-Based SoC Generation and Configuration (1-3S/B)‏‎ (5 revisions)
  215. Predict eye movement through brain activity‏‎ (5 revisions)
  216. Subject specific embeddings for transfer learning in brain-computer interfaces‏‎ (5 revisions)
  217. Design of a Prototype Chip with Interleaved Memory and Network-on-Chip‏‎ (5 revisions)
  218. Hardware Accelerator for Model Predictive Controller‏‎ (5 revisions)
  219. Noise Figure Measurement for Cryogenic System‏‎ (5 revisions)
  220. An Energy Efficient Brain-Computer Interface using Mr.Wolf‏‎ (5 revisions)
  221. Engineering For Kids‏‎ (5 revisions)
  222. Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device‏‎ (5 revisions)
  223. Toward Superposition of Brain-Computer Interface Models‏‎ (5 revisions)
  224. Ultra Low Power Conversion Circuit For Batteryless Applications‏‎ (5 revisions)
  225. Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor‏‎ (5 revisions)
  226. ASIC Design Projects‏‎ (5 revisions)
  227. A Wearable System To Control Phone And Electronic Device Without Hands‏‎ (5 revisions)
  228. Predictable Execution on GPU Caches‏‎ (5 revisions)
  229. Federico Villani‏‎ (5 revisions)
  230. Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration‏‎ (5 revisions)
  231. Ultra Low Power Wake Up Radio for Wireless Sensor Network‏‎ (5 revisions)
  232. Design and Implementation of ultra low power vision system‏‎ (5 revisions)
  233. Ultrasound signal processing acceleration with CUDA‏‎ (5 revisions)
  234. Fast Simulation of Manycore Systems (1S)‏‎ (5 revisions)
  235. WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing‏‎ (5 revisions)
  236. Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring‏‎ (5 revisions)
  237. Low-power Clock Generation Solutions for 65nm Technology‏‎ (5 revisions)
  238. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)‏‎ (5 revisions)
  239. Towards Autonomous Navigation for Nano-Blimps‏‎ (5 revisions)
  240. On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)‏‎ (5 revisions)
  241. Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea‏‎ (5 revisions)
  242. TCNs vs. LSTMs for Embedded Platforms‏‎ (5 revisions)
  243. Compression of Ultrasound data on FPGA‏‎ (5 revisions)
  244. High-Speed SAR ADC for next generation wireless communication in 12nm FinFET‏‎ (5 revisions)
  245. Electrothermal characterization of van der Waals Heterostructures with a partial overlap‏‎ (5 revisions)
  246. Final Presentation‏‎ (5 revisions)
  247. Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path‏‎ (5 revisions)
  248. Ultrafast Medical Ultrasound imaging on a GPU‏‎ (5 revisions)
  249. Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)‏‎ (5 revisions)
  250. Universal Stream Semantic Registers for Snitch (1S)‏‎ (5 revisions - redirect page)
  251. Phase-change memory devices for emerging computing paradigms‏‎ (5 revisions)
  252. Artificial Reverberation for Embedded Systems‏‎ (5 revisions)
  253. High-Throughput Authenticated Encryption Architectures based on Block Ciphers‏‎ (5 revisions)
  254. LLVM and DaCe for Snitch (1-2S)‏‎ (5 revisions)
  255. Channel Shortening Prefilter‏‎ (5 revisions - redirect page)
  256. Snitch meets iCE40 (1-2S/B)‏‎ (5 revisions - redirect page)
  257. Counter-based Fast Power Estimation using FPGAs (M/1-3S)‏‎ (5 revisions)
  258. Implementation of a NB-IoT Positioning System‏‎ (5 revisions)
  259. Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces‏‎ (5 revisions)
  260. Adding Linux Support to our DMA Engine (1-2S/B)‏‎ (5 revisions)
  261. Indoor Smart Tracking of Hospital instrumentation‏‎ (5 revisions)
  262. Beat DigRF‏‎ (5 revisions)
  263. A Wireless Sensor Network for a Smart Building Monitor and Control‏‎ (5 revisions)
  264. Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC‏‎ (5 revisions)
  265. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)‏‎ (5 revisions)
  266. IBM A2O Core‏‎ (5 revisions)
  267. Designing a Power Management Unit for PULP SoCs‏‎ (5 revisions)
  268. Inductive Charging Circuit for Implantable Devices‏‎ (5 revisions)
  269. Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control‏‎ (5 revisions)
  270. Image Sensor Interface and Pre-processing‏‎ (5 revisions)
  271. An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications‏‎ (5 revisions)
  272. Embedded Artificial Intelligence:Systems And Applications‏‎ (5 revisions)
  273. Low Latency Brain-Machine Interfaces‏‎ (5 revisions)
  274. Hardware/software codesign neural decoding algorithm for “neural dust”‏‎ (5 revisions)
  275. Resource Partitioning of Caches‏‎ (5 revisions)
  276. FPGA Testbed Implementation for Bluetooth Indoor Positioning‏‎ (5 revisions)
  277. State-Saving @ NXP‏‎ (5 revisions)
  278. Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)‏‎ (5 revisions)
  279. Low-Complexity MIMO Detection‏‎ (5 revisions)
  280. Design of a Fused Multiply Add Floating Point Unit‏‎ (5 revisions)
  281. Development of an efficient algorithm for quantum transport codes‏‎ (5 revisions)
  282. Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams‏‎ (5 revisions)
  283. Eye tracking‏‎ (5 revisions)
  284. Open Power-On Chip Controller Study and Integration‏‎ (5 revisions)
  285. Andreas Kurth‏‎ (5 revisions)
  286. LightProbe - Frontend Firmware and Control Side Channel‏‎ (5 revisions)
  287. Simulation of 2D artificial cilia metasurface in COMSOL‏‎ (5 revisions)
  288. Machine Learning for extracting Muscle features from Ultrasound raw data‏‎ (5 revisions)
  289. 5G Cellular RF Front-end Design in 22nm CMOS Technology‏‎ (5 revisions)
  290. Ultra-low power transceiver for implantable devices‏‎ (5 revisions)
  291. Learning Image Compression with Convolutional Networks‏‎ (5 revisions)
  292. Software-Defined Paging in the Snitch Cluster (2-3S)‏‎ (5 revisions)
  293. Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)‏‎ (5 revisions)
  294. Android Software Design‏‎ (6 revisions)
  295. FPGA mapping of RPC DRAM‏‎ (6 revisions)
  296. VLSI Implementation of a 5G Ciphering Accelerator‏‎ (6 revisions)
  297. Design of a Low Power Smart Sensing Multi-modal Vision Platform‏‎ (6 revisions)
  298. Learning Image Decompression with Convolutional Networks‏‎ (6 revisions)
  299. Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)‏‎ (6 revisions)
  300. Moritz Schneider‏‎ (6 revisions)
  301. Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)‏‎ (6 revisions)
  302. Graph neural networks for epileptic seizure detection‏‎ (6 revisions)
  303. Enabling Efficient Systolic Execution on MemPool (M)‏‎ (6 revisions)
  304. Ultrasound image data recycler‏‎ (6 revisions)
  305. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)‏‎ (6 revisions)
  306. LightProbe - Ultracompact Power Supply PCB‏‎ (6 revisions)
  307. Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening‏‎ (6 revisions)
  308. Channel Estimation for 3GPP TD-SCDMA‏‎ (6 revisions)
  309. Implementing Configurable Dual-Core Redundancy‏‎ (6 revisions)
  310. Autonomous Smart Watches: Hardware and Software Desing‏‎ (6 revisions)
  311. Creating a HDMI Video Interface for PULP‏‎ (6 revisions)
  312. System Emulation for AR and VR devices‏‎ (6 revisions)
  313. Implementation of a Heterogeneous System for Image Processing on an FPGA‏‎ (6 revisions)
  314. Implementing DSP Instructions in Banshee (1S)‏‎ (6 revisions)
  315. CMOS power amplifier for field measurements in MRI systems‏‎ (6 revisions)
  316. Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)‏‎ (6 revisions)
  317. MemPool on HERO (1S)‏‎ (6 revisions)
  318. Bluetooth Low Energy receiver in 65nm CMOS‏‎ (6 revisions)
  319. Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing‏‎ (6 revisions)
  320. New RVV 1.0 Vector Instructions for Ara‏‎ (6 revisions)
  321. Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets‏‎ (6 revisions)
  322. Low-power Temperature-insensitive Timer‏‎ (6 revisions)
  323. PULPonFPGA: Lightweight Virtual Memory Support - Software Cache‏‎ (6 revisions)
  324. Improved Collision Avoidance for Nano-drones‏‎ (6 revisions)
  325. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things‏‎ (6 revisions)
  326. Floating-Point Divide & Square Root Unit for Transprecision‏‎ (6 revisions)
  327. A Recurrent Neural Network Speech Recognition Chip‏‎ (6 revisions)
  328. Beat Cadence‏‎ (6 revisions)
  329. Exploring Algorithms for Early Seizure Detection‏‎ (6 revisions)
  330. Compression of iEEG Data‏‎ (6 revisions)
  331. Ultra-Efficient Visual Classification on Movidius Myriad2‏‎ (6 revisions)
  332. Switched Capacitor Based Bandgap-Reference‏‎ (6 revisions)
  333. Resilient Brain-Inspired Hyperdimensional Computing Architectures‏‎ (6 revisions)
  334. FPGA Optimizations of Dense Binary Hyperdimensional Computing‏‎ (6 revisions)
  335. Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)‏‎ (6 revisions)
  336. Exploring NAS spaces with C-BRED‏‎ (6 revisions)
  337. Multiuser Equalization and Detection for 3GPP TD-SCDMA‏‎ (6 revisions)
  338. Novel Metastability Mitigation Technique‏‎ (6 revisions)
  339. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms‏‎ (6 revisions)
  340. Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)‏‎ (6 revisions)
  341. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)‏‎ (6 revisions)
  342. Efficient Synchronization of Manycore Systems (M/1S)‏‎ (6 revisions)
  343. Novel Methods for Jammer Mitigation‏‎ (6 revisions)
  344. Synchronization and Power Control Concepts for 3GPP TD-SCDMA‏‎ (6 revisions)
  345. Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors‏‎ (6 revisions)
  346. VLSI Design of an Asynchronous LDPC Decoder‏‎ (6 revisions)
  347. Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)‏‎ (6 revisions)
  348. Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)‏‎ (6 revisions)
  349. Writing a Hero runtime for EPAC (1-3S/B)‏‎ (6 revisions)
  350. Next Generation Channel Decoder‏‎ (6 revisions)
  351. IBM Research–Zurich‏‎ (6 revisions)
  352. Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)‏‎ (6 revisions)
  353. Change-based Evaluation of Convolutional Neural Networks‏‎ (6 revisions)
  354. Self Aware Epilepsy Monitoring‏‎ (6 revisions)
  355. Towards Self Sustainable UAVs‏‎ (6 revisions)
  356. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs‏‎ (6 revisions)
  357. EEG earbud‏‎ (7 revisions)
  358. Development of statistics and contention monitoring unit for PULP‏‎ (7 revisions)
  359. SW/HW Predictability and Security‏‎ (7 revisions)
  360. Feature Extraction and Architecture Clustering for Keyword Spotting (1S)‏‎ (7 revisions)
  361. Sub Noise Floor Channel Estimation for the Cellular Internet of Things‏‎ (7 revisions)
  362. Gomeza old project5‏‎ (7 revisions)
  363. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core‏‎ (7 revisions)
  364. Charging System for Implantable Electronics‏‎ (7 revisions)
  365. Physical Layer Implementation of HSPA+ 4G Mobile Transceiver‏‎ (7 revisions)
  366. Zephyr RTOS on PULP‏‎ (7 revisions)
  367. RVfplib‏‎ (7 revisions)
  368. Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)‏‎ (7 revisions)
  369. Transforming MemPool into a CGRA (M)‏‎ (7 revisions)
  370. Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients‏‎ (7 revisions)
  371. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT‏‎ (7 revisions)
  372. Putting Together What Fits Together - GrÆStl‏‎ (7 revisions)
  373. FFT HDL Code Generator for Multi-Antenna mmWave Communication‏‎ (7 revisions)
  374. Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)‏‎ (7 revisions)
  375. System Analysis and VLSI Design of NB-IoT Baseband Processing‏‎ (7 revisions)
  376. Bateryless Heart Rate Monitoring‏‎ (7 revisions)
  377. ISA extensions in the Snitch Processor for Signal Processing (1M)‏‎ (7 revisions)
  378. Predictable Execution‏‎ (7 revisions)
  379. Satellite Internet of Things‏‎ (7 revisions)
  380. Mauro Salomon‏‎ (7 revisions)
  381. A RISC-V ISA Extension for Scalar Chaining in Snitch (M)‏‎ (7 revisions)
  382. Compressed Sensing for Wireless Biosignal Monitoring‏‎ (7 revisions)
  383. Outdoor Precision Object Tracking for Rockfall Experiments‏‎ (7 revisions)
  384. Spiking Neural Network for Autonomous Navigation‏‎ (7 revisions)
  385. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations‏‎ (7 revisions)
  386. Battery indifferent wearable Ultrasound‏‎ (7 revisions)
  387. Make Cellular Internet of Things Receivers Smart‏‎ (7 revisions)
  388. High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS‏‎ (7 revisions)
  389. A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities‏‎ (7 revisions)
  390. Streaming Integer Extensions for Snitch (M/1-2S)‏‎ (7 revisions)
  391. Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea‏‎ (7 revisions)
  392. Ibex: FPGA Optimizations‏‎ (7 revisions)
  393. Variable Bit Precision Logic for Deep Learning and Artificial Intelligence‏‎ (7 revisions)
  394. Digital Audio Interface for Smart Intensive Computing Triggering‏‎ (7 revisions)
  395. Memory Augmented Neural Networks in Brain-Computer Interfaces‏‎ (7 revisions)
  396. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)‏‎ (7 revisions)
  397. Indoor Positioning with Bluetooth‏‎ (7 revisions)
  398. Efficient NB-IoT Uplink Design‏‎ (7 revisions)
  399. RazorEDGE: An Evolved EDGE DBB ASIC‏‎ (7 revisions)
  400. Development of a Rockfall Sensor Node‏‎ (7 revisions)
  401. Digital Audio Processor for Cellular Applications‏‎ (7 revisions)
  402. Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications‏‎ (7 revisions)
  403. LightProbe - 200G Remote DMA for GPU FPGA Data Transfers‏‎ (7 revisions)
  404. Efficient Search Design for Hyperdimensional Computing‏‎ (7 revisions)
  405. Synchronisation and Cyclic Prefix Handling For LTE Testbed‏‎ (7 revisions)
  406. Ultra-low power processor design‏‎ (7 revisions)
  407. LTE IoT Network Synchronization‏‎ (7 revisions)
  408. EEG artifact detection for epilepsy monitoring‏‎ (7 revisions)
  409. Optimizing the Pipeline in our Floating Point Architectures (1S)‏‎ (7 revisions)
  410. IoT Turbo Decoder‏‎ (7 revisions)
  411. Fault Tolerance‏‎ (7 revisions)
  412. Characterization techniques for silicon photonics-Lumiphase‏‎ (7 revisions)
  413. Internet of Things Network Synchronizer‏‎ (7 revisions)
  414. Development of an implantable Force sensor for orthopedic applications‏‎ (7 revisions)
  415. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications‏‎ (7 revisions)
  416. Autonomous Sensing For Trains In The IoT Era‏‎ (7 revisions)
  417. Ultrasound Low power WiFi with IMX7‏‎ (7 revisions)
  418. Extend the RI5CY core with priviledge extensions‏‎ (8 revisions)
  419. NVDLA meets PULP‏‎ (8 revisions)
  420. Hardware Accelerator Integration into Embedded Linux‏‎ (8 revisions)
  421. Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications‏‎ (8 revisions)
  422. A Unified Compute Kernel Library for Snitch (1-2S)‏‎ (8 revisions)
  423. Audio Video Preprocessing In Parallel Ultra Low Power Platform‏‎ (8 revisions)
  424. Sandro Belfanti‏‎ (8 revisions)
  425. Low-Power Environmental Sensing‏‎ (8 revisions)
  426. Ultra Low-Power Oscillator‏‎ (8 revisions)
  427. Implementation of a Cache Reliability Mechanism (1S/M)‏‎ (8 revisions)
  428. Learning at the Edge with Hardware-Aware Algorithms‏‎ (8 revisions)
  429. Evaluating SoA Post-Training Quantization Algorithms‏‎ (8 revisions)
  430. Semi-Custom Digital VLSI for Processing-in-Memory‏‎ (8 revisions)
  431. Investigation of Metal Diffusion in Oxides for CBRAM Applications‏‎ (8 revisions)
  432. Machine Learning on Ultrasound Images‏‎ (8 revisions)
  433. Weekly Reports‏‎ (8 revisions)
  434. Analog Compute-in-Memory Accelerator Interface and Integration‏‎ (8 revisions)
  435. (M/1-2S): A Snitch-based Compute Accelerator for HERO‏‎ (8 revisions - redirect page)
  436. Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)‏‎ (8 revisions)
  437. Pirmin Vogel‏‎ (8 revisions)
  438. ISA extensions in the Snitch Processor for Signal Processing (M)‏‎ (8 revisions)
  439. An FPGA-Based Evaluation Platform for Mobile Communications‏‎ (8 revisions)
  440. PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker‏‎ (8 revisions)
  441. Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification‏‎ (8 revisions)
  442. Flexible Electronic Systems and Epidermal Devices‏‎ (8 revisions - redirect page)
  443. Implementing Hibernation on the ARM Cortex M0‏‎ (8 revisions)
  444. Evaluating the RiscV Architecture‏‎ (8 revisions)
  445. A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)‏‎ (8 revisions)
  446. Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs‏‎ (8 revisions)
  447. Manycore System on FPGA (M/S/G)‏‎ (8 revisions)
  448. Multi issue OoO Ariane Backend (M)‏‎ (8 revisions)
  449. PREM Runtime Scheduling Policies‏‎ (8 revisions)
  450. Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC‏‎ (8 revisions)
  451. BCI-controlled Drone‏‎ (8 revisions)
  452. Fast Wakeup From Deep Sleep State‏‎ (8 revisions)
  453. Streaming Layer Normalization in ITA (M/1-2S)‏‎ (8 revisions)
  454. Wireless EEG Acquisition and Processing‏‎ (8 revisions)
  455. Modular Distributed Data Collection Platform‏‎ (8 revisions)
  456. Hypervisor Extension for Ariane (M)‏‎ (8 revisions)
  457. Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)‏‎ (8 revisions)
  458. SCMI Support for Power Controller Subsystem‏‎ (8 revisions)
  459. Linux Driver for fine-grain and low overhead access to on-chip performance counters‏‎ (8 revisions)
  460. Deep Convolutional Autoencoder for iEEG Signals‏‎ (8 revisions)
  461. Development of a fingertip blood pressure sensor‏‎ (8 revisions)
  462. Hardware/software co-programming on the Parallella platform‏‎ (8 revisions)
  463. Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)‏‎ (8 revisions)
  464. Fault-Tolerant Floating-Point Units (M)‏‎ (8 revisions)
  465. ASIC Implementation of Jammer Mitigation‏‎ (8 revisions)
  466. Physical Implementation of ITA (2S)‏‎ (8 revisions)
  467. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format‏‎ (8 revisions)
  468. OTDOA Positioning for LTE Cat-M‏‎ (8 revisions)
  469. Resource Partitioning of RPC DRAM‏‎ (8 revisions)
  470. A Trustworthy Three-Factor Authentication System‏‎ (8 revisions)
  471. Object Detection and Tracking on the Edge‏‎ (8 revisions)
  472. A computational memory unit using phase-change memory devices‏‎ (8 revisions)
  473. Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)‏‎ (8 revisions)
  474. EvalEDGE: A 2G Cellular Transceiver FMC‏‎ (8 revisions)
  475. Next Generation Synchronization Signals‏‎ (9 revisions)
  476. Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration‏‎ (9 revisions)
  477. Machine Learning for extracting Muscle features using Ultrasound 2‏‎ (9 revisions)
  478. Karim Badawi‏‎ (9 revisions)
  479. Feature Extraction for Speech Recognition (1S)‏‎ (9 revisions)
  480. Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces‏‎ (9 revisions)
  481. Design and Implementation of an Approximate Floating Point Unit‏‎ (9 revisions)
  482. Knowledge Distillation for Embedded Machine Learning‏‎ (9 revisions)
  483. Hyper-Dimensional Computing Based Predictive Maintenance‏‎ (9 revisions)
  484. Efficient Implementation of an Active-Set QP Solver for FPGAs‏‎ (9 revisions)
  485. Deconvolution Accelerator for On-Chip Semi-Supervised Learning‏‎ (9 revisions)
  486. HERO: TLB Invalidation‏‎ (9 revisions)
  487. PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory‏‎ (9 revisions)
  488. Hyper Meccano: Acceleration of Hyperdimensional Computing‏‎ (9 revisions)
  489. Design of a 25 Gbps SerDes for optical chip-to-chip communication‏‎ (9 revisions)
  490. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)‏‎ (9 revisions)
  491. Real-Time Pedestrian Detection For Privacy Enhancement‏‎ (9 revisions)
  492. Runtime partitioning of L1 memory in Mempool (M)‏‎ (9 revisions)
  493. Integrating Hardware Accelerators into Snitch‏‎ (9 revisions)
  494. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)‏‎ (9 revisions)
  495. Harald Kröll‏‎ (9 revisions)
  496. Improved Reacquisition for the 5G Cellular IoT‏‎ (9 revisions)
  497. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)‏‎ (9 revisions)
  498. Automatic unplugging detection for Ultrasound probes‏‎ (9 revisions)
  499. LTE-Advanced RF Front-end Design in 28nm CMOS Technology‏‎ (9 revisions)
  500. Ultrasound-EMG combined hand gesture recognition‏‎ (9 revisions)

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