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Revision as of 11:08, 17 January 2014
| THIS PAGE IS CURRENTLY UNDER DEVELOPMENT |
In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.
Contents
Available Projects
Hot Projects
- Design of Streaming Data Platform for High-Speed ADC Data
- Implementation of an Accelerator for Retentive Networks (1-2S)
- Efficient collective communications in FlooNoC (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- EEG-based drowsiness detection
- In-ear EEG signal acquisition
- EEG earbud
- NeuroSoC RISC-V Component (M/1-2S)
- 3D Matrix Multiplication Unit for ITA (1S)
- Physical Implementation of ITA (2S)
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- Realtime Gaze Tracking on Siracusa
- System Emulation for AR and VR devices
- Learning at the Edge with Hardware-Aware Algorithms
- Advanced EEG glasses
- Softmax for Transformers (M/1-2S)
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Modular Distributed Data Collection Platform
- Object Detection and Tracking on the Edge
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations
- Charge and heat transport through graphene nanoribbon based devices
- Energy Efficient Serial Link
- Audio Visual Speech Separation and Recognition (1S/1M)
- Predict eye movement through brain activity
- Design of low mismatch DAC used for VAD
- Neural Recording Interface and Signal Processing
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Bandwidth Efficient NEureka
- Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Integration Of A Smart Vision System
- Event-based navigation on autonomous nano-drones
- Development of an implantable Force sensor for orthopedic applications
- Quantum Transport Modeling of Interband Cascade Lasers (ICL)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Exploring NAS spaces with C-BRED
- Improved Collision Avoidance for Nano-drones
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Fast Accelerator Context Switch for PULP
- Visualization of Neural Architecture Search Spaces
- Self Aware Epilepsy Monitoring
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Non-blocking Algorithms in Real-Time Operating Systems
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- Probing the limits of fake-quantised neural networks
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- EEG artifact detection with machine learning
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- EEG artifact detection for epilepsy monitoring
- Fast Simulation of Manycore Systems (1S)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Integrated silicon photonic structures-Lumiphase
- Characterization techniques for silicon photonics-Lumiphase
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Huawei Research
- Graph neural networks for epileptic seizure detection
- IBM Research
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Data Augmentation Techniques in Biosignal Classification
- Compression of iEEG Data
- BCI-controlled Drone
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Deep neural networks for seizure detection
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Phase-change memory devices for emerging computing paradigms
- Finite element modeling of electrochemical random access memory
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Quantum transport in 2D heterostructures
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Design and implementation of the front-end for a portable ionizing radiation detector
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Real-Time Implementation of Quantum State Identification using an FPGA
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Towards Online Training of CNNs: Hebbian-Based Deep Learning
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- Development of a syringe label reader for the neurocritical care unit
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Design of Charge-Pump PLL in 22nm for 5G communication applications
- PVT Dynamic Adaptation in PULPv3
- Linux Driver for fine-grain and low overhead access to on-chip performance counters
- Open Power-On Chip Controller Study and Integration
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Using Motion Sensors to Support Indoor Localization
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Development of an efficient algorithm for quantum transport codes
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Redox Processes in CBRAM
- Developing High Efficiency Batteries for Electric Cars
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
Digital Design
- Modeling FlooNoC in GVSoC (S/M)
- Advanced Data Movers for Modern Neural Networks
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Implementation of an Accelerator for Retentive Networks (1-2S)
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Fault-Tolerant Floating-Point Units (M)
- Efficient collective communications in FlooNoC (1M)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- EEG-based drowsiness detection
- In-ear EEG signal acquisition
- EEG earbud
- NeuroSoC RISC-V Component (M/1-2S)
- 3D Matrix Multiplication Unit for ITA (1S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Physical Implementation of ITA (2S)
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- Realtime Gaze Tracking on Siracusa
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- System Emulation for AR and VR devices
- Learning at the Edge with Hardware-Aware Algorithms
- RedCap-5G for IOT application on prototype taped-out silicon
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Advanced EEG glasses
- Softmax for Transformers (M/1-2S)
- Implementation of a Cache Reliability Mechanism (1S/M)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Modular Distributed Data Collection Platform
- Cycle-Accurate Event-Based Simulation of Snitch Core
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- Real-time Linux on RISC-V
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- On-Board Software for PULP on a Satellite
- Object Detection and Tracking on the Edge
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- BirdGuard
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Audio Visual Speech Separation and Recognition (1S/1M)
- Predict eye movement through brain activity
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Resource Partitioning of RPC DRAM
- Bandwidth Efficient NEureka
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- All the flavours of FFT on MemPool (1-2S/B)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Ultrasound image data recycler
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Extended Verification for Ara
- Design of combined Ultrasound and PPG systems
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- An Efficient Compiler Backend for Snitch (1S/B)
- PULP Freertos with LLVM
- Zephyr RTOS on PULP
- Integration Of A Smart Vision System
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Event-based navigation on autonomous nano-drones
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Improving datarate and efficiency of ultra low power wearable ultrasound
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Battery indifferent wearable Ultrasound
- Wearable Ultrasound for Artery monitoring
- Exploring NAS spaces with C-BRED
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Improved Collision Avoidance for Nano-drones
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Ultra-wideband Concurrent Ranging
- Enhancing our DMA Engine with Fault Tolerance
- Fast Accelerator Context Switch for PULP
- Visualization of Neural Architecture Search Spaces
- Self Aware Epilepsy Monitoring
- Serverless Benchmarks on RISC-V (M)
- Non-blocking Algorithms in Real-Time Operating Systems
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- Probing the limits of fake-quantised neural networks
- EEG artifact detection with machine learning
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- EEG artifact detection for epilepsy monitoring
- Fast Simulation of Manycore Systems (1S)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Automatic unplugging detection for Ultrasound probes
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Huawei Research
- Securing Block Ciphers against SCA and SIFA
- Graph neural networks for epileptic seizure detection
- RVfplib
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Short Range Radars For Biomedical Application
- Smart Patch For Heath Care And Rehabilitation
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Probabilistic training algorithms for quantized neural networks
- Machine Learning on Ultrasound Images
- IP-Based SoC Generation and Configuration (1-3S/B)
- Efficient Search Design for Hyperdimensional Computing
- PREM Runtime Scheduling Policies
- IBM Research
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
- Data Augmentation Techniques in Biosignal Classification
- Compression of iEEG Data
- BCI-controlled Drone
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor
- Accurate deep learning inference using computational memory
- Deep neural networks for seizure detection
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Visualizing Functional Microbubbles using Ultrasound Imaging
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Extending the RISCV backend of LLVM to support PULP Extensions
- Compiler Profiling and Optimizing
- PREM Intervals and Loop Tiling
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- PREM on PULP
- Edge Computing for Long-Term Wearable Biomedical Systems
- AMZ Driverless Competition Embedded Systems Projects
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Wireless Sensing With Long Range Comminication (LoRa)
- Indoor Smart Tracking of Hospital instrumentation
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- Physics is looking for PULP
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- An Industrial-grade Bluetooth LE Mesh Network Solution
- BLISS - Battery-Less Identification System for Security
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Zero Power Touch Sensor and Reciever For Body Communication
- Wake Up Radio For Energy Efficient Communication System and IC Design
- A Wireless Sensor Network for HPC monitoring
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Power Geolocalization And Indoor Localization
- Real-Time Implementation of Quantum State Identification using an FPGA
- Neural Networks Framwork for Embedded Plattforms
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Single-Bit-Synapse Spiking Neural System-on-Chip
- OpenRISC SoC for Sensor Applications
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- PVT Dynamic Adaptation in PULPv3
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Towards The Integration of E-skin into Prosthetic Devices
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Towards Self Sustainable UAVs
- Using Motion Sensors to Support Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Bateryless Heart Rate Monitoring
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Kinetic Energy Harvesting For Autonomous Smart Watches
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomous Smart Watches: Hardware and Software Desing
Analog Design
- Digital Control of a DC/DC Buck Converter
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- Analog building blocks for mmWave manipulation
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- Bluetooth Low Energy network with optimized data throughput
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- 5G Cellular RF Front-end Design in 22nm CMOS Technology
- Design of Charge-Pump PLL in 22nm for 5G communication applications
Nano Electronics
- Developing High Efficiency Batteries for Electric Cars
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
- Assessment of novel photovoltaic architectures by circuit simulation
Projects in Progress
Digital Design
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Low Precision Ara for ML
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Streaming Layer Normalization in ITA (M/1-2S)
- Ultrasound-EMG combined hand gesture recognition
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- On - Device Continual Learning for Seizure Detection on GAP9
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Big Data Analytics Benchmarks for Ara
- Radiation Testing of a PULP ASIC
- Virtual Memory Ara
- Runtime partitioning of L1 memory in Mempool (M)
- Ultrasound Doppler system development
- New RVV 1.0 Vector Instructions for Ara
- Ternary Neural Networks for Face Recognition
- ASIC Development of 5G-NR LDPC Decoder
- Efficient TNN compression
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Event-Driven Vision on an embedded platform
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
Completed Projects
Digital Design
- Network-off-Chip (M)
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Transformer Deployment on Heterogeneous Many-Core Systems
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Resource Partitioning of Caches
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Enabling Efficient Systolic Execution on MemPool (M)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Ultrasound based hand gesture recognition
- Development of statistics and contention monitoring unit for PULP
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Implementing Configurable Dual-Core Redundancy
- Running Rust on PULP
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Design of combined Ultrasound and Electromyography systems
- Bridging QuantLab with LPDNN
- Triple-Core PULPissimo
- Smart e-glasses for concealed recording of EEG signals
- PULP’s CLIC extensions for fast interrupt handling
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Wireless EEG Acquisition and Processing
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Watchdog Timer for PULP
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Designing a Power Management Unit for PULP SoCs
- SCMI Support for Power Controller Subsystem
- Streaming Integer Extensions for Snitch (M/1-2S)
- Implementing DSP Instructions in Banshee (1S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Flexfloat DL Training Framework
- CLIC for the CVA6
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Ultra low power wearable ultrasound probe
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Analog Compute-in-Memory Accelerator Interface and Integration
- Machine Learning for extracting Muscle features using Ultrasound 2
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Evaluating SoA Post-Training Quantization Algorithms
- Novel Metastability Mitigation Technique
- Ultrasound Low power WiFi with IMX7
- Ultrasound signal processing acceleration with CUDA
- Compression of Ultrasound data on FPGA
- Implementation of an AES Hardware Processing Engine (B/S)
- Securing Block Ciphers against SCA and SIFA
- Online Learning of User Features (1S)
- Wearables in Fashion
- LLVM and DaCe for Snitch (1-2S)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Transforming MemPool into a CGRA (M)
- Manycore System on FPGA (M/S/G)
- Bluetooth Low Energy receiver in 65nm CMOS
- Efficient Synchronization of Manycore Systems (M/1S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Hypervisor Extension for Ariane (M)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Exploring schedules for incremental and annealing quantization algorithms
- Low Latency Brain-Machine Interfaces
- ISA extensions in the Snitch Processor for Signal Processing (M)
- MemPool on HERO (1S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Multi issue OoO Ariane Backend (M)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Smart Meters
- Time Gain Compensation for Ultrasound Imaging
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Machine Learning for extracting Muscle features using Ultrasound
- Hardware Constrained Neural Architechture Search
- Hyper-Dimensional Computing Based Predictive Maintenance
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Improved State Estimation on PULP-based Nano-UAVs
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- TCNs vs. LSTMs for Embedded Platforms
- Exploring Algorithms for Early Seizure Detection
- Improving Resiliency of Hyperdimensional Computing
- Toward Superposition of Brain-Computer Interface Models
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- Next Generation Synchronization Signals
- Deep Convolutional Autoencoder for iEEG Signals
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- Floating-Point Divide & Square Root Unit for Transprecision
- Timing Channel Mitigations for RISC-V Cores
- NVDLA meets PULP
- Advanced 5G Repetition Combining
- Indoor Positioning with Bluetooth
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Outdoor Precision Object Tracking for Rockfall Experiments
- Design and Evaluation of a Small Size Avalanche Beacon
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Freedom from Interference in Heterogeneous COTS SoCs
- Predictable Execution on GPU Caches
- Digital Audio Interface for Smart Intensive Computing Triggering
- Real-Time ECG Contractions Classification
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Study and Development of Intelligent Capability for Small-Size UAVs
- Towards Autonomous Navigation for Nano-Blimps
- PULP-Shield for Autonomous UAV
- Self-Learning Drones based on Neural Networks
- HERO: TLB Invalidation
- Smart Virtual Memory Sharing
- Shared Correlation Accelerator for an RF SoC
- Interference Cancellation for EC-GSM-IoT
- Neural Networks Framwork for Embedded Plattforms
- A Wireless Sensor Network for HPC monitoring
- IoT Turbo Decoder
- BigPULP: Shared Virtual Memory Multicluster Extensions
- BigPULP: Multicluster Synchronization Extensions
- Creating a HDMI Video Interface for PULP
- LightProbe - WIFI extension (PCB)
- Trace Debugger for custom RISC-V Core
- Deep Learning for Brain-Computer Interface
- A computational memory unit using phase-change memory devices
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Autonomous Sensing For Trains In The IoT Era
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- LightProbe - Implementation of compressed-sensing algorithms
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Sensor Fusion for Rockfall Sensor Node
- Efficient NB-IoT Uplink Design
- Internet of Things SoC Characterization
- A Wireless Sensor Network for a Smart Building Monitor and Control
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- Internet of Things Network Synchronizer
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- A Recurrent Neural Network Speech Recognition Chip
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- Turbo Equalization for Cellular IoT
- Intelligent Power Management Unit (iPMU)
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Learning Image Decompression with Convolutional Networks
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- Development of a Rockfall Sensor Node
- Standard Cell Compatible Memory Array Design
- Implementing Hibernation on the ARM Cortex M0
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- EvalEDGE: A 2G Cellular Transceiver FMC
- Spatio-Temporal Video Filtering
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- High-speed Scene Labeling on FPGA
- FFT-based Convolutional Network Accelerator
- Ultrafast Medical Ultrasound imaging on a GPU
- RazorEDGE: An Evolved EDGE DBB ASIC
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Vector Processor for In-Memory Computing
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Real-Time Stereo to Multiview Conversion
- Real-Time Optical Flow Using Neural Networks
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Hardware/software co-programming on the Parallella platform
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- NORX - an AEAD algorithm for the CAESAR competition
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- FPGA-Based Digital Frontend for 3G Receivers
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- Glitches Reduce Listening Time of Your iPod
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Design and Implementation of ultra low power vision system
- Compressed Sensing Reconstruction on FPGA
